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4 * This file is part of libFirm.
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15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
29 #include "lc_opts_enum.h"
33 #include "bearch_ia32_t.h"
34 #include "ia32_architecture.h"
36 ia32_code_gen_config_t ia32_cg_config;
39 * CPU architectures and features.
41 enum cpu_arch_features {
42 arch_generic32 = 0x00000001, /**< no specific architecture */
44 arch_i386 = 0x00000002, /**< i386 architecture */
45 arch_i486 = 0x00000004, /**< i486 architecture */
46 arch_pentium = 0x00000008, /**< Pentium architecture */
47 arch_ppro = 0x00000010, /**< PentiumPro architecture */
48 arch_netburst = 0x00000020, /**< Netburst architecture */
49 arch_nocona = 0x00000040, /**< Nocona architecture */
50 arch_core2 = 0x00000080, /**< Core2 architecture */
51 arch_atom = 0x00000100, /**< Atom architecture */
53 arch_k6 = 0x00000200, /**< k6 architecture */
54 arch_geode = 0x00000400, /**< Geode architecture */
55 arch_athlon = 0x00000800, /**< Athlon architecture */
56 arch_k8 = 0x00001000, /**< K8/Opteron architecture */
57 arch_k10 = 0x00002000, /**< K10/Barcelona architecture */
59 arch_mask = 0x00003FFF,
61 arch_athlon_plus = arch_athlon | arch_k8 | arch_k10,
62 arch_all_amd = arch_k6 | arch_geode | arch_athlon_plus,
64 arch_feature_mmx = 0x00004000, /**< MMX instructions */
65 arch_feature_p6_insn = 0x00008000, /**< PentiumPro instructions */
66 arch_feature_sse1 = 0x00010000, /**< SSE1 instructions */
67 arch_feature_sse2 = 0x00020000, /**< SSE2 instructions */
68 arch_feature_sse3 = 0x00040000, /**< SSE3 instructions */
69 arch_feature_ssse3 = 0x00080000, /**< SSSE3 instructions */
70 arch_feature_3DNow = 0x00100000, /**< 3DNow! instructions */
71 arch_feature_3DNowE = 0x00200000, /**< Enhanced 3DNow! instructions */
72 arch_feature_64bit = 0x00400000, /**< x86_64 support */
73 arch_feature_sse4_1 = 0x00800000, /**< SSE4.1 instructions */
74 arch_feature_sse4_2 = 0x01000000, /**< SSE4.2 instructions */
75 arch_feature_sse4a = 0x02000000, /**< SSE4a instructions */
77 arch_mmx_insn = arch_feature_mmx, /**< MMX instructions */
78 arch_sse1_insn = arch_feature_sse1 | arch_mmx_insn, /**< SSE1 instructions, include MMX */
79 arch_sse2_insn = arch_feature_sse2 | arch_sse1_insn, /**< SSE2 instructions, include SSE1 */
80 arch_sse3_insn = arch_feature_sse3 | arch_sse2_insn, /**< SSE3 instructions, include SSE2 */
81 arch_ssse3_insn = arch_feature_ssse3 | arch_sse3_insn, /**< SSSE3 instructions, include SSE3 */
82 arch_sse4_1_insn = arch_feature_sse4_1 | arch_ssse3_insn, /**< SSE4.1 instructions, include SSSE3 */
83 arch_sse4_2_insn = arch_feature_sse4_2 | arch_sse4_1_insn, /**< SSE4.2 instructions, include SSE4.1 */
84 arch_sse4a_insn = arch_feature_sse4a | arch_ssse3_insn, /**< SSE4a instructions, include SSSE3 */
86 arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */
87 arch_3DNowE_insn = arch_feature_3DNowE | arch_3DNow_insn, /**< Enhanced 3DNow! instructions */
88 arch_64bit_insn = arch_feature_64bit | arch_sse2_insn, /**< x86_64 support, includes SSE2 */
91 #define FLAGS(x, f) (((x) & (f)) != 0)
97 cpu_generic = arch_generic32,
100 cpu_i386 = arch_i386,
101 cpu_i486 = arch_i486,
102 cpu_pentium = arch_pentium,
103 cpu_pentium_mmx = arch_pentium | arch_mmx_insn,
104 cpu_pentium_pro = arch_ppro | arch_feature_p6_insn,
105 cpu_pentium_2 = arch_ppro | arch_feature_p6_insn | arch_mmx_insn,
106 cpu_pentium_3 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn,
107 cpu_pentium_m = arch_ppro | arch_feature_p6_insn | arch_sse2_insn,
108 cpu_pentium_4 = arch_netburst | arch_feature_p6_insn | arch_sse2_insn,
109 cpu_prescott = arch_nocona | arch_feature_p6_insn | arch_sse3_insn,
110 cpu_nocona = arch_nocona | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
111 cpu_core2 = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn,
112 cpu_penryn = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_sse4_1_insn,
115 cpu_k6 = arch_k6 | arch_mmx_insn,
116 cpu_k6_PLUS = arch_k6 | arch_3DNow_insn,
117 cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn,
118 cpu_athlon_old = arch_athlon | arch_3DNowE_insn | arch_feature_p6_insn,
119 cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_p6_insn,
120 cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
121 cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
122 cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
123 cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse4a_insn,
126 cpu_winchip_c6 = arch_i486 | arch_feature_mmx,
127 cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
128 cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
129 cpu_c3_2 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn, /* really no 3DNow! */
132 static int opt_size = 0;
133 static int emit_machcode = 0;
134 static cpu_support arch = cpu_generic;
135 static cpu_support opt_arch = cpu_generic;
136 static int use_sse2 = 0;
137 static int opt_cc = 1;
138 static int opt_unsafe_floatconv = 0;
140 /* instruction set architectures. */
141 static const lc_opt_enum_int_items_t arch_items[] = {
142 { "i386", cpu_i386 },
143 { "i486", cpu_i486 },
144 { "i586", cpu_pentium },
145 { "pentium", cpu_pentium },
146 { "pentium-mmx", cpu_pentium_mmx },
147 { "i686", cpu_pentium_pro },
148 { "pentiumpro", cpu_pentium_pro },
149 { "pentium2", cpu_pentium_2 },
150 { "p2", cpu_pentium_2 },
151 { "pentium3", cpu_pentium_3 },
152 { "pentium3m", cpu_pentium_3 },
153 { "p3", cpu_pentium_3 },
154 { "pentium-m", cpu_pentium_m },
155 { "pm", cpu_pentium_m },
156 { "pentium4", cpu_pentium_4 },
157 { "pentium4m", cpu_pentium_4 },
158 { "p4", cpu_pentium_4 },
159 { "prescott", cpu_prescott },
160 { "nocona", cpu_nocona },
161 { "merom", cpu_core2 },
162 { "core2", cpu_core2 },
163 { "penryn", cpu_penryn },
166 { "k6-2", cpu_k6_PLUS },
167 { "k6-3", cpu_k6_PLUS },
168 { "geode", cpu_geode },
169 { "athlon", cpu_athlon_old },
170 { "athlon-tbird", cpu_athlon },
171 { "athlon-4", cpu_athlon },
172 { "athlon-xp", cpu_athlon },
173 { "athlon-mp", cpu_athlon },
174 { "athlon64", cpu_athlon64 },
176 { "opteron", cpu_k8 },
177 { "athlon-fx", cpu_k8 },
178 { "k8-sse3", cpu_k8_sse3 },
179 { "opteron-sse3", cpu_k8_sse3 },
181 { "barcelona", cpu_k10 },
182 { "amdfam10", cpu_k10 },
184 { "winchip-c6", cpu_winchip_c6, },
185 { "winchip2", cpu_winchip2 },
187 { "c3-2", cpu_c3_2 },
189 { "generic", cpu_generic },
190 { "generic32", cpu_generic },
194 static lc_opt_enum_int_var_t arch_var = {
195 (int*) &arch, arch_items
198 static lc_opt_enum_int_var_t opt_arch_var = {
199 (int*) &opt_arch, arch_items
202 static const lc_opt_enum_int_items_t fp_unit_items[] = {
208 static lc_opt_enum_int_var_t fp_unit_var = {
209 &use_sse2, fp_unit_items
212 static const lc_opt_table_entry_t ia32_architecture_options[] = {
213 LC_OPT_ENT_BOOL("size", "optimize for size", &opt_size),
214 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
216 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
218 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
220 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
222 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
223 "optimisations", &opt_unsafe_floatconv, 1),
224 LC_OPT_ENT_BOOL("machcode", "output machine code instead of assembler",
229 typedef struct insn_const {
230 int add_cost; /**< cost of an add instruction */
231 int lea_cost; /**< cost of a lea instruction */
232 int const_shf_cost; /**< cost of a constant shift instruction */
233 int cost_mul_start; /**< starting cost of a multiply instruction */
234 int cost_mul_bit; /**< cost of multiply for every set bit */
235 unsigned function_alignment; /**< logarithm for alignment of function labels */
236 unsigned label_alignment; /**< logarithm for alignment of loops labels */
237 unsigned label_alignment_max_skip; /**< maximum skip for alignment of loops labels */
240 /* costs for optimizing for size */
241 static const insn_const size_cost = {
242 2, /* cost of an add instruction */
243 3, /* cost of a lea instruction */
244 3, /* cost of a constant shift instruction */
245 4, /* starting cost of a multiply instruction */
246 0, /* cost of multiply for every set bit */
247 0, /* logarithm for alignment of function labels */
248 0, /* logarithm for alignment of loops labels */
249 0, /* maximum skip for alignment of loops labels */
252 /* costs for the i386 */
253 static const insn_const i386_cost = {
254 1, /* cost of an add instruction */
255 1, /* cost of a lea instruction */
256 3, /* cost of a constant shift instruction */
257 9, /* starting cost of a multiply instruction */
258 1, /* cost of multiply for every set bit */
259 2, /* logarithm for alignment of function labels */
260 2, /* logarithm for alignment of loops labels */
261 3, /* maximum skip for alignment of loops labels */
264 /* costs for the i486 */
265 static const insn_const i486_cost = {
266 1, /* cost of an add instruction */
267 1, /* cost of a lea instruction */
268 2, /* cost of a constant shift instruction */
269 12, /* starting cost of a multiply instruction */
270 1, /* cost of multiply for every set bit */
271 4, /* logarithm for alignment of function labels */
272 4, /* logarithm for alignment of loops labels */
273 15, /* maximum skip for alignment of loops labels */
276 /* costs for the Pentium */
277 static const insn_const pentium_cost = {
278 1, /* cost of an add instruction */
279 1, /* cost of a lea instruction */
280 1, /* cost of a constant shift instruction */
281 11, /* starting cost of a multiply instruction */
282 0, /* cost of multiply for every set bit */
283 4, /* logarithm for alignment of function labels */
284 4, /* logarithm for alignment of loops labels */
285 7, /* maximum skip for alignment of loops labels */
288 /* costs for the Pentium Pro */
289 static const insn_const pentiumpro_cost = {
290 1, /* cost of an add instruction */
291 1, /* cost of a lea instruction */
292 1, /* cost of a constant shift instruction */
293 4, /* starting cost of a multiply instruction */
294 0, /* cost of multiply for every set bit */
295 4, /* logarithm for alignment of function labels */
296 4, /* logarithm for alignment of loops labels */
297 10, /* maximum skip for alignment of loops labels */
300 /* costs for the K6 */
301 static const insn_const k6_cost = {
302 1, /* cost of an add instruction */
303 2, /* cost of a lea instruction */
304 1, /* cost of a constant shift instruction */
305 3, /* starting cost of a multiply instruction */
306 0, /* cost of multiply for every set bit */
307 5, /* logarithm for alignment of function labels */
308 5, /* logarithm for alignment of loops labels */
309 7, /* maximum skip for alignment of loops labels */
312 /* costs for the Geode */
313 static const insn_const geode_cost = {
314 1, /* cost of an add instruction */
315 1, /* cost of a lea instruction */
316 1, /* cost of a constant shift instruction */
317 7, /* starting cost of a multiply instruction */
318 0, /* cost of multiply for every set bit */
319 0, /* logarithm for alignment of function labels */
320 0, /* logarithm for alignment of loops labels */
321 0, /* maximum skip for alignment of loops labels */
324 /* costs for the Athlon */
325 static const insn_const athlon_cost = {
326 1, /* cost of an add instruction */
327 2, /* cost of a lea instruction */
328 1, /* cost of a constant shift instruction */
329 5, /* starting cost of a multiply instruction */
330 0, /* cost of multiply for every set bit */
331 4, /* logarithm for alignment of function labels */
332 4, /* logarithm for alignment of loops labels */
333 7, /* maximum skip for alignment of loops labels */
336 /* costs for the Opteron/K8 */
337 static const insn_const k8_cost = {
338 1, /* cost of an add instruction */
339 2, /* cost of a lea instruction */
340 1, /* cost of a constant shift instruction */
341 3, /* starting cost of a multiply instruction */
342 0, /* cost of multiply for every set bit */
344 4, /* logarithm for alignment of function labels */
345 4, /* logarithm for alignment of loops labels */
346 7, /* maximum skip for alignment of loops labels */
354 /* costs for the K10 */
355 static const insn_const k10_cost = {
356 1, /* cost of an add instruction */
357 2, /* cost of a lea instruction */
358 1, /* cost of a constant shift instruction */
359 3, /* starting cost of a multiply instruction */
360 0, /* cost of multiply for every set bit */
361 5, /* logarithm for alignment of function labels */
362 5, /* logarithm for alignment of loops labels */
363 7, /* maximum skip for alignment of loops labels */
366 /* costs for the Pentium 4 */
367 static const insn_const netburst_cost = {
368 1, /* cost of an add instruction */
369 3, /* cost of a lea instruction */
370 4, /* cost of a constant shift instruction */
371 15, /* starting cost of a multiply instruction */
372 0, /* cost of multiply for every set bit */
373 4, /* logarithm for alignment of function labels */
374 4, /* logarithm for alignment of loops labels */
375 7, /* maximum skip for alignment of loops labels */
378 /* costs for the Nocona and Core */
379 static const insn_const nocona_cost = {
380 1, /* cost of an add instruction */
381 1, /* cost of a lea instruction */
382 1, /* cost of a constant shift instruction */
383 10, /* starting cost of a multiply instruction */
384 0, /* cost of multiply for every set bit */
385 4, /* logarithm for alignment of function labels */
386 4, /* logarithm for alignment of loops labels */
387 7, /* maximum skip for alignment of loops labels */
390 /* costs for the Core2 */
391 static const insn_const core2_cost = {
392 1, /* cost of an add instruction */
393 1, /* cost of a lea instruction */
394 1, /* cost of a constant shift instruction */
395 3, /* starting cost of a multiply instruction */
396 0, /* cost of multiply for every set bit */
397 4, /* logarithm for alignment of function labels */
398 4, /* logarithm for alignment of loops labels */
399 10, /* maximum skip for alignment of loops labels */
402 /* costs for the generic32 */
403 static const insn_const generic32_cost = {
404 1, /* cost of an add instruction */
405 2, /* cost of a lea instruction */
406 1, /* cost of a constant shift instruction */
407 4, /* starting cost of a multiply instruction */
408 0, /* cost of multiply for every set bit */
409 4, /* logarithm for alignment of function labels */
410 4, /* logarithm for alignment of loops labels */
411 7, /* maximum skip for alignment of loops labels */
414 static const insn_const *arch_costs = &generic32_cost;
416 static void set_arch_costs(void)
419 arch_costs = &size_cost;
422 switch (opt_arch & arch_mask) {
423 case arch_i386: arch_costs = &i386_cost; break;
424 case arch_i486: arch_costs = &i486_cost; break;
425 case arch_pentium: arch_costs = &pentium_cost; break;
426 case arch_ppro: arch_costs = &pentiumpro_cost; break;
427 case arch_netburst: arch_costs = &netburst_cost; break;
428 case arch_nocona: arch_costs = &nocona_cost; break;
429 case arch_core2: arch_costs = &core2_cost; break;
430 case arch_k6: arch_costs = &k6_cost; break;
431 case arch_geode: arch_costs = &geode_cost; break;
432 case arch_athlon: arch_costs = &athlon_cost; break;
433 case arch_k8: arch_costs = &k8_cost; break;
434 case arch_k10: arch_costs = &k10_cost; break;
436 case arch_generic32: arch_costs = &generic32_cost; break;
440 /* Evaluate the costs of an instruction. */
441 int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
446 cost = arch_costs->cost_mul_start;
447 if (arch_costs->cost_mul_bit > 0) {
448 char *bitstr = get_tarval_bitpattern(tv);
451 for (i = 0; bitstr[i] != '\0'; ++i) {
452 if (bitstr[i] == '1') {
453 cost += arch_costs->cost_mul_bit;
460 return arch_costs->lea_cost;
463 return arch_costs->add_cost;
465 return arch_costs->const_shf_cost;
467 return arch_costs->add_cost;
473 void ia32_setup_cg_config(void)
475 ia32_code_gen_config_t *const c = &ia32_cg_config;
476 memset(c, 0, sizeof(*c));
480 c->optimize_size = opt_size != 0;
481 /* on newer intel cpus mov, pop is often faster than leave although it has a
483 c->use_leave = FLAGS(opt_arch, arch_i386 | arch_all_amd | arch_core2) || opt_size;
484 /* P4s don't like inc/decs because they only partially write the flags
485 * register which produces false dependencies */
486 c->use_incdec = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
487 c->use_sse2 = use_sse2 && FLAGS(arch, arch_feature_sse2);
488 c->use_ffreep = FLAGS(opt_arch, arch_athlon_plus);
489 c->use_ftst = !FLAGS(arch, arch_feature_p6_insn);
490 /* valgrind can't cope with femms yet and the usefulness of the optimization
491 * is questionable anyway */
493 c->use_femms = FLAGS(opt_arch, arch_athlon_plus) &&
494 FLAGS(arch, arch_feature_mmx | arch_all_amd);
498 c->use_fucomi = FLAGS(arch, arch_feature_p6_insn);
499 c->use_cmov = FLAGS(arch, arch_feature_p6_insn);
500 c->use_modeD_moves = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode);
501 c->use_add_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_geode) && !opt_size;
502 c->use_add_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode | arch_i386 | arch_i486) && !opt_size;
503 c->use_sub_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro) && !opt_size;
504 c->use_sub_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_i386 | arch_i486) && !opt_size;
505 c->use_imul_mem_imm32 = !FLAGS(opt_arch, arch_k8 | arch_k10) || opt_size;
506 c->use_pxor = FLAGS(opt_arch, arch_netburst);
507 c->use_mov_0 = FLAGS(opt_arch, arch_k6) && !opt_size;
508 c->use_short_sex_eax = !FLAGS(opt_arch, arch_k6) && !opt_size;
509 c->use_pad_return = FLAGS(opt_arch, arch_athlon_plus | arch_core2 | arch_generic32) && !opt_size;
510 c->use_bt = FLAGS(opt_arch, arch_core2 | arch_athlon_plus) || opt_size;
511 c->use_fisttp = FLAGS(opt_arch & arch, arch_feature_sse3);
512 c->use_sse_prefetch = FLAGS(arch, (arch_feature_3DNowE | arch_feature_sse1));
513 c->use_3dnow_prefetch = FLAGS(arch, arch_feature_3DNow);
514 c->use_popcnt = FLAGS(arch, (arch_feature_sse4_2 | arch_feature_sse4a));
515 c->use_i486 = (arch & arch_mask) >= arch_i486;
516 c->optimize_cc = opt_cc;
517 c->use_unsafe_floatconv = opt_unsafe_floatconv;
518 c->emit_machcode = emit_machcode;
520 c->function_alignment = arch_costs->function_alignment;
521 c->label_alignment = arch_costs->label_alignment;
522 c->label_alignment_max_skip = arch_costs->label_alignment_max_skip;
524 c->label_alignment_factor =
525 FLAGS(opt_arch, arch_i386 | arch_i486) || opt_size ? 0 :
526 opt_arch & arch_all_amd ? 3 :
530 void ia32_init_architecture(void)
532 lc_opt_entry_t *be_grp, *ia32_grp;
534 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
536 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
537 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
539 lc_opt_add_table(ia32_grp, ia32_architecture_options);