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15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
29 #include "lc_opts_enum.h"
33 #include "bearch_ia32_t.h"
34 #include "ia32_architecture.h"
36 ia32_code_gen_config_t ia32_cg_config;
39 * CPU architectures and features.
41 enum cpu_arch_features {
42 arch_generic32 = 0x00000001, /**< no specific architecture */
44 arch_i386 = 0x00000002, /**< i386 architecture */
45 arch_i486 = 0x00000004, /**< i486 architecture */
46 arch_pentium = 0x00000008, /**< Pentium architecture */
47 arch_ppro = 0x00000010, /**< PentiumPro architecture */
48 arch_netburst = 0x00000020, /**< Netburst architecture */
49 arch_nocona = 0x00000040, /**< Nocona architecture */
50 arch_core2 = 0x00000080, /**< Core2 architecture */
51 arch_atom = 0x00000100, /**< Atom architecture */
53 arch_k6 = 0x00000200, /**< k6 architecture */
54 arch_geode = 0x00000400, /**< Geode architecture */
55 arch_athlon = 0x00000800, /**< Athlon architecture */
56 arch_k8 = 0x00001000, /**< K8/Opteron architecture */
57 arch_k10 = 0x00002000, /**< K10/Barcelona architecture */
59 arch_mask = 0x00003FFF,
61 arch_athlon_plus = arch_athlon | arch_k8 | arch_k10,
62 arch_all_amd = arch_k6 | arch_geode | arch_athlon_plus,
64 arch_feature_mmx = 0x00004000, /**< MMX instructions */
65 arch_feature_p6_insn = 0x00008000, /**< PentiumPro instructions */
66 arch_feature_sse1 = 0x00010000, /**< SSE1 instructions */
67 arch_feature_sse2 = 0x00020000, /**< SSE2 instructions */
68 arch_feature_sse3 = 0x00040000, /**< SSE3 instructions */
69 arch_feature_ssse3 = 0x00080000, /**< SSSE3 instructions */
70 arch_feature_3DNow = 0x00100000, /**< 3DNow! instructions */
71 arch_feature_3DNowE = 0x00200000, /**< Enhanced 3DNow! instructions */
72 arch_feature_64bit = 0x00400000, /**< x86_64 support */
74 arch_mmx_insn = arch_feature_mmx, /**< MMX instructions */
75 arch_sse1_insn = arch_feature_sse1 | arch_mmx_insn, /**< SSE1 instructions, include MMX */
76 arch_sse2_insn = arch_feature_sse2 | arch_sse1_insn, /**< SSE2 instructions, include SSE1 */
77 arch_sse3_insn = arch_feature_sse3 | arch_sse2_insn, /**< SSE3 instructions, include SSE2 */
78 arch_ssse3_insn = arch_feature_ssse3 | arch_sse3_insn, /**< SSSE3 instructions, include SSE3 */
80 arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */
81 arch_3DNowE_insn = arch_feature_3DNowE | arch_3DNow_insn, /**< Enhanced 3DNow! instructions */
82 arch_64bit_insn = arch_feature_64bit | arch_sse2_insn, /**< x86_64 support, includes SSE2 */
85 #define FLAGS(x, f) (((x) & (f)) != 0)
91 cpu_generic = arch_generic32,
96 cpu_pentium = arch_pentium,
97 cpu_pentium_mmx = arch_pentium | arch_mmx_insn,
98 cpu_pentium_pro = arch_ppro | arch_feature_p6_insn,
99 cpu_pentium_2 = arch_ppro | arch_feature_p6_insn | arch_mmx_insn,
100 cpu_pentium_3 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn,
101 cpu_pentium_m = arch_ppro | arch_feature_p6_insn | arch_sse2_insn,
102 cpu_pentium_4 = arch_netburst | arch_feature_p6_insn | arch_sse2_insn,
103 cpu_prescott = arch_nocona | arch_feature_p6_insn | arch_sse3_insn,
104 cpu_nocona = arch_nocona | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
105 cpu_core2 = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn,
108 cpu_k6 = arch_k6 | arch_mmx_insn,
109 cpu_k6_PLUS = arch_k6 | arch_3DNow_insn,
110 cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn,
111 cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_p6_insn,
112 cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
113 cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
114 cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
115 cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
118 cpu_winchip_c6 = arch_i486 | arch_feature_mmx,
119 cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
120 cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
121 cpu_c3_2 = arch_ppro | arch_sse1_insn, /* really no 3DNow! */
124 static int opt_size = 0;
125 static cpu_support arch = cpu_generic;
126 static cpu_support opt_arch = cpu_generic;
127 static int use_sse2 = 0;
128 static int opt_cc = 1;
129 static int opt_unsafe_floatconv = 0;
131 /* instruction set architectures. */
132 static const lc_opt_enum_int_items_t arch_items[] = {
133 { "i386", cpu_i386 },
134 { "i486", cpu_i486 },
135 { "i586", cpu_pentium },
136 { "pentium", cpu_pentium },
137 { "pentium-mmx", cpu_pentium_mmx },
138 { "i686", cpu_pentium_pro },
139 { "pentiumpro", cpu_pentium_pro },
140 { "pentium2", cpu_pentium_2 },
141 { "p2", cpu_pentium_2 },
142 { "pentium3", cpu_pentium_3 },
143 { "pentium3m", cpu_pentium_3 },
144 { "p3", cpu_pentium_3 },
145 { "pentium-m", cpu_pentium_m },
146 { "pm", cpu_pentium_m },
147 { "pentium4", cpu_pentium_4 },
148 { "pentium4m", cpu_pentium_4 },
149 { "p4", cpu_pentium_4 },
150 { "prescott", cpu_prescott },
151 { "nocona", cpu_nocona },
152 { "merom", cpu_core2 },
153 { "core2", cpu_core2 },
156 { "k6-2", cpu_k6_PLUS },
157 { "k6-3", cpu_k6_PLUS },
158 { "geode", cpu_geode },
159 { "athlon", cpu_athlon },
160 { "athlon-tbird", cpu_athlon },
161 { "athlon-4", cpu_athlon },
162 { "athlon-xp", cpu_athlon },
163 { "athlon-mp", cpu_athlon },
164 { "athlon64", cpu_athlon64 },
166 { "opteron", cpu_k8 },
167 { "athlon-fx", cpu_k8 },
168 { "k8-sse3", cpu_k8_sse3 },
169 { "opteron-sse3", cpu_k8_sse3 },
171 { "barcelona", cpu_k10 },
172 { "amdfam10", cpu_k10 },
174 { "winchip-c6", cpu_winchip_c6, },
175 { "winchip2", cpu_winchip2 },
177 { "c3-2", cpu_c3_2 },
179 { "generic", cpu_generic },
180 { "generic32", cpu_generic },
184 static lc_opt_enum_int_var_t arch_var = {
185 (int*) &arch, arch_items
188 static lc_opt_enum_int_var_t opt_arch_var = {
189 (int*) &opt_arch, arch_items
192 static const lc_opt_enum_int_items_t fp_unit_items[] = {
198 static lc_opt_enum_int_var_t fp_unit_var = {
199 &use_sse2, fp_unit_items
202 static const lc_opt_table_entry_t ia32_architecture_options[] = {
203 LC_OPT_ENT_BOOL("size", "optimize for size", &opt_size),
204 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
206 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
208 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
210 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
212 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
213 "optimisations", &opt_unsafe_floatconv, 1),
217 typedef struct insn_const {
218 int add_cost; /**< cost of an add instruction */
219 int lea_cost; /**< cost of a lea instruction */
220 int const_shf_cost; /**< cost of a constant shift instruction */
221 int cost_mul_start; /**< starting cost of a multiply instruction */
222 int cost_mul_bit; /**< cost of multiply for every set bit */
223 unsigned function_alignment; /**< logarithm for alignment of function labels */
224 unsigned label_alignment; /**< logarithm for alignment of loops labels */
225 unsigned label_alignment_max_skip; /**< maximum skip for alignment of loops labels */
228 /* costs for optimizing for size */
229 static const insn_const size_cost = {
230 2, /* cost of an add instruction */
231 3, /* cost of a lea instruction */
232 3, /* cost of a constant shift instruction */
233 4, /* starting cost of a multiply instruction */
234 0, /* cost of multiply for every set bit */
235 0, /* logarithm for alignment of function labels */
236 0, /* logarithm for alignment of loops labels */
237 0, /* maximum skip for alignment of loops labels */
240 /* costs for the i386 */
241 static const insn_const i386_cost = {
242 1, /* cost of an add instruction */
243 1, /* cost of a lea instruction */
244 3, /* cost of a constant shift instruction */
245 9, /* starting cost of a multiply instruction */
246 1, /* cost of multiply for every set bit */
247 2, /* logarithm for alignment of function labels */
248 2, /* logarithm for alignment of loops labels */
249 3, /* maximum skip for alignment of loops labels */
252 /* costs for the i486 */
253 static const insn_const i486_cost = {
254 1, /* cost of an add instruction */
255 1, /* cost of a lea instruction */
256 2, /* cost of a constant shift instruction */
257 12, /* starting cost of a multiply instruction */
258 1, /* cost of multiply for every set bit */
259 4, /* logarithm for alignment of function labels */
260 4, /* logarithm for alignment of loops labels */
261 15, /* maximum skip for alignment of loops labels */
264 /* costs for the Pentium */
265 static const insn_const pentium_cost = {
266 1, /* cost of an add instruction */
267 1, /* cost of a lea instruction */
268 1, /* cost of a constant shift instruction */
269 11, /* starting cost of a multiply instruction */
270 0, /* cost of multiply for every set bit */
271 4, /* logarithm for alignment of function labels */
272 4, /* logarithm for alignment of loops labels */
273 7, /* maximum skip for alignment of loops labels */
276 /* costs for the Pentium Pro */
277 static const insn_const pentiumpro_cost = {
278 1, /* cost of an add instruction */
279 1, /* cost of a lea instruction */
280 1, /* cost of a constant shift instruction */
281 4, /* starting cost of a multiply instruction */
282 0, /* cost of multiply for every set bit */
283 4, /* logarithm for alignment of function labels */
284 4, /* logarithm for alignment of loops labels */
285 10, /* maximum skip for alignment of loops labels */
288 /* costs for the K6 */
289 static const insn_const k6_cost = {
290 1, /* cost of an add instruction */
291 2, /* cost of a lea instruction */
292 1, /* cost of a constant shift instruction */
293 3, /* starting cost of a multiply instruction */
294 0, /* cost of multiply for every set bit */
295 5, /* logarithm for alignment of function labels */
296 5, /* logarithm for alignment of loops labels */
297 7, /* maximum skip for alignment of loops labels */
300 /* costs for the Geode */
301 static const insn_const geode_cost = {
302 1, /* cost of an add instruction */
303 1, /* cost of a lea instruction */
304 1, /* cost of a constant shift instruction */
305 7, /* starting cost of a multiply instruction */
306 0, /* cost of multiply for every set bit */
307 0, /* logarithm for alignment of function labels */
308 0, /* logarithm for alignment of loops labels */
309 0, /* maximum skip for alignment of loops labels */
312 /* costs for the Athlon */
313 static const insn_const athlon_cost = {
314 1, /* cost of an add instruction */
315 2, /* cost of a lea instruction */
316 1, /* cost of a constant shift instruction */
317 5, /* starting cost of a multiply instruction */
318 0, /* cost of multiply for every set bit */
319 4, /* logarithm for alignment of function labels */
320 4, /* logarithm for alignment of loops labels */
321 7, /* maximum skip for alignment of loops labels */
324 /* costs for the Opteron/K8/K10 */
325 static const insn_const k8_cost = {
326 1, /* cost of an add instruction */
327 2, /* cost of a lea instruction */
328 1, /* cost of a constant shift instruction */
329 3, /* starting cost of a multiply instruction */
330 0, /* cost of multiply for every set bit */
332 4, /* logarithm for alignment of function labels */
333 4, /* logarithm for alignment of loops labels */
334 7, /* maximum skip for alignment of loops labels */
342 /* costs for the K10 */
343 static const insn_const k10_cost = {
344 1, /* cost of an add instruction */
345 2, /* cost of a lea instruction */
346 1, /* cost of a constant shift instruction */
347 3, /* starting cost of a multiply instruction */
348 0, /* cost of multiply for every set bit */
349 5, /* logarithm for alignment of function labels */
350 5, /* logarithm for alignment of loops labels */
351 7, /* maximum skip for alignment of loops labels */
354 /* costs for the Pentium 4 */
355 static const insn_const netburst_cost = {
356 1, /* cost of an add instruction */
357 3, /* cost of a lea instruction */
358 4, /* cost of a constant shift instruction */
359 15, /* starting cost of a multiply instruction */
360 0, /* cost of multiply for every set bit */
361 4, /* logarithm for alignment of function labels */
362 4, /* logarithm for alignment of loops labels */
363 7, /* maximum skip for alignment of loops labels */
366 /* costs for the Nocona and Core */
367 static const insn_const nocona_cost = {
368 1, /* cost of an add instruction */
369 1, /* cost of a lea instruction */
370 1, /* cost of a constant shift instruction */
371 10, /* starting cost of a multiply instruction */
372 0, /* cost of multiply for every set bit */
373 4, /* logarithm for alignment of function labels */
374 4, /* logarithm for alignment of loops labels */
375 7, /* maximum skip for alignment of loops labels */
378 /* costs for the Core2 */
379 static const insn_const core2_cost = {
380 1, /* cost of an add instruction */
381 1, /* cost of a lea instruction */
382 1, /* cost of a constant shift instruction */
383 3, /* starting cost of a multiply instruction */
384 0, /* cost of multiply for every set bit */
385 4, /* logarithm for alignment of function labels */
386 4, /* logarithm for alignment of loops labels */
387 10, /* maximum skip for alignment of loops labels */
390 /* costs for the generic32 */
391 static const insn_const generic32_cost = {
392 1, /* cost of an add instruction */
393 2, /* cost of a lea instruction */
394 1, /* cost of a constant shift instruction */
395 4, /* starting cost of a multiply instruction */
396 0, /* cost of multiply for every set bit */
397 4, /* logarithm for alignment of function labels */
398 4, /* logarithm for alignment of loops labels */
399 7, /* maximum skip for alignment of loops labels */
402 static const insn_const *arch_costs = &generic32_cost;
404 static void set_arch_costs(void)
407 arch_costs = &size_cost;
410 switch (opt_arch & arch_mask) {
412 arch_costs = &i386_cost;
415 arch_costs = &i486_cost;
418 arch_costs = &pentium_cost;
421 arch_costs = &pentiumpro_cost;
424 arch_costs = &netburst_cost;
427 arch_costs = &nocona_cost;
430 arch_costs = &core2_cost;
433 arch_costs = &k6_cost;
436 arch_costs = &geode_cost;
439 arch_costs = &athlon_cost;
442 arch_costs = &k8_cost;
445 arch_costs = &k10_cost;
449 arch_costs = &generic32_cost;
453 /* Evaluate the costs of an instruction. */
454 int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
459 cost = arch_costs->cost_mul_start;
460 if (arch_costs->cost_mul_bit > 0) {
461 char *bitstr = get_tarval_bitpattern(tv);
464 for (i = 0; bitstr[i] != '\0'; ++i) {
465 if (bitstr[i] == '1') {
466 cost += arch_costs->cost_mul_bit;
473 return arch_costs->lea_cost;
476 return arch_costs->add_cost;
478 return arch_costs->const_shf_cost;
480 return arch_costs->add_cost;
486 void ia32_setup_cg_config(void)
488 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
492 ia32_cg_config.optimize_size = opt_size != 0;
493 /* on newer intel cpus mov, pop is often faster then leave although it has a
495 ia32_cg_config.use_leave = FLAGS(opt_arch, arch_i386 | arch_all_amd | arch_core2) || opt_size;
496 /* P4s don't like inc/decs because they only partially write the flags
497 register which produces false dependencies */
498 ia32_cg_config.use_incdec = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
499 ia32_cg_config.use_sse2 = use_sse2 && FLAGS(arch, arch_feature_sse2);
500 ia32_cg_config.use_ffreep = FLAGS(opt_arch, arch_athlon_plus);
501 ia32_cg_config.use_ftst = !FLAGS(arch, arch_feature_p6_insn);
502 /* valgrind can't cope with femms yet and the usefulness of the optimization is questionable anyway */
504 ia32_cg_config.use_femms = FLAGS(opt_arch, arch_athlon_plus) &&
505 FLAGS(arch, arch_feature_mmx | arch_all_amd);
507 ia32_cg_config.use_femms = 0;
509 ia32_cg_config.use_fucomi = FLAGS(arch, arch_feature_p6_insn);
510 ia32_cg_config.use_cmov = FLAGS(arch, arch_feature_p6_insn);
511 ia32_cg_config.use_modeD_moves = FLAGS(opt_arch, arch_athlon_plus | arch_geode | arch_ppro |
512 arch_netburst | arch_nocona | arch_core2 | arch_generic32);
513 ia32_cg_config.use_add_esp_4 = FLAGS(opt_arch, arch_geode | arch_athlon_plus |
514 arch_netburst | arch_nocona | arch_core2 | arch_generic32) &&
516 ia32_cg_config.use_add_esp_8 = FLAGS(opt_arch, arch_geode | arch_athlon_plus |
517 arch_i386 | arch_i486 | arch_ppro | arch_netburst |
518 arch_nocona | arch_core2 | arch_generic32) &&
520 ia32_cg_config.use_sub_esp_4 = FLAGS(opt_arch, arch_athlon_plus | arch_ppro |
521 arch_netburst | arch_nocona | arch_core2 | arch_generic32) &&
523 ia32_cg_config.use_sub_esp_8 = FLAGS(opt_arch, arch_athlon_plus | arch_i386 | arch_i486 |
524 arch_ppro | arch_netburst | arch_nocona | arch_core2 | arch_generic32) &&
526 ia32_cg_config.use_imul_mem_imm32 = !FLAGS(opt_arch, arch_k8 | arch_k10) || opt_size;
527 ia32_cg_config.use_pxor = FLAGS(opt_arch, arch_netburst);
528 ia32_cg_config.use_mov_0 = FLAGS(opt_arch, arch_k6) && !opt_size;
529 ia32_cg_config.use_pad_return = FLAGS(opt_arch, arch_athlon_plus | arch_core2 | arch_generic32) && !opt_size;
530 ia32_cg_config.use_bt = FLAGS(opt_arch, arch_core2 | arch_athlon_plus) || opt_size;
531 ia32_cg_config.use_fisttp = FLAGS(opt_arch & arch, arch_feature_sse3);
532 ia32_cg_config.optimize_cc = opt_cc;
533 ia32_cg_config.use_unsafe_floatconv = opt_unsafe_floatconv;
535 ia32_cg_config.function_alignment = arch_costs->function_alignment;
536 ia32_cg_config.label_alignment = arch_costs->label_alignment;
537 ia32_cg_config.label_alignment_max_skip = arch_costs->label_alignment_max_skip;
539 if (opt_arch & (arch_i386 | arch_i486) || opt_size) {
540 ia32_cg_config.label_alignment_factor = 0;
541 } else if (opt_arch & arch_all_amd) {
542 ia32_cg_config.label_alignment_factor = 3;
544 ia32_cg_config.label_alignment_factor = 2;
548 void ia32_init_architecture(void)
550 lc_opt_entry_t *be_grp, *ia32_grp;
552 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
554 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
555 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
557 lc_opt_add_table(ia32_grp, ia32_architecture_options);