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4 * This file is part of libFirm.
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13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief ia32 architecture variants
23 * @author Michael Beck, Matthias Braun
24 * @version $Id: bearch_ia32_t.h 16363 2007-10-25 23:27:07Z beck $
29 #include "lc_opts_enum.h"
33 #include "bearch_ia32_t.h"
34 #include "ia32_architecture.h"
36 ia32_code_gen_config_t ia32_cg_config;
39 * CPU architectures and features.
41 enum cpu_arch_features {
42 arch_generic32 = 0x00000001, /**< no specific architecture */
44 arch_i386 = 0x00000002, /**< i386 architecture */
45 arch_i486 = 0x00000004, /**< i486 architecture */
46 arch_pentium = 0x00000008, /**< Pentium architecture */
47 arch_ppro = 0x00000010, /**< PentiumPro architecture */
48 arch_netburst = 0x00000020, /**< Netburst architecture */
49 arch_nocona = 0x00000040, /**< Nocona architecture */
50 arch_core2 = 0x00000080, /**< Core2 architecture */
51 arch_atom = 0x00000100, /**< Atom architecture */
53 arch_k6 = 0x00000200, /**< k6 architecture */
54 arch_geode = 0x00000400, /**< Geode architecture */
55 arch_athlon = 0x00000800, /**< Athlon architecture */
56 arch_k8 = 0x00001000, /**< K8/Opteron architecture */
57 arch_k10 = 0x00002000, /**< K10/Barcelona architecture */
59 arch_mask = 0x00003FFF,
61 arch_athlon_plus = arch_athlon | arch_k8 | arch_k10,
62 arch_all_amd = arch_k6 | arch_geode | arch_athlon_plus,
64 arch_feature_mmx = 0x00004000, /**< MMX instructions */
65 arch_feature_p6_insn = 0x00008000, /**< PentiumPro instructions */
66 arch_feature_sse1 = 0x00010000, /**< SSE1 instructions */
67 arch_feature_sse2 = 0x00020000, /**< SSE2 instructions */
68 arch_feature_sse3 = 0x00040000, /**< SSE3 instructions */
69 arch_feature_ssse3 = 0x00080000, /**< SSSE3 instructions */
70 arch_feature_3DNow = 0x00100000, /**< 3DNow! instructions */
71 arch_feature_3DNowE = 0x00200000, /**< Enhanced 3DNow! instructions */
72 arch_feature_64bit = 0x00400000, /**< x86_64 support */
73 arch_feature_sse4_1 = 0x00800000, /**< SSE4.1 instructions */
74 arch_feature_sse4_2 = 0x01000000, /**< SSE4.2 instructions */
75 arch_feature_sse4a = 0x02000000, /**< SSE4a instructions */
77 arch_mmx_insn = arch_feature_mmx, /**< MMX instructions */
78 arch_sse1_insn = arch_feature_sse1 | arch_mmx_insn, /**< SSE1 instructions, include MMX */
79 arch_sse2_insn = arch_feature_sse2 | arch_sse1_insn, /**< SSE2 instructions, include SSE1 */
80 arch_sse3_insn = arch_feature_sse3 | arch_sse2_insn, /**< SSE3 instructions, include SSE2 */
81 arch_ssse3_insn = arch_feature_ssse3 | arch_sse3_insn, /**< SSSE3 instructions, include SSE3 */
82 arch_sse4_1_insn = arch_feature_sse4_1 | arch_ssse3_insn, /**< SSE4.1 instructions, include SSSE3 */
83 arch_sse4_2_insn = arch_feature_sse4_2 | arch_sse4_1_insn, /**< SSE4.2 instructions, include SSE4.1 */
84 arch_sse4a_insn = arch_feature_sse4a | arch_ssse3_insn, /**< SSE4a instructions, include SSSE3 */
86 arch_3DNow_insn = arch_feature_3DNow | arch_feature_mmx, /**< 3DNow! instructions, including MMX */
87 arch_3DNowE_insn = arch_feature_3DNowE | arch_3DNow_insn, /**< Enhanced 3DNow! instructions */
88 arch_64bit_insn = arch_feature_64bit | arch_sse2_insn, /**< x86_64 support, includes SSE2 */
91 #define FLAGS(x, f) (((x) & (f)) != 0)
97 cpu_generic = arch_generic32,
100 cpu_i386 = arch_i386,
101 cpu_i486 = arch_i486,
102 cpu_pentium = arch_pentium,
103 cpu_pentium_mmx = arch_pentium | arch_mmx_insn,
104 cpu_pentium_pro = arch_ppro | arch_feature_p6_insn,
105 cpu_pentium_2 = arch_ppro | arch_feature_p6_insn | arch_mmx_insn,
106 cpu_pentium_3 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn,
107 cpu_pentium_m = arch_ppro | arch_feature_p6_insn | arch_sse2_insn,
108 cpu_pentium_4 = arch_netburst | arch_feature_p6_insn | arch_sse2_insn,
109 cpu_prescott = arch_nocona | arch_feature_p6_insn | arch_sse3_insn,
110 cpu_nocona = arch_nocona | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
111 cpu_core2 = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_ssse3_insn,
112 cpu_penryn = arch_core2 | arch_feature_p6_insn | arch_64bit_insn | arch_sse4_1_insn,
115 cpu_k6 = arch_k6 | arch_mmx_insn,
116 cpu_k6_PLUS = arch_k6 | arch_3DNow_insn,
117 cpu_geode = arch_geode | arch_sse1_insn | arch_3DNowE_insn,
118 cpu_athlon_old = arch_athlon | arch_3DNowE_insn | arch_feature_p6_insn,
119 cpu_athlon = arch_athlon | arch_sse1_insn | arch_3DNowE_insn | arch_feature_p6_insn,
120 cpu_athlon64 = arch_athlon | arch_sse2_insn | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
121 cpu_k8 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn,
122 cpu_k8_sse3 = arch_k8 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse3_insn,
123 cpu_k10 = arch_k10 | arch_3DNowE_insn | arch_feature_p6_insn | arch_64bit_insn | arch_sse4a_insn,
126 cpu_winchip_c6 = arch_i486 | arch_feature_mmx,
127 cpu_winchip2 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
128 cpu_c3 = arch_i486 | arch_feature_mmx | arch_feature_3DNow,
129 cpu_c3_2 = arch_ppro | arch_feature_p6_insn | arch_sse1_insn, /* really no 3DNow! */
132 static int opt_size = 0;
133 static cpu_support arch = cpu_generic;
134 static cpu_support opt_arch = cpu_generic;
135 static int use_sse2 = 0;
136 static int opt_cc = 1;
137 static int opt_unsafe_floatconv = 0;
139 /* instruction set architectures. */
140 static const lc_opt_enum_int_items_t arch_items[] = {
141 { "i386", cpu_i386 },
142 { "i486", cpu_i486 },
143 { "i586", cpu_pentium },
144 { "pentium", cpu_pentium },
145 { "pentium-mmx", cpu_pentium_mmx },
146 { "i686", cpu_pentium_pro },
147 { "pentiumpro", cpu_pentium_pro },
148 { "pentium2", cpu_pentium_2 },
149 { "p2", cpu_pentium_2 },
150 { "pentium3", cpu_pentium_3 },
151 { "pentium3m", cpu_pentium_3 },
152 { "p3", cpu_pentium_3 },
153 { "pentium-m", cpu_pentium_m },
154 { "pm", cpu_pentium_m },
155 { "pentium4", cpu_pentium_4 },
156 { "pentium4m", cpu_pentium_4 },
157 { "p4", cpu_pentium_4 },
158 { "prescott", cpu_prescott },
159 { "nocona", cpu_nocona },
160 { "merom", cpu_core2 },
161 { "core2", cpu_core2 },
162 { "penryn", cpu_penryn },
165 { "k6-2", cpu_k6_PLUS },
166 { "k6-3", cpu_k6_PLUS },
167 { "geode", cpu_geode },
168 { "athlon", cpu_athlon_old },
169 { "athlon-tbird", cpu_athlon },
170 { "athlon-4", cpu_athlon },
171 { "athlon-xp", cpu_athlon },
172 { "athlon-mp", cpu_athlon },
173 { "athlon64", cpu_athlon64 },
175 { "opteron", cpu_k8 },
176 { "athlon-fx", cpu_k8 },
177 { "k8-sse3", cpu_k8_sse3 },
178 { "opteron-sse3", cpu_k8_sse3 },
180 { "barcelona", cpu_k10 },
181 { "amdfam10", cpu_k10 },
183 { "winchip-c6", cpu_winchip_c6, },
184 { "winchip2", cpu_winchip2 },
186 { "c3-2", cpu_c3_2 },
188 { "generic", cpu_generic },
189 { "generic32", cpu_generic },
193 static lc_opt_enum_int_var_t arch_var = {
194 (int*) &arch, arch_items
197 static lc_opt_enum_int_var_t opt_arch_var = {
198 (int*) &opt_arch, arch_items
201 static const lc_opt_enum_int_items_t fp_unit_items[] = {
207 static lc_opt_enum_int_var_t fp_unit_var = {
208 &use_sse2, fp_unit_items
211 static const lc_opt_table_entry_t ia32_architecture_options[] = {
212 LC_OPT_ENT_BOOL("size", "optimize for size", &opt_size),
213 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture",
215 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture",
217 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit",
219 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention",
221 LC_OPT_ENT_BIT("unsafe_floatconv", "do unsafe floating point controlword "
222 "optimisations", &opt_unsafe_floatconv, 1),
226 typedef struct insn_const {
227 int add_cost; /**< cost of an add instruction */
228 int lea_cost; /**< cost of a lea instruction */
229 int const_shf_cost; /**< cost of a constant shift instruction */
230 int cost_mul_start; /**< starting cost of a multiply instruction */
231 int cost_mul_bit; /**< cost of multiply for every set bit */
232 unsigned function_alignment; /**< logarithm for alignment of function labels */
233 unsigned label_alignment; /**< logarithm for alignment of loops labels */
234 unsigned label_alignment_max_skip; /**< maximum skip for alignment of loops labels */
237 /* costs for optimizing for size */
238 static const insn_const size_cost = {
239 2, /* cost of an add instruction */
240 3, /* cost of a lea instruction */
241 3, /* cost of a constant shift instruction */
242 4, /* starting cost of a multiply instruction */
243 0, /* cost of multiply for every set bit */
244 0, /* logarithm for alignment of function labels */
245 0, /* logarithm for alignment of loops labels */
246 0, /* maximum skip for alignment of loops labels */
249 /* costs for the i386 */
250 static const insn_const i386_cost = {
251 1, /* cost of an add instruction */
252 1, /* cost of a lea instruction */
253 3, /* cost of a constant shift instruction */
254 9, /* starting cost of a multiply instruction */
255 1, /* cost of multiply for every set bit */
256 2, /* logarithm for alignment of function labels */
257 2, /* logarithm for alignment of loops labels */
258 3, /* maximum skip for alignment of loops labels */
261 /* costs for the i486 */
262 static const insn_const i486_cost = {
263 1, /* cost of an add instruction */
264 1, /* cost of a lea instruction */
265 2, /* cost of a constant shift instruction */
266 12, /* starting cost of a multiply instruction */
267 1, /* cost of multiply for every set bit */
268 4, /* logarithm for alignment of function labels */
269 4, /* logarithm for alignment of loops labels */
270 15, /* maximum skip for alignment of loops labels */
273 /* costs for the Pentium */
274 static const insn_const pentium_cost = {
275 1, /* cost of an add instruction */
276 1, /* cost of a lea instruction */
277 1, /* cost of a constant shift instruction */
278 11, /* starting cost of a multiply instruction */
279 0, /* cost of multiply for every set bit */
280 4, /* logarithm for alignment of function labels */
281 4, /* logarithm for alignment of loops labels */
282 7, /* maximum skip for alignment of loops labels */
285 /* costs for the Pentium Pro */
286 static const insn_const pentiumpro_cost = {
287 1, /* cost of an add instruction */
288 1, /* cost of a lea instruction */
289 1, /* cost of a constant shift instruction */
290 4, /* starting cost of a multiply instruction */
291 0, /* cost of multiply for every set bit */
292 4, /* logarithm for alignment of function labels */
293 4, /* logarithm for alignment of loops labels */
294 10, /* maximum skip for alignment of loops labels */
297 /* costs for the K6 */
298 static const insn_const k6_cost = {
299 1, /* cost of an add instruction */
300 2, /* cost of a lea instruction */
301 1, /* cost of a constant shift instruction */
302 3, /* starting cost of a multiply instruction */
303 0, /* cost of multiply for every set bit */
304 5, /* logarithm for alignment of function labels */
305 5, /* logarithm for alignment of loops labels */
306 7, /* maximum skip for alignment of loops labels */
309 /* costs for the Geode */
310 static const insn_const geode_cost = {
311 1, /* cost of an add instruction */
312 1, /* cost of a lea instruction */
313 1, /* cost of a constant shift instruction */
314 7, /* starting cost of a multiply instruction */
315 0, /* cost of multiply for every set bit */
316 0, /* logarithm for alignment of function labels */
317 0, /* logarithm for alignment of loops labels */
318 0, /* maximum skip for alignment of loops labels */
321 /* costs for the Athlon */
322 static const insn_const athlon_cost = {
323 1, /* cost of an add instruction */
324 2, /* cost of a lea instruction */
325 1, /* cost of a constant shift instruction */
326 5, /* starting cost of a multiply instruction */
327 0, /* cost of multiply for every set bit */
328 4, /* logarithm for alignment of function labels */
329 4, /* logarithm for alignment of loops labels */
330 7, /* maximum skip for alignment of loops labels */
333 /* costs for the Opteron/K8 */
334 static const insn_const k8_cost = {
335 1, /* cost of an add instruction */
336 2, /* cost of a lea instruction */
337 1, /* cost of a constant shift instruction */
338 3, /* starting cost of a multiply instruction */
339 0, /* cost of multiply for every set bit */
341 4, /* logarithm for alignment of function labels */
342 4, /* logarithm for alignment of loops labels */
343 7, /* maximum skip for alignment of loops labels */
351 /* costs for the K10 */
352 static const insn_const k10_cost = {
353 1, /* cost of an add instruction */
354 2, /* cost of a lea instruction */
355 1, /* cost of a constant shift instruction */
356 3, /* starting cost of a multiply instruction */
357 0, /* cost of multiply for every set bit */
358 5, /* logarithm for alignment of function labels */
359 5, /* logarithm for alignment of loops labels */
360 7, /* maximum skip for alignment of loops labels */
363 /* costs for the Pentium 4 */
364 static const insn_const netburst_cost = {
365 1, /* cost of an add instruction */
366 3, /* cost of a lea instruction */
367 4, /* cost of a constant shift instruction */
368 15, /* starting cost of a multiply instruction */
369 0, /* cost of multiply for every set bit */
370 4, /* logarithm for alignment of function labels */
371 4, /* logarithm for alignment of loops labels */
372 7, /* maximum skip for alignment of loops labels */
375 /* costs for the Nocona and Core */
376 static const insn_const nocona_cost = {
377 1, /* cost of an add instruction */
378 1, /* cost of a lea instruction */
379 1, /* cost of a constant shift instruction */
380 10, /* starting cost of a multiply instruction */
381 0, /* cost of multiply for every set bit */
382 4, /* logarithm for alignment of function labels */
383 4, /* logarithm for alignment of loops labels */
384 7, /* maximum skip for alignment of loops labels */
387 /* costs for the Core2 */
388 static const insn_const core2_cost = {
389 1, /* cost of an add instruction */
390 1, /* cost of a lea instruction */
391 1, /* cost of a constant shift instruction */
392 3, /* starting cost of a multiply instruction */
393 0, /* cost of multiply for every set bit */
394 4, /* logarithm for alignment of function labels */
395 4, /* logarithm for alignment of loops labels */
396 10, /* maximum skip for alignment of loops labels */
399 /* costs for the generic32 */
400 static const insn_const generic32_cost = {
401 1, /* cost of an add instruction */
402 2, /* cost of a lea instruction */
403 1, /* cost of a constant shift instruction */
404 4, /* starting cost of a multiply instruction */
405 0, /* cost of multiply for every set bit */
406 4, /* logarithm for alignment of function labels */
407 4, /* logarithm for alignment of loops labels */
408 7, /* maximum skip for alignment of loops labels */
411 static const insn_const *arch_costs = &generic32_cost;
413 static void set_arch_costs(void)
416 arch_costs = &size_cost;
419 switch (opt_arch & arch_mask) {
420 case arch_i386: arch_costs = &i386_cost; break;
421 case arch_i486: arch_costs = &i486_cost; break;
422 case arch_pentium: arch_costs = &pentium_cost; break;
423 case arch_ppro: arch_costs = &pentiumpro_cost; break;
424 case arch_netburst: arch_costs = &netburst_cost; break;
425 case arch_nocona: arch_costs = &nocona_cost; break;
426 case arch_core2: arch_costs = &core2_cost; break;
427 case arch_k6: arch_costs = &k6_cost; break;
428 case arch_geode: arch_costs = &geode_cost; break;
429 case arch_athlon: arch_costs = &athlon_cost; break;
430 case arch_k8: arch_costs = &k8_cost; break;
431 case arch_k10: arch_costs = &k10_cost; break;
433 case arch_generic32: arch_costs = &generic32_cost; break;
437 /* Evaluate the costs of an instruction. */
438 int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
443 cost = arch_costs->cost_mul_start;
444 if (arch_costs->cost_mul_bit > 0) {
445 char *bitstr = get_tarval_bitpattern(tv);
448 for (i = 0; bitstr[i] != '\0'; ++i) {
449 if (bitstr[i] == '1') {
450 cost += arch_costs->cost_mul_bit;
457 return arch_costs->lea_cost;
460 return arch_costs->add_cost;
462 return arch_costs->const_shf_cost;
464 return arch_costs->add_cost;
470 void ia32_setup_cg_config(void)
472 ia32_code_gen_config_t *const c = &ia32_cg_config;
473 memset(c, 0, sizeof(*c));
477 c->optimize_size = opt_size != 0;
478 /* on newer intel cpus mov, pop is often faster than leave although it has a
480 c->use_leave = FLAGS(opt_arch, arch_i386 | arch_all_amd | arch_core2) || opt_size;
481 /* P4s don't like inc/decs because they only partially write the flags
482 * register which produces false dependencies */
483 c->use_incdec = !FLAGS(opt_arch, arch_netburst | arch_nocona | arch_core2 | arch_geode) || opt_size;
484 c->use_sse2 = use_sse2 && FLAGS(arch, arch_feature_sse2);
485 c->use_ffreep = FLAGS(opt_arch, arch_athlon_plus);
486 c->use_ftst = !FLAGS(arch, arch_feature_p6_insn);
487 /* valgrind can't cope with femms yet and the usefulness of the optimization
488 * is questionable anyway */
490 c->use_femms = FLAGS(opt_arch, arch_athlon_plus) &&
491 FLAGS(arch, arch_feature_mmx | arch_all_amd);
495 c->use_fucomi = FLAGS(arch, arch_feature_p6_insn);
496 c->use_cmov = FLAGS(arch, arch_feature_p6_insn);
497 c->use_modeD_moves = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode);
498 c->use_add_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_geode) && !opt_size;
499 c->use_add_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_geode | arch_i386 | arch_i486) && !opt_size;
500 c->use_sub_esp_4 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro) && !opt_size;
501 c->use_sub_esp_8 = FLAGS(opt_arch, arch_generic32 | arch_athlon_plus | arch_netburst | arch_nocona | arch_core2 | arch_ppro | arch_i386 | arch_i486) && !opt_size;
502 c->use_imul_mem_imm32 = !FLAGS(opt_arch, arch_k8 | arch_k10) || opt_size;
503 c->use_pxor = FLAGS(opt_arch, arch_netburst);
504 c->use_mov_0 = FLAGS(opt_arch, arch_k6) && !opt_size;
505 c->use_short_sex_eax = !FLAGS(opt_arch, arch_k6) && !opt_size;
506 c->use_pad_return = FLAGS(opt_arch, arch_athlon_plus | arch_core2 | arch_generic32) && !opt_size;
507 c->use_bt = FLAGS(opt_arch, arch_core2 | arch_athlon_plus) || opt_size;
508 c->use_fisttp = FLAGS(opt_arch & arch, arch_feature_sse3);
509 c->use_sse_prefetch = FLAGS(arch, (arch_feature_3DNowE | arch_feature_sse1));
510 c->use_3dnow_prefetch = FLAGS(arch, arch_feature_3DNow);
511 c->use_popcnt = FLAGS(arch, (arch_feature_sse4_2 | arch_feature_sse4a));
512 c->optimize_cc = opt_cc;
513 c->use_unsafe_floatconv = opt_unsafe_floatconv;
515 c->function_alignment = arch_costs->function_alignment;
516 c->label_alignment = arch_costs->label_alignment;
517 c->label_alignment_max_skip = arch_costs->label_alignment_max_skip;
519 c->label_alignment_factor =
520 FLAGS(opt_arch, arch_i386 | arch_i486) || opt_size ? 0 :
521 opt_arch & arch_all_amd ? 3 :
525 void ia32_init_architecture(void)
527 lc_opt_entry_t *be_grp, *ia32_grp;
529 memset(&ia32_cg_config, 0, sizeof(ia32_cg_config));
531 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
532 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
534 lc_opt_add_table(ia32_grp, ia32_architecture_options);