2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
26 #ifndef FIRM_BE_IA32_BEARCH_IA32_T_H
27 #define FIRM_BE_IA32_BEARCH_IA32_T_H
29 #include "firm_config.h"
33 #include "ia32_nodes_attr.h"
38 #include "../bemachine.h"
39 #include "../beemitter.h"
42 #define SET_IA32_ORIG_NODE(n, o)
44 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
48 typedef enum ia32_optimize_t ia32_optimize_t;
49 typedef enum cpu_support cpu_support;
50 typedef enum fp_support fp_support;
53 * Bitmask for the backend optimization settings.
55 enum ia32_optimize_t {
56 IA32_OPT_INCDEC = 1 << 0, /**< optimize add/sub 1/-1 to inc/dec */
57 IA32_OPT_CC = 1 << 1, /**< optimize caling convention of private
59 IA32_OPT_UNSAFE_FLOATCONV = 1 << 2, /**< disrespect current floating
60 point rounding mode at entry and exit of
61 functions (this is ok for programs that don't
62 explicitely change the rounding mode) */
66 * Architectures. Clustered for easier macro implementation,
88 /** checks for l <= x <= h */
89 #define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
91 /** returns true if it's Intel architecture */
92 #define ARCH_INTEL(x) _IN_RANGE((x), arch_i386, arch_core)
94 /** returns true if it's AMD architecture */
95 #define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron)
97 /** return true if it's a Athlon/Opteron */
98 #define ARCH_ATHLON(x) _IN_RANGE((x), arch_athlon, arch_opteron)
100 /** return true if the CPU has MMX support */
101 #define ARCH_MMX(x) _IN_RANGE((x), arch_pentium_mmx, arch_opteron)
103 #define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \
104 _IN_RANGE((x), arch_athlon, arch_opteron))
106 /** floating point support */
108 fp_none, /**< no floating point instructions are used */
109 fp_x87, /**< use x87 instructions */
110 fp_sse2 /**< use SSE2 instructions */
113 /** Returns non-zero if the current floating point architecture is SSE2. */
114 #define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2)
116 /** Returns non-zero if the current floating point architecture is x87. */
117 #define USE_x87(cg) ((cg)->fp_kind == fp_x87)
119 typedef struct ia32_isa_t ia32_isa_t;
120 typedef struct ia32_code_gen_t ia32_code_gen_t;
121 typedef struct ia32_irn_ops_t ia32_irn_ops_t;
122 typedef struct ia32_intrinsic_env_t ia32_intrinsic_env_t;
125 * IA32 code generator
127 struct ia32_code_gen_t {
128 const arch_code_generator_if_t *impl; /**< implementation */
129 ir_graph *irg; /**< current irg */
130 const arch_env_t *arch_env; /**< the arch env */
131 set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
132 ia32_isa_t *isa; /**< for fast access to the isa object */
133 be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
134 ir_node **blk_sched; /**< an array containing the scheduled blocks */
135 ia32_optimize_t opt; /**< contains optimization information */
136 int arch; /**< instruction architecture */
137 int opt_arch; /**< optimize for architecture */
138 char fp_kind; /**< floating point kind */
139 char do_x87_sim; /**< set to 1 if x87 simulation should be enforced */
140 char dump; /**< set to 1 if graphs should be dumped */
141 ir_node *unknown_gp; /**< unique Unknown_GP node */
142 ir_node *unknown_vfp; /**< unique Unknown_VFP node */
143 ir_node *unknown_xmm; /**< unique Unknown_XMM node */
144 ir_node *noreg_gp; /**< unique NoReg_GP node */
145 ir_node *noreg_vfp; /**< unique NoReg_VFP node */
146 ir_node *noreg_xmm; /**< unique NoReg_XMM node */
148 ir_node *fpu_trunc_mode; /**< truncate fpu mode */
150 struct obstack *obst;
157 arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
158 pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */
159 pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */
160 pmap *regs_8bit_high; /**< contains the hight part of the 8 bit names of the gp registers */
161 pmap *types; /**< A map of modes to primitive types */
162 pmap *tv_ent; /**< A map of entities that store const tarvals */
163 ia32_optimize_t opt; /**< contains optimization information */
164 int arch; /**< instruction architecture */
165 int opt_arch; /**< optimize for architecture */
166 int fp_kind; /**< floating point kind */
167 ia32_code_gen_t *cg; /**< the current code generator */
168 const be_machine_t *cpu; /**< the abstract machine */
170 struct obstack *name_obst; /**< holds the original node names (for debugging) */
174 struct ia32_irn_ops_t {
175 const arch_irn_ops_if_t *impl;
180 * A helper type collecting needed info for IA32 intrinsic lowering.
182 struct ia32_intrinsic_env_t {
183 ia32_isa_t *isa; /**< the isa object */
184 ir_graph *irg; /**< the irg, these entities belong to */
185 ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */
186 ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */
187 ir_entity *ll_d_conv; /**< entity for converts ll -> d */
188 ir_entity *d_ll_conv; /**< entity for converts d -> ll */
189 ir_entity *divdi3; /**< entity for __divdi3 library call */
190 ir_entity *moddi3; /**< entity for __moddi3 library call */
191 ir_entity *udivdi3; /**< entity for __udivdi3 library call */
192 ir_entity *umoddi3; /**< entity for __umoddi3 library call */
193 tarval *u64_bias; /**< bias value for conversion from float to unsigned 64 */
196 /** The mode for the floating point control word. */
197 extern ir_mode *mode_fpcw;
199 /** The current code generator. */
200 extern ia32_code_gen_t *ia32_current_cg;
203 * Returns the unique per irg GP NoReg node.
205 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg);
206 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg);
207 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg);
210 * Returns the uniqure per irg GP Unknown node.
211 * (warning: cse has to be activated)
213 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg);
214 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg);
215 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg);
218 * Returns the unique per irg FP NoReg node.
220 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg);
223 * Returns the unique per irg FPU truncation mode node.
225 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg);
228 * Returns gp_noreg or fp_noreg, depending on input requirements.
230 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos);
233 * Maps all intrinsic calls that the backend support
234 * and map all instructions the backend did not support
237 void ia32_handle_intrinsics(void);
240 * Ia32 implementation.
242 * @param method the method type of the emulation function entity
243 * @param op the emulated ir_op
244 * @param imode the input mode of the emulated opcode
245 * @param omode the output mode of the emulated opcode
246 * @param context the context parameter
248 ir_entity *ia32_create_intrinsic_fkt(ir_type *method, const ir_op *op,
249 const ir_mode *imode, const ir_mode *omode,