1 #ifndef _BEARCH_IA32_T_H_
2 #define _BEARCH_IA32_T_H_
4 #include "firm_config.h"
8 #include "ia32_nodes_attr.h"
13 #include "../bemachine.h"
16 #define SET_IA32_ORIG_NODE(n, o)
18 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
24 * Bitmask for the backend optimization settings.
26 typedef enum _ia32_optimize_t {
27 IA32_OPT_INCDEC = 1, /**< optimize add/sub 1/-1 to inc/dec */
28 IA32_OPT_DOAM = 2, /**< do address mode optimizations */
29 IA32_OPT_LEA = 4, /**< optimize address calculations into LEAs */
30 IA32_OPT_PLACECNST = 8, /**< place constants in the blocks where they are used */
31 IA32_OPT_IMMOPS = 16, /**< create operations with immediate operands */
32 IA32_OPT_PUSHARGS = 32, /**< create pushs for function argument passing */
36 * Architectures. Clustered for easier macro implementation,
39 typedef enum cpu_support {
40 arch_i386, /**< i386 */
41 arch_i486, /**< i486 */
42 arch_pentium, /**< Pentium */
43 arch_pentium_pro, /**< Pentium Pro */
44 arch_pentium_mmx, /**< Pentium MMX */
45 arch_pentium_2, /**< Pentium II */
46 arch_pentium_3, /**< Pentium III */
47 arch_pentium_4, /**< Pentium IV */
48 arch_pentium_m, /**< Pentium M */
49 arch_core, /**< Core */
51 arch_athlon, /**< Athlon */
52 arch_athlon_64, /**< Athlon64 */
53 arch_opteron, /**< Opteron */
56 /** checks for l <= x <= h */
57 #define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
59 /** returns true if it's Intel architecture */
60 #define ARCH_INTEL(x) _IN_RANGE((x), arch_i386, arch_core)
62 /** returns true if it's AMD architecture */
63 #define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron)
65 #define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \
66 _IN_RANGE((x), arch_athlon, arch_opteron))
68 /** floating point support */
69 typedef enum fp_support {
70 fp_none, /**< no floating point instructions are used */
71 fp_x87, /**< use x87 instructions */
72 fp_sse2 /**< use SSE2 instructions */
75 /** Sets the used flag to the current floating point architecture. */
76 #define FP_USED(cg) ((cg)->used_fp = (cg)->fp_kind)
78 /** Returns non-zero if the current floating point architecture is SSE2. */
79 #define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2)
81 /** Returns non-zero if the current floating point architecture is x87. */
82 #define USE_x87(cg) ((cg)->fp_kind == fp_x87)
84 /** Sets the flag to enforce x87 simulation. */
85 #define FORCE_x87(cg) ((cg)->force_sim = 1)
87 typedef struct _ia32_isa_t ia32_isa_t;
92 typedef struct _ia32_code_gen_t {
93 const arch_code_generator_if_t *impl; /**< implementation */
94 ir_graph *irg; /**< current irg */
95 const arch_env_t *arch_env; /**< the arch env */
96 set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
97 ia32_isa_t *isa; /**< for fast access to the isa object */
98 be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
99 ir_node **blk_sched; /**< an array containing the scheduled blocks */
100 ia32_optimize_t opt; /**< contains optimization information */
101 int arch; /**< instruction architecture */
102 int opt_arch; /**< optimize for architecture */
103 char fp_kind; /**< floating point kind */
104 char used_fp; /**< which floating point unit used in this graph */
105 char force_sim; /**< set to 1 if x87 simulation should be enforced */
106 char dump; /**< set to 1 if graphs should be dumped */
107 ir_node *unknown_gp; /**< unique Unknown_GP node */
108 ir_node *unknown_vfp; /**< unique Unknown_VFP node */
109 ir_node *unknown_xmm; /**< unique Unknown_XMM node */
110 ir_node *noreg_gp; /**< unique NoReg_GP node */
111 ir_node *noreg_vfp; /**< unique NoReg_VFP node */
112 ir_node *noreg_xmm; /**< unique NoReg_XMM node */
113 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< debugging module */
120 arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
121 pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */
122 pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */
123 pmap *types; /**< A map of modes to primitive types */
124 pmap *tv_ent; /**< A map of entities that store const tarvals */
125 ia32_optimize_t opt; /**< contains optimization information */
126 int arch; /**< instruction architecture */
127 int opt_arch; /**< optimize for architecture */
128 int fp_kind; /**< floating point kind */
129 ia32_code_gen_t *cg; /**< the current code generator */
130 FILE *out; /**< output file */
131 const be_machine_t *cpu; /**< the abstract machine */
133 struct obstack *name_obst; /**< holds the original node names (for debugging) */
137 typedef struct _ia32_irn_ops_t {
138 const arch_irn_ops_if_t *impl;
142 typedef struct _ia32_intrinsic_env_t {
143 ir_graph *irg; /**< the irg, these entities belong to */
144 ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */
145 ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */
146 ir_entity *ll_d_conv; /**< entity for converts ll -> d */
147 ir_entity *d_ll_conv; /**< entity for converts d -> ll */
148 } ia32_intrinsic_env_t;
151 * Returns the unique per irg GP NoReg node.
153 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg);
154 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg);
155 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg);
158 * Returns the uniqure per irg GP Unknown node.
159 * (warning: cse has to be activated)
161 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg);
162 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg);
163 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg);
166 * Returns the unique per irg FP NoReg node.
168 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg);
171 * Returns gp_noreg or fp_noreg, depending on input requirements.
173 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos);
176 * Maps all intrinsic calls that the backend support
177 * and map all instructions the backend did not support
180 void ia32_handle_intrinsics(void);
183 * Ia32 implementation.
185 * @param method the method type of the emulation function entity
186 * @param op the emulated ir_op
187 * @param imode the input mode of the emulated opcode
188 * @param omode the output mode of the emulated opcode
189 * @param context the context parameter
191 ir_entity *ia32_create_intrinsic_fkt(ir_type *method, const ir_op *op,
192 const ir_mode *imode, const ir_mode *omode,
195 #endif /* _BEARCH_IA32_T_H_ */