2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
26 #ifndef FIRM_BE_IA32_BEARCH_IA32_T_H
27 #define FIRM_BE_IA32_BEARCH_IA32_T_H
29 #include "firm_config.h"
33 #include "ia32_nodes_attr.h"
38 #include "../bemachine.h"
39 #include "../beemitter.h"
42 #define SET_IA32_ORIG_NODE(n, o)
44 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
48 typedef enum ia32_optimize_t ia32_optimize_t;
49 typedef enum cpu_support cpu_support;
50 typedef enum fp_support fp_support;
53 * Bitmask for the backend optimization settings.
55 enum ia32_optimize_t {
56 IA32_OPT_INCDEC = 1, /**< optimize add/sub 1/-1 to inc/dec */
57 IA32_OPT_DOAM = 2, /**< do address mode optimizations */
58 IA32_OPT_LEA = 4, /**< optimize address calculations into LEAs */
59 IA32_OPT_PLACECNST = 8, /**< place constants in the blocks where they are used */
60 IA32_OPT_IMMOPS = 16, /**< create operations with immediate operands */
61 IA32_OPT_PUSHARGS = 32, /**< create pushs for function argument passing */
65 * Architectures. Clustered for easier macro implementation,
69 arch_i386, /**< i386 */
70 arch_i486, /**< i486 */
71 arch_pentium, /**< Pentium */
72 arch_pentium_pro, /**< Pentium Pro */
73 arch_pentium_mmx, /**< Pentium MMX */
74 arch_pentium_2, /**< Pentium II */
75 arch_pentium_3, /**< Pentium III */
76 arch_pentium_4, /**< Pentium IV */
77 arch_pentium_m, /**< Pentium M */
78 arch_core, /**< Core */
80 arch_athlon, /**< Athlon */
81 arch_athlon_64, /**< Athlon64 */
82 arch_opteron, /**< Opteron */
85 /** checks for l <= x <= h */
86 #define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
88 /** returns true if it's Intel architecture */
89 #define ARCH_INTEL(x) _IN_RANGE((x), arch_i386, arch_core)
91 /** returns true if it's AMD architecture */
92 #define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron)
94 #define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \
95 _IN_RANGE((x), arch_athlon, arch_opteron))
97 /** floating point support */
99 fp_none, /**< no floating point instructions are used */
100 fp_x87, /**< use x87 instructions */
101 fp_sse2 /**< use SSE2 instructions */
104 /** Sets the used flag to the current floating point architecture. */
105 #define FP_USED(cg) ((cg)->used_fp = (cg)->fp_kind)
107 /** Returns non-zero if the current floating point architecture is SSE2. */
108 #define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2)
110 /** Returns non-zero if the current floating point architecture is x87. */
111 #define USE_x87(cg) ((cg)->fp_kind == fp_x87)
113 /** Sets the flag to enforce x87 simulation. */
114 #define FORCE_x87(cg) ((cg)->force_sim = 1)
116 typedef struct ia32_isa_t ia32_isa_t;
117 typedef struct ia32_code_gen_t ia32_code_gen_t;
118 typedef struct ia32_irn_ops_t ia32_irn_ops_t;
119 typedef struct ia32_intrinsic_env_t ia32_intrinsic_env_t;
122 * IA32 code generator
124 struct ia32_code_gen_t {
125 const arch_code_generator_if_t *impl; /**< implementation */
126 ir_graph *irg; /**< current irg */
127 const arch_env_t *arch_env; /**< the arch env */
128 set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
129 ia32_isa_t *isa; /**< for fast access to the isa object */
130 be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
131 ir_node **blk_sched; /**< an array containing the scheduled blocks */
132 ia32_optimize_t opt; /**< contains optimization information */
133 int arch; /**< instruction architecture */
134 int opt_arch; /**< optimize for architecture */
135 char fp_kind; /**< floating point kind */
136 char used_fp; /**< which floating point unit used in this graph */
137 char force_sim; /**< set to 1 if x87 simulation should be enforced */
138 char dump; /**< set to 1 if graphs should be dumped */
139 ir_node *unknown_gp; /**< unique Unknown_GP node */
140 ir_node *unknown_vfp; /**< unique Unknown_VFP node */
141 ir_node *unknown_xmm; /**< unique Unknown_XMM node */
142 ir_node *noreg_gp; /**< unique NoReg_GP node */
143 ir_node *noreg_vfp; /**< unique NoReg_VFP node */
144 ir_node *noreg_xmm; /**< unique NoReg_XMM node */
146 ir_node *fpu_trunc_mode; /**< truncate fpu mode */
148 struct obstack *obst;
155 arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
157 pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */
158 pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */
159 pmap *regs_8bit_high; /**< contains the hight part of the 8 bit names of the gp registers */
160 pmap *types; /**< A map of modes to primitive types */
161 pmap *tv_ent; /**< A map of entities that store const tarvals */
162 ia32_optimize_t opt; /**< contains optimization information */
163 int arch; /**< instruction architecture */
164 int opt_arch; /**< optimize for architecture */
165 int fp_kind; /**< floating point kind */
166 ia32_code_gen_t *cg; /**< the current code generator */
167 const be_machine_t *cpu; /**< the abstract machine */
169 struct obstack *name_obst; /**< holds the original node names (for debugging) */
173 struct ia32_irn_ops_t {
174 const arch_irn_ops_if_t *impl;
178 struct ia32_intrinsic_env_t {
179 ir_graph *irg; /**< the irg, these entities belong to */
180 ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */
181 ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */
182 ir_entity *ll_d_conv; /**< entity for converts ll -> d */
183 ir_entity *d_ll_conv; /**< entity for converts d -> ll */
186 /** mode for the floating point control word */
187 extern ir_mode *mode_fpcw;
190 * Returns the unique per irg GP NoReg node.
192 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg);
193 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg);
194 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg);
197 * Returns the uniqure per irg GP Unknown node.
198 * (warning: cse has to be activated)
200 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg);
201 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg);
202 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg);
205 * Returns the unique per irg FP NoReg node.
207 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg);
210 * Returns the uniqure per irg FPU truncation mode node.
212 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg);
215 * Returns gp_noreg or fp_noreg, depending on input requirements.
217 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos);
220 * Maps all intrinsic calls that the backend support
221 * and map all instructions the backend did not support
224 void ia32_handle_intrinsics(void);
227 * Ia32 implementation.
229 * @param method the method type of the emulation function entity
230 * @param op the emulated ir_op
231 * @param imode the input mode of the emulated opcode
232 * @param omode the output mode of the emulated opcode
233 * @param context the context parameter
235 ir_entity *ia32_create_intrinsic_fkt(ir_type *method, const ir_op *op,
236 const ir_mode *imode, const ir_mode *omode,