2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
26 #ifndef FIRM_BE_IA32_BEARCH_IA32_T_H
27 #define FIRM_BE_IA32_BEARCH_IA32_T_H
29 #include "firm_config.h"
33 #include "ia32_nodes_attr.h"
38 #include "../bemachine.h"
39 #include "../beemitter.h"
42 #define SET_IA32_ORIG_NODE(n, o)
44 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
48 typedef enum ia32_optimize_t ia32_optimize_t;
49 typedef enum cpu_support cpu_support;
50 typedef enum fp_support fp_support;
52 typedef struct ia32_isa_t ia32_isa_t;
53 typedef struct ia32_code_gen_t ia32_code_gen_t;
54 typedef struct ia32_irn_ops_t ia32_irn_ops_t;
55 typedef struct ia32_intrinsic_env_t ia32_intrinsic_env_t;
60 struct ia32_code_gen_t {
61 const arch_code_generator_if_t *impl; /**< implementation */
62 ir_graph *irg; /**< current irg */
63 const arch_env_t *arch_env; /**< the arch env */
64 set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
65 ia32_isa_t *isa; /**< for fast access to the isa object */
66 be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
67 ir_node **blk_sched; /**< an array containing the scheduled blocks */
68 char do_x87_sim; /**< set to 1 if x87 simulation should be enforced */
69 char dump; /**< set to 1 if graphs should be dumped */
70 ir_node *unknown_gp; /**< unique Unknown_GP node */
71 ir_node *unknown_vfp; /**< unique Unknown_VFP node */
72 ir_node *unknown_xmm; /**< unique Unknown_XMM node */
73 ir_node *noreg_gp; /**< unique NoReg_GP node */
74 ir_node *noreg_vfp; /**< unique NoReg_VFP node */
75 ir_node *noreg_xmm; /**< unique NoReg_XMM node */
77 ir_node *fpu_trunc_mode; /**< truncate fpu mode */
86 arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
87 pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */
88 pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */
89 pmap *regs_8bit_high; /**< contains the hight part of the 8 bit names of the gp registers */
90 pmap *types; /**< A map of modes to primitive types */
91 pmap *tv_ent; /**< A map of entities that store const tarvals */
92 ia32_code_gen_t *cg; /**< the current code generator */
93 const be_machine_t *cpu; /**< the abstract machine */
95 struct obstack *name_obst; /**< holds the original node names (for debugging) */
99 struct ia32_irn_ops_t {
100 const arch_irn_ops_if_t *impl;
105 * A helper type collecting needed info for IA32 intrinsic lowering.
107 struct ia32_intrinsic_env_t {
108 ia32_isa_t *isa; /**< the isa object */
109 ir_graph *irg; /**< the irg, these entities belong to */
110 ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */
111 ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */
112 ir_entity *ll_d_conv; /**< entity for converts ll -> d */
113 ir_entity *d_ll_conv; /**< entity for converts d -> ll */
114 ir_entity *divdi3; /**< entity for __divdi3 library call */
115 ir_entity *moddi3; /**< entity for __moddi3 library call */
116 ir_entity *udivdi3; /**< entity for __udivdi3 library call */
117 ir_entity *umoddi3; /**< entity for __umoddi3 library call */
118 tarval *u64_bias; /**< bias value for conversion from float to unsigned 64 */
121 /** The mode for the floating point control word. */
122 extern ir_mode *mode_fpcw;
124 /** The current code generator. */
125 extern ia32_code_gen_t *ia32_current_cg;
128 * Returns the unique per irg GP NoReg node.
130 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg);
131 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg);
132 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg);
135 * Returns the uniqure per irg GP Unknown node.
136 * (warning: cse has to be activated)
138 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg);
139 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg);
140 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg);
143 * Returns the unique per irg FPU truncation mode node.
145 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg);
148 * Returns gp_noreg or fp_noreg, depending on input requirements.
150 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos);
153 * Maps all intrinsic calls that the backend support
154 * and map all instructions the backend did not support
157 void ia32_handle_intrinsics(void);
160 * Ia32 implementation.
162 * @param method the method type of the emulation function entity
163 * @param op the emulated ir_op
164 * @param imode the input mode of the emulated opcode
165 * @param omode the output mode of the emulated opcode
166 * @param context the context parameter
168 ir_entity *ia32_create_intrinsic_fkt(ir_type *method, const ir_op *op,
169 const ir_mode *imode, const ir_mode *omode,