2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 #ifndef _BEARCH_IA32_T_H_
21 #define _BEARCH_IA32_T_H_
23 #include "firm_config.h"
27 #include "ia32_nodes_attr.h"
32 #include "../bemachine.h"
33 #include "../beemitter.h"
36 #define SET_IA32_ORIG_NODE(n, o)
38 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
44 * Bitmask for the backend optimization settings.
46 typedef enum _ia32_optimize_t {
47 IA32_OPT_INCDEC = 1, /**< optimize add/sub 1/-1 to inc/dec */
48 IA32_OPT_DOAM = 2, /**< do address mode optimizations */
49 IA32_OPT_LEA = 4, /**< optimize address calculations into LEAs */
50 IA32_OPT_PLACECNST = 8, /**< place constants in the blocks where they are used */
51 IA32_OPT_IMMOPS = 16, /**< create operations with immediate operands */
52 IA32_OPT_PUSHARGS = 32, /**< create pushs for function argument passing */
56 * Architectures. Clustered for easier macro implementation,
59 typedef enum cpu_support {
60 arch_i386, /**< i386 */
61 arch_i486, /**< i486 */
62 arch_pentium, /**< Pentium */
63 arch_pentium_pro, /**< Pentium Pro */
64 arch_pentium_mmx, /**< Pentium MMX */
65 arch_pentium_2, /**< Pentium II */
66 arch_pentium_3, /**< Pentium III */
67 arch_pentium_4, /**< Pentium IV */
68 arch_pentium_m, /**< Pentium M */
69 arch_core, /**< Core */
71 arch_athlon, /**< Athlon */
72 arch_athlon_64, /**< Athlon64 */
73 arch_opteron, /**< Opteron */
76 /** checks for l <= x <= h */
77 #define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
79 /** returns true if it's Intel architecture */
80 #define ARCH_INTEL(x) _IN_RANGE((x), arch_i386, arch_core)
82 /** returns true if it's AMD architecture */
83 #define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron)
85 #define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \
86 _IN_RANGE((x), arch_athlon, arch_opteron))
88 /** floating point support */
89 typedef enum fp_support {
90 fp_none, /**< no floating point instructions are used */
91 fp_x87, /**< use x87 instructions */
92 fp_sse2 /**< use SSE2 instructions */
95 /** Sets the used flag to the current floating point architecture. */
96 #define FP_USED(cg) ((cg)->used_fp = (cg)->fp_kind)
98 /** Returns non-zero if the current floating point architecture is SSE2. */
99 #define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2)
101 /** Returns non-zero if the current floating point architecture is x87. */
102 #define USE_x87(cg) ((cg)->fp_kind == fp_x87)
104 /** Sets the flag to enforce x87 simulation. */
105 #define FORCE_x87(cg) ((cg)->force_sim = 1)
107 typedef struct _ia32_isa_t ia32_isa_t;
110 * IA32 code generator
112 typedef struct _ia32_code_gen_t {
113 const arch_code_generator_if_t *impl; /**< implementation */
114 ir_graph *irg; /**< current irg */
115 const arch_env_t *arch_env; /**< the arch env */
116 set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
117 ia32_isa_t *isa; /**< for fast access to the isa object */
118 be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
119 ir_node **blk_sched; /**< an array containing the scheduled blocks */
120 ia32_optimize_t opt; /**< contains optimization information */
121 int arch; /**< instruction architecture */
122 int opt_arch; /**< optimize for architecture */
123 char fp_kind; /**< floating point kind */
124 char used_fp; /**< which floating point unit used in this graph */
125 char force_sim; /**< set to 1 if x87 simulation should be enforced */
126 char dump; /**< set to 1 if graphs should be dumped */
127 ir_node *unknown_gp; /**< unique Unknown_GP node */
128 ir_node *unknown_vfp; /**< unique Unknown_VFP node */
129 ir_node *unknown_xmm; /**< unique Unknown_XMM node */
130 ir_node *noreg_gp; /**< unique NoReg_GP node */
131 ir_node *noreg_vfp; /**< unique NoReg_VFP node */
132 ir_node *noreg_xmm; /**< unique NoReg_XMM node */
134 ir_node *fpu_trunc_mode; /**< truncate fpu mode */
136 struct obstack *obst;
143 arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
145 pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */
146 pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */
147 pmap *types; /**< A map of modes to primitive types */
148 pmap *tv_ent; /**< A map of entities that store const tarvals */
149 ia32_optimize_t opt; /**< contains optimization information */
150 int arch; /**< instruction architecture */
151 int opt_arch; /**< optimize for architecture */
152 int fp_kind; /**< floating point kind */
153 ia32_code_gen_t *cg; /**< the current code generator */
154 const be_machine_t *cpu; /**< the abstract machine */
156 struct obstack *name_obst; /**< holds the original node names (for debugging) */
160 typedef struct _ia32_irn_ops_t {
161 const arch_irn_ops_if_t *impl;
165 typedef struct _ia32_intrinsic_env_t {
166 ir_graph *irg; /**< the irg, these entities belong to */
167 ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */
168 ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */
169 ir_entity *ll_d_conv; /**< entity for converts ll -> d */
170 ir_entity *d_ll_conv; /**< entity for converts d -> ll */
171 } ia32_intrinsic_env_t;
173 /** mode for the floating point control word */
174 extern ir_mode *mode_fpcw;
177 * Returns the unique per irg GP NoReg node.
179 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg);
180 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg);
181 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg);
184 * Returns the uniqure per irg GP Unknown node.
185 * (warning: cse has to be activated)
187 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg);
188 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg);
189 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg);
192 * Returns the unique per irg FP NoReg node.
194 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg);
197 * Returns the uniqure per irg FPU truncation mode node.
199 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg);
202 * Returns gp_noreg or fp_noreg, depending on input requirements.
204 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos);
207 * Maps all intrinsic calls that the backend support
208 * and map all instructions the backend did not support
211 void ia32_handle_intrinsics(void);
214 * Ia32 implementation.
216 * @param method the method type of the emulation function entity
217 * @param op the emulated ir_op
218 * @param imode the input mode of the emulated opcode
219 * @param omode the output mode of the emulated opcode
220 * @param context the context parameter
222 ir_entity *ia32_create_intrinsic_fkt(ir_type *method, const ir_op *op,
223 const ir_mode *imode, const ir_mode *omode,
226 #endif /* _BEARCH_IA32_T_H_ */