1 #ifndef _BEARCH_IA32_T_H_
2 #define _BEARCH_IA32_T_H_
4 #include "firm_config.h"
8 #include "bearch_ia32.h"
9 #include "ia32_nodes_attr.h"
13 #include "../bemachine.h"
16 #define SET_IA32_ORIG_NODE(n, o)
18 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
24 * Bitmask for the backend optimization settings.
26 typedef enum _ia32_optimize_t {
27 IA32_OPT_INCDEC = 1, /**< optimize add/sub 1/-1 to inc/dec */
28 IA32_OPT_DOAM = 2, /**< do address mode optimizations */
29 IA32_OPT_LEA = 4, /**< optimize address calculations into LEAs */
30 IA32_OPT_PLACECNST = 8, /**< place constants in the blocks where they are used */
31 IA32_OPT_IMMOPS = 16, /**< create operations with immediate operands */
32 IA32_OPT_EXTBB = 32, /**< do extended basic block scheduling */
33 IA32_OPT_PUSHARGS = 64, /**< create pushs for function argument passing */
37 * Architectures. Clustered for easier macro implementation,
40 typedef enum cpu_support {
41 arch_i386, /**< i386 */
42 arch_i486, /**< i486 */
43 arch_pentium, /**< Pentium */
44 arch_pentium_pro, /**< Pentium Pro */
45 arch_pentium_mmx, /**< Pentium MMX */
46 arch_pentium_2, /**< Pentium II */
47 arch_pentium_3, /**< Pentium III */
48 arch_pentium_4, /**< Pentium IV */
49 arch_pentium_m, /**< Pentium M */
50 arch_core, /**< Core */
52 arch_athlon, /**< Athlon */
53 arch_athlon_64, /**< Athlon64 */
54 arch_opteron, /**< Opteron */
57 /** checks for l <= x <= h */
58 #define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
60 /** returns true if it's Intel architecture */
61 #define ARCH_INTEL(x) _IN_RANGE((x), arch_i386, arch_core)
63 /** returns true if it's AMD architecture */
64 #define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron)
66 #define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \
67 _IN_RANGE((x), arch_athlon, arch_opteron))
69 /** floating point support */
70 typedef enum fp_support {
71 fp_none, /**< no floating point instructions are used */
72 fp_x87, /**< use x87 instructions */
73 fp_sse2 /**< use SSE2 instructions */
76 /** Sets the used flag to the current floating point architecture. */
77 #define FP_USED(cg) ((cg)->used_fp = (cg)->fp_kind)
79 /** Returns non-zero if the current floating point architecture is SSE2. */
80 #define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2)
82 /** Returns non-zero if the current floating point architecture is x87. */
83 #define USE_x87(cg) ((cg)->fp_kind == fp_x87)
85 /** Sets the flag to enforce x87 simulation. */
86 #define FORCE_x87(cg) ((cg)->force_sim = 1)
88 typedef struct _ia32_isa_t ia32_isa_t;
93 typedef struct _ia32_code_gen_t {
94 const arch_code_generator_if_t *impl; /**< implementation */
95 ir_graph *irg; /**< current irg */
96 const arch_env_t *arch_env; /**< the arch env */
97 set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
98 ia32_isa_t *isa; /**< for fast access to the isa object */
99 be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
100 ir_node **blk_sched; /**< an array containing the scheduled blocks */
101 ia32_optimize_t opt; /**< contains optimization information */
102 nodeset *kill_conv; /**< Remember all convs to be killed */
103 int arch; /**< instruction architecture */
104 int opt_arch; /**< optimize for architecture */
105 char fp_kind; /**< floating point kind */
106 char used_fp; /**< which floating point unit used in this graph */
107 char force_sim; /**< set to 1 if x87 simulation should be enforced */
108 char dump; /**< set to 1 if graphs should be dumped */
109 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< debugging module */
116 arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
117 pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */
118 pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */
119 pmap *types; /**< A map of modes to primitive types */
120 pmap *tv_ent; /**< A map of entities that store const tarvals */
121 ia32_optimize_t opt; /**< contains optimization information */
122 int arch; /**< instruction architecture */
123 int opt_arch; /**< optimize for architecture */
124 int fp_kind; /**< floating point kind */
125 ia32_code_gen_t *cg; /**< the current code generator */
126 FILE *out; /**< output file */
127 const be_machine_t *cpu; /**< the abstract machine */
129 struct obstack *name_obst; /**< holds the original node names (for debugging) */
133 typedef struct _ia32_irn_ops_t {
134 const arch_irn_ops_if_t *impl;
138 /* this is a struct to minimize the number of parameters
139 for transformation walker */
140 typedef struct _ia32_transform_env_t {
141 dbg_info *dbg; /**< The node debug info */
142 ir_graph *irg; /**< The irg, the node should be created in */
143 ir_node *block; /**< The block, the node should belong to */
144 ir_node *irn; /**< The irn, to be transformed */
145 ir_mode *mode; /**< The mode of the irn */
146 ia32_code_gen_t *cg; /**< The code generator */
147 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< The firm debugger */
148 } ia32_transform_env_t;
150 typedef struct _ia32_intrinsic_env_t {
151 ir_graph *irg; /**< the irg, these entities belong to */
152 ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */
153 ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */
154 ir_entity *ll_d_conv; /**< entity for converts ll -> d */
155 ir_entity *d_ll_conv; /**< entity for converts d -> ll */
156 } ia32_intrinsic_env_t;
159 * Returns the unique per irg GP NoReg node.
161 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg);
164 * Returns the unique per irg FP NoReg node.
166 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg);
169 * Returns gp_noreg or fp_noreg, depending on input requirements.
171 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos);
174 * Maps all intrinsic calls that the backend support
175 * and map all instructions the backend did not support
178 void ia32_handle_intrinsics(void);
181 * Ia32 implementation.
183 * @param method the method type of the emulation function entity
184 * @param op the emulated ir_op
185 * @param imode the input mode of the emulated opcode
186 * @param omode the output mode of the emulated opcode
187 * @param context the context parameter
189 ir_entity *ia32_create_intrinsic_fkt(ir_type *method, const ir_op *op,
190 const ir_mode *imode, const ir_mode *omode,
193 #endif /* _BEARCH_IA32_T_H_ */