nsz Git - libfirm/blob - ir/be/ia32/bearch_ia32_t.h

   1 /*
   2  * Copyright (C) 1995-2007 University of Karlsruhe.  All right reserved.
   3  *
   4  * This file is part of libFirm.
   5  *
   6  * This file may be distributed and/or modified under the terms of the
   7  * GNU General Public License version 2 as published by the Free Software
   8  * Foundation and appearing in the file LICENSE.GPL included in the
   9  * packaging of this file.
  10  *
  11  * Licensees holding valid libFirm Professional Edition licenses may use
  12  * this file in accordance with the libFirm Commercial License.
  13  * Agreement provided with the Software.
  14  *
  15  * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
  16  * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE.
  18  */
  19
  20 /**
  21  * @file
  22  * @brief       This is the main ia32 firm backend driver.
  23  * @author      Christian Wuerdig
  24  * @version     $Id$
  25  */
  26 #ifndef FIRM_BE_IA32_BEARCH_IA32_T_H
  27 #define FIRM_BE_IA32_BEARCH_IA32_T_H
  28
  29 #include "firm_config.h"
  30
  31 #include "pmap.h"
  32 #include "debug.h"
  33 #include "ia32_nodes_attr.h"
  34 #include "set.h"
  35 #include "pdeq.h"
  36
  37 #include "be.h"
  38 #include "../bemachine.h"
  39 #include "../beemitter.h"
  40
  41 #ifdef NDEBUG
  42 #define SET_IA32_ORIG_NODE(n, o)
  43 #else  /* ! NDEBUG */
  44 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
  45 #endif /* NDEBUG */
  46
  47 /* some typedefs */
  48 typedef enum ia32_optimize_t ia32_optimize_t;
  49 typedef enum cpu_support     cpu_support;
  50 typedef enum fp_support      fp_support;
  51
  52 /**
  53  * Bitmask for the backend optimization settings.
  54  */
  55 enum ia32_optimize_t {
  56         IA32_OPT_INCDEC    = 1 << 0,   /**< optimize add/sub 1/-1 to inc/dec */
  57         IA32_OPT_CC        = 1 << 1,   /**< optimize calling convention of private
  58                                             functions */
  59         IA32_OPT_UNSAFE_FLOATCONV = 1 << 2, /**< disrespect current floating
  60                                    point rounding mode at entry and exit of
  61                                    functions (this is ok for programs that don't
  62                                    explicitly change the rounding mode) */
  63 };
  64
  65 /**
  66  * CPU features.
  67  */
  68 enum cpu_arch_features {
  69         arch_feature_intel    = 0x80000000,                      /**< Intel CPU */
  70         arch_feature_amd      = 0x40000000,                      /**< AMD CPU */
  71         arch_feature_p6       = 0x20000000,                      /**< P6 instructions */
  72         arch_feature_mmx      = 0x10000000,                      /**< MMX instructions */
  73         arch_feature_sse1     = 0x08000000 | arch_feature_mmx,   /**< SSE1 instructions, include MMX */
  74         arch_feature_sse2     = 0x04000000 | arch_feature_sse1,  /**< SSE2 instructions, include SSE1 */
  75         arch_feature_sse3     = 0x02000000 | arch_feature_sse2,  /**< SSE3 instructions, include SSE2 */
  76         arch_feature_ssse3    = 0x01000000 | arch_feature_sse3,  /**< SSSE3 instructions, include SSE3 */
  77         arch_feature_3DNow    = 0x00800000,                      /**< 3DNow! instructions */
  78         arch_feature_3DNowE   = 0x00400000 | arch_feature_3DNow, /**< Enhanced 3DNow! instructions */
  79         arch_feature_netburst = 0x00200000 | arch_feature_intel, /**< Netburst architecture */
  80         arch_feature_64bit    = 0x00100000 | arch_feature_sse2,  /**< x86_64 support, include SSE2 */
  81 };
  82
  83 /**
  84  * Architectures.
  85  */
  86 enum cpu_support {
  87         /* intel CPU's */
  88         arch_generic     =  0,
  89
  90         arch_i386        =  1,
  91         arch_i486        =  2,
  92         arch_pentium     =  3 | arch_feature_intel,
  93         arch_pentium_mmx =  4 | arch_feature_intel | arch_feature_mmx,
  94         arch_pentium_pro =  5 | arch_feature_intel | arch_feature_p6,
  95         arch_pentium_2   =  6 | arch_feature_intel | arch_feature_p6 | arch_feature_mmx,
  96         arch_pentium_3   =  7 | arch_feature_intel | arch_feature_p6 | arch_feature_sse1,
  97         arch_pentium_4   =  8 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse2,
  98         arch_pentium_m   =  9 | arch_feature_intel | arch_feature_p6 | arch_feature_sse2,
  99         arch_core        = 10 | arch_feature_intel | arch_feature_p6 | arch_feature_sse3,
 100         arch_prescott    = 11 | arch_feature_netburst | arch_feature_p6 | arch_feature_sse3,
 101         arch_core2       = 12 | arch_feature_intel | arch_feature_p6 | arch_feature_64bit | arch_feature_ssse3,
 102
 103         /* AMD CPU's */
 104         arch_k6          = 13 | arch_feature_amd | arch_feature_mmx,
 105         arch_k6_2        = 14 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
 106         arch_k6_3        = 15 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNow,
 107         arch_athlon      = 16 | arch_feature_amd | arch_feature_mmx | arch_feature_3DNowE | arch_feature_p6,
 108         arch_athlon_xp   = 17 | arch_feature_amd | arch_feature_sse1 | arch_feature_3DNowE | arch_feature_p6,
 109         arch_opteron     = 18 | arch_feature_amd | arch_feature_64bit | arch_feature_3DNowE | arch_feature_p6,
 110
 111         /* other */
 112         arch_winchip_c6  = 19 | arch_feature_mmx,
 113         arch_winchip2    = 20 | arch_feature_mmx | arch_feature_3DNow,
 114         arch_c3          = 21 | arch_feature_mmx | arch_feature_3DNow,
 115         arch_c3_2        = 22 | arch_feature_sse1,  /* really no 3DNow! */
 116 };
 117
 118 /** checks for l <= x <= h */
 119 #define _IN_RANGE(x, l, h)  ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
 120
 121 /** returns true if it's Intel architecture */
 122 #define ARCH_INTEL(x)       (((x) & arch_feature_intel) != 0)
 123
 124 /** returns true if it's AMD architecture */
 125 #define ARCH_AMD(x)         (((x) & arch_feature_amd) != 0)
 126
 127 /** return true if it's a Athlon/Opteron */
 128 #define ARCH_ATHLON(x)      _IN_RANGE((x), arch_athlon, arch_opteron)
 129
 130 /** return true if the CPU has MMX support */
 131 #define ARCH_MMX(x)         (((x) & arch_feature_mmx) != 0)
 132
 133 /** return true if the CPU has 3DNow! support */
 134 #define ARCH_3DNow(x)       (((x) & arch_feature_3DNow) != 0)
 135
 136 /** return true if the CPU has P6 features (CMOV) */
 137 #define IS_P6_ARCH(x)       (((x) & arch_feature_p6) != 0)
 138
 139 /** floating point support */
 140 enum fp_support {
 141         fp_none,  /**< no floating point instructions are used */
 142         fp_x87,   /**< use x87 instructions */
 143         fp_sse2   /**< use SSE2 instructions */
 144 };
 145
 146 /** Returns non-zero if the current floating point architecture is SSE2. */
 147 #define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2)
 148
 149 /** Returns non-zero if the current floating point architecture is x87. */
 150 #define USE_x87(cg)  ((cg)->fp_kind == fp_x87)
 151
 152 typedef struct ia32_isa_t            ia32_isa_t;
 153 typedef struct ia32_code_gen_t       ia32_code_gen_t;
 154 typedef struct ia32_irn_ops_t        ia32_irn_ops_t;
 155 typedef struct ia32_intrinsic_env_t  ia32_intrinsic_env_t;
 156
 157 /**
 158  * IA32 code generator
 159  */
 160 struct ia32_code_gen_t {
 161         const arch_code_generator_if_t *impl;          /**< implementation */
 162         ir_graph                       *irg;           /**< current irg */
 163         const arch_env_t               *arch_env;      /**< the arch env */
 164         set                            *reg_set;       /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
 165         ia32_isa_t                     *isa;           /**< for fast access to the isa object */
 166         be_irg_t                       *birg;          /**< The be-irg (contains additional information about the irg) */
 167         ir_node                        **blk_sched;    /**< an array containing the scheduled blocks */
 168         ia32_optimize_t                opt;            /**< contains optimization information */
 169         int                            arch;           /**< instruction architecture */
 170         int                            opt_arch;       /**< optimize for architecture */
 171         char                           fp_kind;        /**< floating point kind */
 172         char                           do_x87_sim;     /**< set to 1 if x87 simulation should be enforced */
 173         char                           dump;           /**< set to 1 if graphs should be dumped */
 174         ir_node                       *unknown_gp;     /**< unique Unknown_GP node */
 175         ir_node                       *unknown_vfp;    /**< unique Unknown_VFP node */
 176         ir_node                       *unknown_xmm;    /**< unique Unknown_XMM node */
 177         ir_node                       *noreg_gp;       /**< unique NoReg_GP node */
 178         ir_node                       *noreg_vfp;      /**< unique NoReg_VFP node */
 179         ir_node                       *noreg_xmm;      /**< unique NoReg_XMM node */
 180
 181         ir_node                       *fpu_trunc_mode; /**< truncate fpu mode */
 182
 183         struct obstack                *obst;
 184 };
 185
 186 /**
 187  * IA32 ISA object
 188  */
 189 struct ia32_isa_t {
 190         arch_isa_t            arch_isa;       /**< must be derived from arch_isa_t */
 191         pmap                  *regs_16bit;    /**< Contains the 16bits names of the gp registers */
 192         pmap                  *regs_8bit;     /**< Contains the 8bits names of the gp registers */
 193         pmap                  *regs_8bit_high; /**< contains the hight part of the 8 bit names of the gp registers */
 194         pmap                  *types;         /**< A map of modes to primitive types */
 195         pmap                  *tv_ent;        /**< A map of entities that store const tarvals */
 196         ia32_optimize_t       opt;            /**< contains optimization information */
 197         int                   arch;           /**< instruction architecture */
 198         int                   opt_arch;       /**< optimize for architecture */
 199         int                   fp_kind;        /**< floating point kind */
 200         ia32_code_gen_t       *cg;            /**< the current code generator */
 201         const be_machine_t    *cpu;           /**< the abstract machine */
 202 #ifndef NDEBUG
 203         struct obstack        *name_obst;     /**< holds the original node names (for debugging) */
 204 #endif /* NDEBUG */
 205 };
 206
 207 struct ia32_irn_ops_t {
 208         const arch_irn_ops_if_t *impl;
 209         ia32_code_gen_t         *cg;
 210 };
 211
 212 /**
 213  * A helper type collecting needed info for IA32 intrinsic lowering.
 214  */
 215 struct ia32_intrinsic_env_t {
 216         ia32_isa_t *isa;          /**< the isa object */
 217         ir_graph   *irg;          /**< the irg, these entities belong to */
 218         ir_entity  *ll_div_op1;   /**< entity for first div operand (move into FPU) */
 219         ir_entity  *ll_div_op2;   /**< entity for second div operand (move into FPU) */
 220         ir_entity  *ll_d_conv;    /**< entity for converts ll -> d */
 221         ir_entity  *d_ll_conv;    /**< entity for converts d -> ll */
 222         ir_entity  *divdi3;       /**< entity for __divdi3 library call */
 223         ir_entity  *moddi3;       /**< entity for __moddi3 library call */
 224         ir_entity  *udivdi3;      /**< entity for __udivdi3 library call */
 225         ir_entity  *umoddi3;      /**< entity for __umoddi3 library call */
 226         tarval     *u64_bias;     /**< bias value for conversion from float to unsigned 64 */
 227 };
 228
 229 /** The mode for the floating point control word. */
 230 extern ir_mode *mode_fpcw;
 231
 232 /** The current code generator. */
 233 extern ia32_code_gen_t *ia32_current_cg;
 234
 235 /**
 236  * Returns the unique per irg GP NoReg node.
 237  */
 238 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg);
 239 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg);
 240 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg);
 241
 242 /**
 243  * Returns the uniqure per irg GP Unknown node.
 244  * (warning: cse has to be activated)
 245  */
 246 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg);
 247 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg);
 248 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg);
 249
 250 /**
 251  * Returns the unique per irg FP NoReg node.
 252  */
 253 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg);
 254
 255 /**
 256  * Returns the unique per irg FPU truncation mode node.
 257  */
 258 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg);
 259
 260 /**
 261  * Returns gp_noreg or fp_noreg, depending on input requirements.
 262  */
 263 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos);
 264
 265 /**
 266  * Maps all intrinsic calls that the backend support
 267  * and map all instructions the backend did not support
 268  * to runtime calls.
 269  */
 270 void ia32_handle_intrinsics(void);
 271
 272 /**
 273  * Ia32 implementation.
 274  *
 275  * @param method   the method type of the emulation function entity
 276  * @param op       the emulated ir_op
 277  * @param imode    the input mode of the emulated opcode
 278  * @param omode    the output mode of the emulated opcode
 279  * @param context  the context parameter
 280  */
 281 ir_entity *ia32_create_intrinsic_fkt(ir_type *method, const ir_op *op,
 282                                      const ir_mode *imode, const ir_mode *omode,
 283                                      void *context);
 284
 285 #endif