2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
26 #ifndef FIRM_BE_IA32_BEARCH_IA32_T_H
27 #define FIRM_BE_IA32_BEARCH_IA32_T_H
31 #include "ia32_nodes_attr.h"
36 #include "../bemachine.h"
37 #include "../beemitter.h"
40 #define SET_IA32_ORIG_NODE(n, o)
42 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
46 typedef enum ia32_optimize_t ia32_optimize_t;
47 typedef enum cpu_support cpu_support;
48 typedef enum fp_support fp_support;
50 typedef struct ia32_isa_t ia32_isa_t;
51 typedef struct ia32_code_gen_t ia32_code_gen_t;
52 typedef struct ia32_irn_ops_t ia32_irn_ops_t;
53 typedef struct ia32_intrinsic_env_t ia32_intrinsic_env_t;
58 struct ia32_code_gen_t {
59 const arch_code_generator_if_t *impl; /**< implementation */
60 ir_graph *irg; /**< current irg */
61 set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
62 ia32_isa_t *isa; /**< for fast access to the isa object */
63 be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
64 ir_node **blk_sched; /**< an array containing the scheduled blocks */
65 unsigned do_x87_sim:1; /**< set to 1 if x87 simulation should be enforced */
66 unsigned dump:1; /**< set to 1 if graphs should be dumped */
67 unsigned gprof:1; /**< set to 1 grof profiling is in use */
68 ir_node *unknown_gp; /**< unique Unknown_GP node */
69 ir_node *unknown_vfp; /**< unique Unknown_VFP node */
70 ir_node *unknown_xmm; /**< unique Unknown_XMM node */
71 ir_node *noreg_gp; /**< unique NoReg_GP node */
72 ir_node *noreg_vfp; /**< unique NoReg_VFP node */
73 ir_node *noreg_xmm; /**< unique NoReg_XMM node */
75 ir_node *fpu_trunc_mode; /**< truncate fpu mode */
76 ir_node *get_eip; /**< get eip node */
85 arch_env_t arch_env; /**< must be derived from arch_env_t */
86 pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */
87 pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */
88 pmap *regs_8bit_high; /**< contains the hight part of the 8 bit names of the gp registers */
89 pmap *types; /**< A map of modes to primitive types */
90 pmap *tv_ent; /**< A map of entities that store const tarvals */
91 ia32_code_gen_t *cg; /**< the current code generator */
92 const be_machine_t *cpu; /**< the abstract machine */
94 struct obstack *name_obst; /**< holds the original node names (for debugging) */
99 * A helper type collecting needed info for IA32 intrinsic lowering.
101 struct ia32_intrinsic_env_t {
102 ia32_isa_t *isa; /**< the isa object */
103 ir_graph *irg; /**< the irg, these entities belong to */
104 ir_entity *ll_div_op1; /**< entity for first div operand (move into FPU) */
105 ir_entity *ll_div_op2; /**< entity for second div operand (move into FPU) */
106 ir_entity *ll_d_conv; /**< entity for converts ll -> d */
107 ir_entity *d_ll_conv; /**< entity for converts d -> ll */
108 ir_entity *divdi3; /**< entity for __divdi3 library call */
109 ir_entity *moddi3; /**< entity for __moddi3 library call */
110 ir_entity *udivdi3; /**< entity for __udivdi3 library call */
111 ir_entity *umoddi3; /**< entity for __umoddi3 library call */
112 tarval *u64_bias; /**< bias value for conversion from float to unsigned 64 */
115 typedef enum transformer_t {
123 /** The selected transformer. */
124 extern transformer_t be_transformer;
126 /** The mode for the floating point control word. */
127 extern ir_mode *mode_fpcw;
129 /** The current code generator. */
130 extern ia32_code_gen_t *ia32_current_cg;
133 * Returns the unique per irg GP NoReg node.
135 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg);
136 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg);
137 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg);
140 * Returns the uniqure per irg GP Unknown node.
141 * (warning: cse has to be activated)
143 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg);
144 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg);
145 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg);
148 * Returns the unique per irg FPU truncation mode node.
150 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg);
153 * Split instruction with source AM into Load and separate instruction.
154 * @return result of the Load
156 ir_node *turn_back_am(ir_node *node);
159 * Maps all intrinsic calls that the backend support
160 * and map all instructions the backend did not support
163 void ia32_handle_intrinsics(void);
166 * Ia32 implementation.
168 * @param method the method type of the emulation function entity
169 * @param op the emulated ir_op
170 * @param imode the input mode of the emulated opcode
171 * @param omode the output mode of the emulated opcode
172 * @param context the context parameter
174 ir_entity *ia32_create_intrinsic_fkt(ir_type *method, const ir_op *op,
175 const ir_mode *imode, const ir_mode *omode,