1 #ifndef _BEARCH_IA32_T_H_
2 #define _BEARCH_IA32_T_H_
4 #include "firm_config.h"
8 #include "bearch_ia32.h"
9 #include "ia32_nodes_attr.h"
14 #define SET_IA32_ORIG_NODE(n, o)
16 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
22 * Bitmask for the backend optimization settings.
24 typedef enum _ia32_optimize_t {
25 IA32_OPT_INCDEC = 1, /**< optimize add/sub 1/-1 to inc/dec */
26 IA32_OPT_DOAM = 2, /**< do address mode optimizations */
27 IA32_OPT_LEA = 4, /**< optimize address calculations into LEAs */
28 IA32_OPT_PLACECNST = 8, /**< place constants in the blocks where they are used */
29 IA32_OPT_IMMOPS = 16, /**< create operations with immediate operands */
30 IA32_OPT_EXTBB = 32, /**< do extended basic block scheduling */
34 * Architectures. Clustered for easier macro implementation,
37 typedef enum cpu_support {
38 arch_i386, /**< i386 */
39 arch_i486, /**< i486 */
40 arch_pentium, /**< Pentium */
41 arch_pentium_pro, /**< Pentium Pro */
42 arch_pentium_mmx, /**< Pentium MMX */
43 arch_pentium_2, /**< Pentium II */
44 arch_pentium_3, /**< Pentium III */
45 arch_pentium_4, /**< Pentium IV */
46 arch_pentium_m, /**< Pentium M */
47 arch_core, /**< Core */
49 arch_athlon, /**< Athlon */
50 arch_athlon_64, /**< Athlon64 */
51 arch_opteron, /**< Opteron */
54 /** checks for l <= x <= h */
55 #define _IN_RANGE(x, l, h) ((unsigned)((x) - (l)) <= (unsigned)((h) - (l)))
57 /** returns true if it's Intel architecture */
58 #define ARCH_INTEL(x) _IN_RANGE((x), arch_i386, arch_core)
60 /** returns true if it's AMD architecture */
61 #define ARCH_AMD(x) _IN_RANGE((x), arch_k6, arch_opteron)
63 #define IS_P6_ARCH(x) (_IN_RANGE((x), arch_pentium_pro, arch_core) || \
64 _IN_RANGE((x), arch_athlon, arch_opteron))
66 /** floating point support */
67 typedef enum fp_support {
68 fp_none, /**< no floating point instructions are used */
69 fp_x87, /**< use x87 instructions */
70 fp_sse2 /**< use SSE2 instructions */
73 /** Sets the used flag to the current floating point architecture. */
74 #define FP_USED(cg) ((cg)->used_fp = (cg)->fp_kind)
76 /** Returns non-zero if the current floating point architecture is SSE2. */
77 #define USE_SSE2(cg) ((cg)->fp_kind == fp_sse2)
79 /** Returns non-zero if the current floating point architecture is x87. */
80 #define USE_x87(cg) ((cg)->fp_kind == fp_x87)
82 /** Sets the flag to enforce x87 simulation. */
83 #define FORCE_x87(cg) ((cg)->force_sim = 1)
85 typedef struct _ia32_isa_t ia32_isa_t;
90 typedef struct _ia32_code_gen_t {
91 const arch_code_generator_if_t *impl; /**< implementation */
92 ir_graph *irg; /**< current irg */
93 const arch_env_t *arch_env; /**< the arch env */
94 set *reg_set; /**< set to memorize registers for non-ia32 nodes (e.g. phi nodes) */
95 ia32_isa_t *isa; /**< for fast access to the isa object */
96 const be_irg_t *birg; /**< The be-irg (contains additional information about the irg) */
97 ir_node **blk_sched; /**< an array containing the scheduled blocks */
98 ia32_optimize_t opt; /**< contains optimization information */
99 entity *fp_to_gp; /**< allocated entity for fp to gp conversion */
100 entity *gp_to_fp; /**< allocated entity for gp to fp conversion */
101 int arch; /**< instruction architecture */
102 int opt_arch; /**< optimize for architecture */
103 char fp_kind; /**< floating point kind */
104 char used_fp; /**< which floating point unit used in this graph */
105 char force_sim; /**< set to 1 if x87 simulation should be enforced */
106 char dump; /**< set to 1 if graphs should be dumped */
107 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< debugging module */
114 arch_isa_t arch_isa; /**< must be derived from arch_isa_t */
115 pmap *regs_16bit; /**< Contains the 16bits names of the gp registers */
116 pmap *regs_8bit; /**< Contains the 8bits names of the gp registers */
117 pmap *types; /**< A map of modes to primitive types */
118 pmap *tv_ent; /**< A map of entities that store const tarvals */
119 ia32_optimize_t opt; /**< contains optimization information */
120 int arch; /**< instruction architecture */
121 int opt_arch; /**< optimize for architecture */
122 int fp_kind; /**< floating point kind */
123 ia32_code_gen_t *cg; /**< the current code generator */
124 FILE *out; /**< output file */
126 struct obstack *name_obst; /**< holds the original node names (for debugging) */
127 unsigned long name_obst_size;
131 typedef struct _ia32_irn_ops_t {
132 const arch_irn_ops_if_t *impl;
136 /* this is a struct to minimize the number of parameters
137 for transformation walker */
138 typedef struct _ia32_transform_env_t {
139 dbg_info *dbg; /**< The node debug info */
140 ir_graph *irg; /**< The irg, the node should be created in */
141 ir_node *block; /**< The block, the node should belong to */
142 ir_node *irn; /**< The irn, to be transformed */
143 ir_mode *mode; /**< The mode of the irn */
144 ia32_code_gen_t *cg; /**< The code generator */
145 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< The firm debugger */
146 } ia32_transform_env_t;
148 typedef struct _ia32_intrinsic_env_t {
149 entity *ll_div_op1; /**< entity for first div operand (move into FPU) */
150 entity *ll_div_op2; /**< entity for second div operand (move into FPU) */
151 entity *ll_d_conv; /**< entity for converts ll -> d */
152 entity *d_ll_conv; /**< entity for converts d -> ll */
153 } ia32_intrinsic_env_t;
156 * Returns the unique per irg GP NoReg node.
158 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg);
161 * Returns the unique per irg FP NoReg node.
163 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg);
166 * Maps all intrinsic calls that the backend support
167 * and map all instructions the backend did not support
170 void ia32_handle_intrinsics(void);
173 * Ia32 implementation.
175 * @param method the method type of the emulation function entity
176 * @param op the emulated ir_op
177 * @param imode the input mode of the emulated opcode
178 * @param omode the output mode of the emulated opcode
179 * @param context the context parameter
181 entity *ia32_create_intrinsic_fkt(ir_type *method, const ir_op *op,
182 const ir_mode *imode, const ir_mode *omode,
185 #endif /* _BEARCH_IA32_T_H_ */