2 * This is the main ia32 firm backend driver.
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
41 #include "bearch_ia32_t.h"
43 #include "ia32_new_nodes.h" /* ia32 nodes interface */
44 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
45 #include "ia32_gen_decls.h" /* interface declaration emitter */
46 #include "ia32_transform.h"
47 #include "ia32_emitter.h"
48 #include "ia32_map_regs.h"
49 #include "ia32_optimize.h"
51 #include "ia32_dbg_stat.h"
53 #define DEBUG_MODULE "firm.be.ia32.isa"
56 static set *cur_reg_set = NULL;
59 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
61 /* Creates the unique per irg GP NoReg node. */
62 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
63 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
66 /* Creates the unique per irg FP NoReg node. */
67 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
68 return be_abi_get_callee_save_irn(cg->birg->abi,
69 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
72 /**************************************************
75 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
76 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
77 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
78 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
81 **************************************************/
83 static ir_node *my_skip_proj(const ir_node *n) {
91 * Return register requirements for an ia32 node.
92 * If the node returns a tuple (mode_T) then the proj's
93 * will be asked for this information.
95 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
96 const ia32_irn_ops_t *ops = self;
97 const ia32_register_req_t *irn_req;
98 long node_pos = pos == -1 ? 0 : pos;
99 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
100 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
102 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
103 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
107 if (mode == mode_T && pos < 0) {
108 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
112 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
116 node_pos = ia32_translate_proj_pos(irn);
122 irn = my_skip_proj(irn);
124 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
127 if (is_ia32_irn(irn)) {
129 irn_req = get_ia32_in_req(irn, pos);
132 irn_req = get_ia32_out_req(irn, node_pos);
135 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
137 memcpy(req, &(irn_req->req), sizeof(*req));
139 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
140 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
141 req->other_same = get_irn_n(irn, irn_req->same_pos);
144 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
145 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
146 req->other_different = get_irn_n(irn, irn_req->different_pos);
150 /* treat Unknowns like Const with default requirements */
151 if (is_Unknown(irn)) {
152 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
153 if (mode_is_float(mode)) {
154 if (USE_SSE2(ops->cg))
155 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
157 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
159 else if (mode_is_int(mode) || mode_is_reference(mode))
160 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
161 else if (mode == mode_T || mode == mode_M) {
162 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
166 assert(0 && "unsupported Unknown-Mode");
169 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
177 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
179 const ia32_irn_ops_t *ops = self;
181 if (get_irn_mode(irn) == mode_X) {
185 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
188 pos = ia32_translate_proj_pos(irn);
189 irn = my_skip_proj(irn);
192 if (is_ia32_irn(irn)) {
193 const arch_register_t **slots;
195 slots = get_ia32_slots(irn);
199 ia32_set_firm_reg(irn, reg, cur_reg_set);
203 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
205 const arch_register_t *reg = NULL;
209 if (get_irn_mode(irn) == mode_X) {
213 pos = ia32_translate_proj_pos(irn);
214 irn = my_skip_proj(irn);
217 if (is_ia32_irn(irn)) {
218 const arch_register_t **slots;
219 slots = get_ia32_slots(irn);
223 reg = ia32_get_firm_reg(irn, cur_reg_set);
229 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
230 irn = my_skip_proj(irn);
232 return arch_irn_class_branch;
233 else if (is_ia32_Cnst(irn))
234 return arch_irn_class_const;
235 else if (is_ia32_irn(irn))
236 return arch_irn_class_normal;
241 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
242 irn = my_skip_proj(irn);
243 if (is_ia32_irn(irn))
244 return get_ia32_flags(irn);
247 return arch_irn_flags_ignore;
252 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
253 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
256 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
258 const ia32_irn_ops_t *ops = self;
260 if (get_ia32_frame_ent(irn)) {
261 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
263 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
264 snprintf(buf, sizeof(buf), "%d", bias);
266 if (get_ia32_op_type(irn) == ia32_Normal) {
267 set_ia32_cnst(irn, buf);
270 add_ia32_am_offs(irn, buf);
272 set_ia32_am_flavour(irn, am_flav);
278 be_abi_call_flags_bits_t flags;
279 const arch_isa_t *isa;
280 const arch_env_t *aenv;
284 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
286 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
287 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
288 env->flags = fl.bits;
291 env->isa = aenv->isa;
296 * Put all registers which are saved by the prologue/epilogue in a set.
298 * @param self The callback object.
299 * @param s The result set.
301 static void ia32_abi_dont_save_regs(void *self, pset *s)
303 ia32_abi_env_t *env = self;
304 if(env->flags.try_omit_fp)
305 pset_insert_ptr(s, env->isa->bp);
309 * Generate the routine prologue.
311 * @param self The callback object.
312 * @param mem A pointer to the mem node. Update this if you define new memory.
313 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
315 * @return The register which shall be used as a stack frame base.
317 * All nodes which define registers in @p reg_map must keep @p reg_map current.
319 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
321 ia32_abi_env_t *env = self;
323 if (!env->flags.try_omit_fp) {
324 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
325 ir_node *bl = get_irg_start_block(env->irg);
326 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
327 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
331 push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
332 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
333 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
335 /* the push must have SP out register */
336 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
337 set_ia32_flags(push, arch_irn_flags_ignore);
339 /* move esp to ebp */
340 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
341 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
342 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
343 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
345 /* beware: the copy must be done before any other sp use */
346 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
347 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
348 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
349 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
351 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
352 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
361 * Generate the routine epilogue.
362 * @param self The callback object.
363 * @param mem A pointer to the mem node. Update this if you define new memory.
364 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
365 * @return The register which shall be used as a stack frame base.
367 * All nodes which define registers in @p reg_map must keep @p reg_map current.
369 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
371 ia32_abi_env_t *env = self;
372 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
373 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
375 if (env->flags.try_omit_fp) {
376 /* simply remove the stack frame here */
377 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
380 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
381 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
382 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
384 /* gcc always emits a leave at the end of a routine */
385 if (1 || ARCH_AMD(isa->opt_arch)) {
389 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
390 set_ia32_flags(leave, arch_irn_flags_ignore);
391 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
392 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
393 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
398 /* copy ebp to esp */
399 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
402 pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
403 set_ia32_flags(pop, arch_irn_flags_ignore);
404 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
405 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
406 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
408 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
409 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
412 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
413 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
417 * Produces the type which sits between the stack args and the locals on the stack.
418 * it will contain the return address and space to store the old base pointer.
419 * @return The Firm type modeling the ABI between type.
421 static ir_type *ia32_abi_get_between_type(void *self)
423 static ir_type *omit_fp_between_type = NULL;
424 static ir_type *between_type = NULL;
426 ia32_abi_env_t *env = self;
430 entity *ret_addr_ent;
431 entity *omit_fp_ret_addr_ent;
433 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
434 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
436 between_type = new_type_class(new_id_from_str("ia32_between_type"));
437 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
438 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
440 set_entity_offset_bytes(old_bp_ent, 0);
441 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
442 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
444 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
445 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
447 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
448 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
451 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
454 static const be_abi_callbacks_t ia32_abi_callbacks = {
457 ia32_abi_get_between_type,
458 ia32_abi_dont_save_regs,
463 /* fill register allocator interface */
465 static const arch_irn_ops_if_t ia32_irn_ops_if = {
466 ia32_get_irn_reg_req,
471 ia32_get_frame_entity,
475 ia32_irn_ops_t ia32_irn_ops = {
482 /**************************************************
485 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
486 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
487 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
488 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
491 **************************************************/
494 * Transforms the standard firm graph into
497 static void ia32_prepare_graph(void *self) {
498 ia32_code_gen_t *cg = self;
499 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
501 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
502 ia32_register_transformers();
503 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
504 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
506 if (cg->opt & IA32_OPT_DOAM) {
507 edges_deactivate(cg->irg);
508 //dead_node_elimination(cg->irg);
509 edges_activate(cg->irg);
511 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
513 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
514 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
517 DEBUG_ONLY(cg->mod = old_mod;)
522 * Insert copies for all ia32 nodes where the should_be_same requirement
524 * Transform Sub into Neg -- Add if IN2 == OUT
526 static void ia32_finish_node(ir_node *irn, void *env) {
527 ia32_code_gen_t *cg = env;
528 const ia32_register_req_t **reqs;
529 const arch_register_t *out_reg, *in_reg, *in2_reg;
531 ir_node *copy, *in_node, *block, *in2_node;
532 ia32_op_type_t op_tp;
534 if (is_ia32_irn(irn)) {
535 /* AM Dest nodes don't produce any values */
536 op_tp = get_ia32_op_type(irn);
537 if (op_tp == ia32_AddrModeD)
540 reqs = get_ia32_out_req_all(irn);
541 n_res = get_ia32_n_res(irn);
542 block = get_nodes_block(irn);
544 /* check all OUT requirements, if there is a should_be_same */
545 if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) &&
546 ! is_ia32_Lea(irn) && ! is_ia32_Conv_I2I(irn) && ! is_ia32_Conv_I2I8Bit(irn))
548 for (i = 0; i < n_res; i++) {
549 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
550 /* get in and out register */
551 out_reg = get_ia32_out_reg(irn, i);
552 in_node = get_irn_n(irn, reqs[i]->same_pos);
553 in_reg = arch_get_irn_register(cg->arch_env, in_node);
555 /* don't copy ignore nodes */
556 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
559 /* check if in and out register are equal */
560 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
561 /* in case of a commutative op: just exchange the in's */
562 /* beware: the current op could be everything, so test for ia32 */
563 /* commutativity first before getting the second in */
564 if (is_ia32_commutative(irn)) {
565 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
566 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
568 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
569 set_irn_n(irn, reqs[i]->same_pos, in2_node);
570 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
577 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
578 /* create copy from in register */
579 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
581 DBG_OPT_2ADDRCPY(copy);
583 /* destination is the out register */
584 arch_set_irn_register(cg->arch_env, copy, out_reg);
586 /* insert copy before the node into the schedule */
587 sched_add_before(irn, copy);
590 set_irn_n(irn, reqs[i]->same_pos, copy);
597 /* If we have a CondJmp with immediate, we need to */
598 /* check if it's the right operand, otherwise we have */
599 /* to change it, as CMP doesn't support immediate as */
601 if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) {
602 set_ia32_op_type(irn, ia32_AddrModeD);
603 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
606 /* check if there is a sub which need to be transformed */
607 ia32_transform_sub_to_neg_add(irn, cg);
609 /* transform a LEA into an Add if possible */
610 ia32_transform_lea_to_add(irn, cg);
614 /* check for peephole optimization */
615 ia32_peephole_optimization(irn, cg);
618 static void ia32_finish_irg_walker(ir_node *block, void *env) {
621 for (irn = sched_first(block); !sched_is_end(irn); irn = next) {
622 next = sched_next(irn);
623 ia32_finish_node(irn, env);
628 * Add Copy nodes for not fulfilled should_be_equal constraints
630 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
631 irg_block_walk_graph(irg, NULL, ia32_finish_irg_walker, cg);
637 * Dummy functions for hooks we don't need but which must be filled.
639 static void ia32_before_sched(void *self) {
643 * Called before the register allocator.
644 * Calculate a block schedule here. We need it for the x87
645 * simulator and the emitter.
647 static void ia32_before_ra(void *self) {
648 ia32_code_gen_t *cg = self;
650 cg->blk_sched = sched_create_block_schedule(cg->irg);
655 * Transforms a be node into a Load.
657 static void transform_to_Load(ia32_transform_env_t *env) {
658 ir_node *irn = env->irn;
659 entity *ent = be_get_frame_entity(irn);
660 ir_mode *mode = env->mode;
661 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
662 ir_node *nomem = new_rd_NoMem(env->irg);
663 ir_node *sched_point = NULL;
664 ir_node *ptr = get_irn_n(irn, 0);
665 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
666 ir_node *new_op, *proj;
667 const arch_register_t *reg;
669 if (sched_is_scheduled(irn)) {
670 sched_point = sched_prev(irn);
673 if (mode_is_float(mode)) {
674 if (USE_SSE2(env->cg))
675 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
677 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
680 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
683 set_ia32_am_support(new_op, ia32_am_Source);
684 set_ia32_op_type(new_op, ia32_AddrModeS);
685 set_ia32_am_flavour(new_op, ia32_B);
686 set_ia32_ls_mode(new_op, mode);
687 set_ia32_frame_ent(new_op, ent);
688 set_ia32_use_frame(new_op);
690 DBG_OPT_RELOAD2LD(irn, new_op);
692 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
695 sched_add_after(sched_point, new_op);
696 sched_add_after(new_op, proj);
701 /* copy the register from the old node to the new Load */
702 reg = arch_get_irn_register(env->cg->arch_env, irn);
703 arch_set_irn_register(env->cg->arch_env, new_op, reg);
705 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
711 * Transforms a be node into a Store.
713 static void transform_to_Store(ia32_transform_env_t *env) {
714 ir_node *irn = env->irn;
715 entity *ent = be_get_frame_entity(irn);
716 ir_mode *mode = env->mode;
717 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
718 ir_node *nomem = new_rd_NoMem(env->irg);
719 ir_node *ptr = get_irn_n(irn, 0);
720 ir_node *val = get_irn_n(irn, 1);
721 ir_node *new_op, *proj;
722 ir_node *sched_point = NULL;
724 if (sched_is_scheduled(irn)) {
725 sched_point = sched_prev(irn);
728 if (mode_is_float(mode)) {
729 if (USE_SSE2(env->cg))
730 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
732 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
734 else if (get_mode_size_bits(mode) == 8) {
735 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
738 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
741 set_ia32_am_support(new_op, ia32_am_Dest);
742 set_ia32_op_type(new_op, ia32_AddrModeD);
743 set_ia32_am_flavour(new_op, ia32_B);
744 set_ia32_ls_mode(new_op, mode);
745 set_ia32_frame_ent(new_op, ent);
746 set_ia32_use_frame(new_op);
748 DBG_OPT_SPILL2ST(irn, new_op);
750 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
753 sched_add_after(sched_point, new_op);
754 sched_add_after(new_op, proj);
759 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
765 * Fix the mode of Spill/Reload
767 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
769 if (mode_is_float(mode)) {
781 * Block-Walker: Calls the transform functions Spill and Reload.
783 static void ia32_after_ra_walker(ir_node *block, void *env) {
784 ir_node *node, *prev;
785 ia32_code_gen_t *cg = env;
786 ia32_transform_env_t tenv;
789 tenv.irg = current_ir_graph;
791 DEBUG_ONLY(tenv.mod = cg->mod;)
793 /* beware: the schedule is changed here */
794 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
795 prev = sched_prev(node);
796 if (be_is_Reload(node)) {
797 /* we always reload the whole register */
798 tenv.dbg = get_irn_dbg_info(node);
800 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
801 transform_to_Load(&tenv);
803 else if (be_is_Spill(node)) {
804 /* we always spill the whole register */
805 tenv.dbg = get_irn_dbg_info(node);
807 tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
808 transform_to_Store(&tenv);
814 * We transform Spill and Reload here. This needs to be done before
815 * stack biasing otherwise we would miss the corrected offset for these nodes.
817 * If x87 instruction should be emitted, run the x87 simulator and patch
818 * the virtual instructions. This must obviously be done after register allocation.
820 static void ia32_after_ra(void *self) {
821 ia32_code_gen_t *cg = self;
822 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
824 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
825 if (cg->used_fp == fp_x87) {
826 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
832 * Emits the code, closes the output file and frees
833 * the code generator interface.
835 static void ia32_codegen(void *self) {
836 ia32_code_gen_t *cg = self;
837 ir_graph *irg = cg->irg;
839 ia32_finish_irg(irg, cg);
840 be_dump(irg, "-finished", dump_ir_block_graph_sched);
841 ia32_gen_routine(cg->isa->out, irg, cg);
845 /* remove it from the isa */
848 /* de-allocate code generator */
849 del_set(cg->reg_set);
854 static void *ia32_cg_init(const be_irg_t *birg);
856 static const arch_code_generator_if_t ia32_code_gen_if = {
858 NULL, /* before abi introduce hook */
860 ia32_before_sched, /* before scheduling hook */
861 ia32_before_ra, /* before register allocation hook */
862 ia32_after_ra, /* after register allocation hook */
863 ia32_codegen /* emit && done */
867 * Initializes a IA32 code generator.
869 static void *ia32_cg_init(const be_irg_t *birg) {
870 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
871 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
873 cg->impl = &ia32_code_gen_if;
875 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
876 cg->arch_env = birg->main_env->arch_env;
879 cg->blk_sched = NULL;
882 cg->fp_kind = isa->fp_kind;
883 cg->used_fp = fp_none;
885 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
887 /* copy optimizations from isa for easier access */
894 if (isa->name_obst_size) {
895 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
896 isa->name_obst_size = 0;
897 obstack_free(isa->name_obst, NULL);
898 obstack_init(isa->name_obst);
902 cur_reg_set = cg->reg_set;
904 ia32_irn_ops.cg = cg;
906 return (arch_code_generator_t *)cg;
911 /*****************************************************************
912 * ____ _ _ _____ _____
913 * | _ \ | | | | |_ _|/ ____| /\
914 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
915 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
916 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
917 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
919 *****************************************************************/
922 * The template that generates a new ISA object.
923 * Note that this template can be changed by command line
926 static ia32_isa_t ia32_isa_template = {
928 &ia32_isa_if, /* isa interface implementation */
929 &ia32_gp_regs[REG_ESP], /* stack pointer register */
930 &ia32_gp_regs[REG_EBP], /* base pointer register */
931 -1, /* stack direction */
933 NULL, /* 16bit register names */
934 NULL, /* 8bit register names */
938 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
939 IA32_OPT_DOAM | /* optimize address mode default: on */
940 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
941 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
942 IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
943 arch_pentium_4, /* instruction architecture */
944 arch_pentium_4, /* optimize for architecture */
945 fp_sse2, /* use sse2 unit */
946 NULL, /* current code generator */
948 NULL, /* name obstack */
949 0 /* name obst size */
954 * Initializes the backend ISA.
956 static void *ia32_init(FILE *file_handle) {
957 static int inited = 0;
963 isa = xmalloc(sizeof(*isa));
964 memcpy(isa, &ia32_isa_template, sizeof(*isa));
966 ia32_register_init(isa);
967 ia32_create_opcodes();
969 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
970 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
971 /* no SSE2 for these cpu's */
972 isa->fp_kind = fp_x87;
974 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
975 /* Pentium 4 don't like inc and dec instructions */
976 isa->opt &= ~IA32_OPT_INCDEC;
979 isa->regs_16bit = pmap_create();
980 isa->regs_8bit = pmap_create();
981 isa->types = pmap_create();
982 isa->tv_ent = pmap_create();
983 isa->out = file_handle;
985 ia32_build_16bit_reg_map(isa->regs_16bit);
986 ia32_build_8bit_reg_map(isa->regs_8bit);
988 /* patch register names of x87 registers */
990 ia32_st_regs[0].name = "st";
991 ia32_st_regs[1].name = "st(1)";
992 ia32_st_regs[2].name = "st(2)";
993 ia32_st_regs[3].name = "st(3)";
994 ia32_st_regs[4].name = "st(4)";
995 ia32_st_regs[5].name = "st(5)";
996 ia32_st_regs[6].name = "st(6)";
997 ia32_st_regs[7].name = "st(7)";
1001 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1002 obstack_init(isa->name_obst);
1003 isa->name_obst_size = 0;
1006 fprintf(isa->out, "\t.intel_syntax\n");
1016 * Closes the output file and frees the ISA structure.
1018 static void ia32_done(void *self) {
1019 ia32_isa_t *isa = self;
1021 /* emit now all global declarations */
1022 ia32_gen_decls(isa->out);
1024 pmap_destroy(isa->regs_16bit);
1025 pmap_destroy(isa->regs_8bit);
1026 pmap_destroy(isa->tv_ent);
1027 pmap_destroy(isa->types);
1030 //printf("name obst size = %d bytes\n", isa->name_obst_size);
1031 obstack_free(isa->name_obst, NULL);
1039 * Return the number of register classes for this architecture.
1040 * We report always these:
1041 * - the general purpose registers
1042 * - the floating point register set (depending on the unit used for FP)
1043 * - MMX/SSE registers (currently not supported)
1045 static int ia32_get_n_reg_class(const void *self) {
1050 * Return the register class for index i.
1052 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1053 const ia32_isa_t *isa = self;
1054 assert(i >= 0 && i < 2 && "Invalid ia32 register class requested.");
1056 return &ia32_reg_classes[CLASS_ia32_gp];
1057 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1061 * Get the register class which shall be used to store a value of a given mode.
1062 * @param self The this pointer.
1063 * @param mode The mode in question.
1064 * @return A register class which can hold values of the given mode.
1066 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1067 const ia32_isa_t *isa = self;
1068 if (mode_is_float(mode)) {
1069 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1072 return &ia32_reg_classes[CLASS_ia32_gp];
1076 * Get the ABI restrictions for procedure calls.
1077 * @param self The this pointer.
1078 * @param method_type The type of the method (procedure) in question.
1079 * @param abi The abi object to be modified
1081 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1082 const ia32_isa_t *isa = self;
1085 unsigned cc = get_method_calling_convention(method_type);
1086 int n = get_method_n_params(method_type);
1089 int i, ignore_1, ignore_2;
1091 const arch_register_t *reg;
1092 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1094 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1096 /* set abi flags for calls */
1097 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1098 call_flags.bits.store_args_sequential = use_push;
1099 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1100 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1101 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1103 /* set stack parameter passing style */
1104 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1106 /* collect the mode for each type */
1107 modes = alloca(n * sizeof(modes[0]));
1109 for (i = 0; i < n; i++) {
1110 tp = get_method_param_type(method_type, i);
1111 modes[i] = get_type_mode(tp);
1114 /* set register parameters */
1115 if (cc & cc_reg_param) {
1116 /* determine the number of parameters passed via registers */
1117 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1119 /* loop over all parameters and set the register requirements */
1120 for (i = 0; i <= biggest_n; i++) {
1121 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1122 assert(reg && "kaputt");
1123 be_abi_call_param_reg(abi, i, reg);
1130 /* set stack parameters */
1131 for (i = stack_idx; i < n; i++) {
1132 be_abi_call_param_stack(abi, i, 1, 0, 0);
1136 /* set return registers */
1137 n = get_method_n_ress(method_type);
1139 assert(n <= 2 && "more than two results not supported");
1141 /* In case of 64bit returns, we will have two 32bit values */
1143 tp = get_method_res_type(method_type, 0);
1144 mode = get_type_mode(tp);
1146 assert(!mode_is_float(mode) && "two FP results not supported");
1148 tp = get_method_res_type(method_type, 1);
1149 mode = get_type_mode(tp);
1151 assert(!mode_is_float(mode) && "two FP results not supported");
1153 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1154 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1157 const arch_register_t *reg;
1159 tp = get_method_res_type(method_type, 0);
1160 assert(is_atomic_type(tp));
1161 mode = get_type_mode(tp);
1163 reg = mode_is_float(mode) ?
1164 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1165 &ia32_gp_regs[REG_EAX];
1167 be_abi_call_res_reg(abi, 0, reg);
1172 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1173 return &ia32_irn_ops;
1176 const arch_irn_handler_t ia32_irn_handler = {
1180 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1181 return &ia32_irn_handler;
1184 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1185 return is_ia32_irn(irn);
1189 * Initializes the code generator interface.
1191 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1192 return &ia32_code_gen_if;
1195 list_sched_selector_t ia32_sched_selector;
1198 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1200 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1201 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1202 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1203 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1204 return &ia32_sched_selector;
1208 * Returns the necessary byte alignment for storing a register of given class.
1210 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1211 ir_mode *mode = arch_register_class_mode(cls);
1212 int bytes = get_mode_size_bytes(mode);
1214 if (mode_is_float(mode) && bytes > 8)
1221 /* instruction set architectures. */
1222 static const lc_opt_enum_int_items_t arch_items[] = {
1223 { "386", arch_i386, },
1224 { "486", arch_i486, },
1225 { "pentium", arch_pentium, },
1226 { "586", arch_pentium, },
1227 { "pentiumpro", arch_pentium_pro, },
1228 { "686", arch_pentium_pro, },
1229 { "pentiummmx", arch_pentium_mmx, },
1230 { "pentium2", arch_pentium_2, },
1231 { "p2", arch_pentium_2, },
1232 { "pentium3", arch_pentium_3, },
1233 { "p3", arch_pentium_3, },
1234 { "pentium4", arch_pentium_4, },
1235 { "p4", arch_pentium_4, },
1236 { "pentiumm", arch_pentium_m, },
1237 { "pm", arch_pentium_m, },
1238 { "core", arch_core, },
1240 { "athlon", arch_athlon, },
1241 { "athlon64", arch_athlon_64, },
1242 { "opteron", arch_opteron, },
1246 static lc_opt_enum_int_var_t arch_var = {
1247 &ia32_isa_template.arch, arch_items
1250 static lc_opt_enum_int_var_t opt_arch_var = {
1251 &ia32_isa_template.opt_arch, arch_items
1254 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1256 { "sse2", fp_sse2 },
1260 static lc_opt_enum_int_var_t fp_unit_var = {
1261 &ia32_isa_template.fp_kind, fp_unit_items
1264 static const lc_opt_enum_int_items_t gas_items[] = {
1265 { "linux", ASM_LINUX_GAS },
1266 { "mingw", ASM_MINGW_GAS },
1270 static lc_opt_enum_int_var_t gas_var = {
1271 &asm_flavour, gas_items
1274 static const lc_opt_table_entry_t ia32_options[] = {
1275 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1276 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1277 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1278 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1279 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1280 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1281 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1282 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1287 * Register command line options for the ia32 backend.
1291 * ia32-arch=arch create instruction for arch
1292 * ia32-opt=arch optimize for run on arch
1293 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1294 * ia32-incdec optimize for inc/dec
1295 * ia32-noaddrmode do not use address mode
1296 * ia32-noplacecnst do not place constants,
1297 * ia32-noimmop no operations with immediates
1298 * ia32-noextbb do not use extended basic block scheduling
1299 * ia32-gasmode set the GAS compatibility mode
1301 static void ia32_register_options(lc_opt_entry_t *ent)
1303 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1304 lc_opt_add_table(be_grp_ia32, ia32_options);
1306 #endif /* WITH_LIBCORE */
1308 const arch_isa_if_t ia32_isa_if = {
1311 ia32_get_n_reg_class,
1313 ia32_get_reg_class_for_mode,
1315 ia32_get_irn_handler,
1316 ia32_get_code_generator_if,
1317 ia32_get_list_sched_selector,
1318 ia32_get_reg_class_alignment,
1320 ia32_register_options