2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
38 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
55 #include "../beirg_t.h"
56 #include "../benode_t.h"
57 #include "../belower.h"
58 #include "../besched_t.h"
61 #include "../beirgmod.h"
62 #include "../be_dbgout.h"
63 #include "../beblocksched.h"
64 #include "../bemachine.h"
65 #include "../beilpsched.h"
66 #include "../bespillslots.h"
67 #include "../bemodule.h"
68 #include "../begnuas.h"
69 #include "../bestate.h"
70 #include "../beflags.h"
71 #include "../betranshlp.h"
73 #include "bearch_ia32_t.h"
75 #include "ia32_new_nodes.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "gen_ia32_machine.h"
78 #include "ia32_common_transform.h"
79 #include "ia32_transform.h"
80 #include "ia32_emitter.h"
81 #include "ia32_map_regs.h"
82 #include "ia32_optimize.h"
84 #include "ia32_dbg_stat.h"
85 #include "ia32_finish.h"
86 #include "ia32_util.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
93 transformer_t be_transformer = TRANSFORMER_DEFAULT;
96 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
99 static set *cur_reg_set = NULL;
101 ir_mode *mode_fpcw = NULL;
102 ia32_code_gen_t *ia32_current_cg = NULL;
104 /** The current omit-fp state */
105 static unsigned ia32_curr_fp_ommitted = 0;
106 static ir_type *omit_fp_between_type = NULL;
107 static ir_type *between_type = NULL;
108 static ir_entity *old_bp_ent = NULL;
109 static ir_entity *ret_addr_ent = NULL;
110 static ir_entity *omit_fp_ret_addr_ent = NULL;
113 * The environment for the intrinsic mapping.
115 static ia32_intrinsic_env_t intrinsic_env = {
117 NULL, /* the irg, these entities belong to */
118 NULL, /* entity for __divdi3 library call */
119 NULL, /* entity for __moddi3 library call */
120 NULL, /* entity for __udivdi3 library call */
121 NULL, /* entity for __umoddi3 library call */
125 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
128 * Used to create per-graph unique pseudo nodes.
130 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
131 create_const_node_func func,
132 const arch_register_t* reg)
134 ir_node *block, *res;
139 block = get_irg_start_block(cg->irg);
140 res = func(NULL, block);
141 arch_set_irn_register(res, reg);
147 /* Creates the unique per irg GP NoReg node. */
148 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
149 return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
150 &ia32_gp_regs[REG_GP_NOREG]);
153 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
154 return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
155 &ia32_vfp_regs[REG_VFP_NOREG]);
158 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
159 return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
160 &ia32_xmm_regs[REG_XMM_NOREG]);
163 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
164 return create_const(cg, &cg->unknown_gp, new_bd_ia32_Unknown_GP,
165 &ia32_gp_regs[REG_GP_UKNWN]);
168 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
169 return create_const(cg, &cg->unknown_vfp, new_bd_ia32_Unknown_VFP,
170 &ia32_vfp_regs[REG_VFP_UKNWN]);
173 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
174 return create_const(cg, &cg->unknown_xmm, new_bd_ia32_Unknown_XMM,
175 &ia32_xmm_regs[REG_XMM_UKNWN]);
178 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
179 return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
180 &ia32_fp_cw_regs[REG_FPCW]);
185 * Returns the admissible noreg register node for input register pos of node irn.
187 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
189 const arch_register_req_t *req = arch_get_register_req(irn, pos);
191 assert(req != NULL && "Missing register requirements");
192 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
193 return ia32_new_NoReg_gp(cg);
195 if (ia32_cg_config.use_sse2) {
196 return ia32_new_NoReg_xmm(cg);
198 return ia32_new_NoReg_vfp(cg);
202 /**************************************************
205 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
206 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
207 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
208 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
211 **************************************************/
214 * Return register requirements for an ia32 node.
215 * If the node returns a tuple (mode_T) then the proj's
216 * will be asked for this information.
218 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
221 ir_mode *mode = get_irn_mode(node);
224 if (mode == mode_X || is_Block(node)) {
225 return arch_no_register_req;
228 if (mode == mode_T && pos < 0) {
229 return arch_no_register_req;
232 node_pos = pos == -1 ? 0 : pos;
234 if (mode == mode_M || pos >= 0) {
235 return arch_no_register_req;
238 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
239 node = skip_Proj_const(node);
242 if (is_ia32_irn(node)) {
243 const arch_register_req_t *req;
245 req = get_ia32_in_req(node, pos);
247 req = get_ia32_out_req(node, node_pos);
254 /* unknowns should be transformed already */
255 return arch_no_register_req;
258 static arch_irn_class_t ia32_classify(const ir_node *irn) {
259 arch_irn_class_t classification = 0;
261 irn = skip_Proj_const(irn);
264 classification |= arch_irn_class_branch;
266 if (! is_ia32_irn(irn))
267 return classification;
269 if (is_ia32_is_reload(irn))
270 classification |= arch_irn_class_reload;
272 if (is_ia32_is_spill(irn))
273 classification |= arch_irn_class_spill;
275 if (is_ia32_is_remat(irn))
276 classification |= arch_irn_class_remat;
278 return classification;
282 * The IA32 ABI callback object.
285 be_abi_call_flags_bits_t flags; /**< The call flags. */
286 const arch_env_t *aenv; /**< The architecture environment. */
287 ir_graph *irg; /**< The associated graph. */
290 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
291 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
294 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
295 set_ia32_frame_ent(irn, ent);
298 static void ia32_set_frame_offset(ir_node *irn, int bias)
300 if (get_ia32_frame_ent(irn) == NULL)
303 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
304 ia32_code_gen_t *cg = ia32_current_cg;
305 int omit_fp = be_abi_omit_fp(cg->birg->abi);
307 /* Pop nodes modify the stack pointer before calculating the
308 * destination address, so fix this here
313 add_ia32_am_offs_int(irn, bias);
316 static int ia32_get_sp_bias(const ir_node *node)
318 if (is_ia32_Call(node))
319 return -(int)get_ia32_call_attr_const(node)->pop;
321 if (is_ia32_Push(node))
324 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
331 * Generate the routine prologue.
333 * @param self The callback object.
334 * @param mem A pointer to the mem node. Update this if you define new memory.
335 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
336 * @param stack_bias Points to the current stack bias, can be modified if needed.
338 * @return The register which shall be used as a stack frame base.
340 * All nodes which define registers in @p reg_map must keep @p reg_map current.
342 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
344 ia32_abi_env_t *env = self;
345 ia32_code_gen_t *cg = ia32_current_cg;
346 const arch_env_t *arch_env = env->aenv;
348 ia32_curr_fp_ommitted = env->flags.try_omit_fp;
349 if (! env->flags.try_omit_fp) {
350 ir_node *bl = get_irg_start_block(env->irg);
351 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
352 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
353 ir_node *noreg = ia32_new_NoReg_gp(cg);
356 /* mark bp register as ignore */
357 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
358 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
361 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
362 curr_sp = new_r_Proj(bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
363 *mem = new_r_Proj(bl, push, mode_M, pn_ia32_Push_M);
365 /* the push must have SP out register */
366 arch_set_irn_register(curr_sp, arch_env->sp);
368 /* this modifies the stack bias, because we pushed 32bit */
371 /* move esp to ebp */
372 curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
373 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
374 arch_register_req_type_ignore);
376 /* beware: the copy must be done before any other sp use */
377 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
378 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
379 arch_register_req_type_produces_sp);
381 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
382 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
391 * Generate the routine epilogue.
392 * @param self The callback object.
393 * @param bl The block for the epilog
394 * @param mem A pointer to the mem node. Update this if you define new memory.
395 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
396 * @return The register which shall be used as a stack frame base.
398 * All nodes which define registers in @p reg_map must keep @p reg_map current.
400 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
402 ia32_abi_env_t *env = self;
403 const arch_env_t *arch_env = env->aenv;
404 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
405 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
407 if (env->flags.try_omit_fp) {
408 /* simply remove the stack frame here */
409 curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
411 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
413 if (ia32_cg_config.use_leave) {
417 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
418 curr_bp = new_r_Proj(bl, leave, mode_bp, pn_ia32_Leave_frame);
419 curr_sp = new_r_Proj(bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
423 /* the old SP is not needed anymore (kill the proj) */
424 assert(is_Proj(curr_sp));
427 /* copy ebp to esp */
428 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
429 arch_set_irn_register(curr_sp, arch_env->sp);
430 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
431 arch_register_req_type_ignore);
434 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
435 curr_bp = new_r_Proj(bl, pop, mode_bp, pn_ia32_Pop_res);
436 curr_sp = new_r_Proj(bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
438 *mem = new_r_Proj(bl, pop, mode_M, pn_ia32_Pop_M);
440 arch_set_irn_register(curr_sp, arch_env->sp);
441 arch_set_irn_register(curr_bp, arch_env->bp);
444 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
445 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
449 * Initialize the callback object.
450 * @param call The call object.
451 * @param aenv The architecture environment.
452 * @param irg The graph with the method.
453 * @return Some pointer. This pointer is passed to all other callback functions as self object.
455 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
457 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
458 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
459 env->flags = fl.bits;
466 * Destroy the callback object.
467 * @param self The callback object.
469 static void ia32_abi_done(void *self) {
474 * Build the between type and entities if not already build.
476 static void ia32_build_between_type(void) {
477 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
478 if (! between_type) {
479 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
480 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
482 between_type = new_type_struct(IDENT("ia32_between_type"));
483 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
484 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
486 set_entity_offset(old_bp_ent, 0);
487 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
488 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
489 set_type_state(between_type, layout_fixed);
491 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
492 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
494 set_entity_offset(omit_fp_ret_addr_ent, 0);
495 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
496 set_type_state(omit_fp_between_type, layout_fixed);
502 * Produces the type which sits between the stack args and the locals on the stack.
503 * it will contain the return address and space to store the old base pointer.
504 * @return The Firm type modeling the ABI between type.
506 static ir_type *ia32_abi_get_between_type(void *self)
508 ia32_abi_env_t *env = self;
510 ia32_build_between_type();
511 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
515 * Return the stack entity that contains the return address.
517 ir_entity *ia32_get_return_address_entity(void) {
518 ia32_build_between_type();
519 return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
523 * Return the stack entity that contains the frame address.
525 ir_entity *ia32_get_frame_address_entity(void) {
526 ia32_build_between_type();
527 return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
531 * Get the estimated cycle count for @p irn.
533 * @param self The this pointer.
534 * @param irn The node.
536 * @return The estimated cycle count for this operation
538 static int ia32_get_op_estimated_cost(const ir_node *irn)
541 ia32_op_type_t op_tp;
545 if (!is_ia32_irn(irn))
548 assert(is_ia32_irn(irn));
550 cost = get_ia32_latency(irn);
551 op_tp = get_ia32_op_type(irn);
553 if (is_ia32_CopyB(irn)) {
556 else if (is_ia32_CopyB_i(irn)) {
557 int size = get_ia32_copyb_size(irn);
558 cost = 20 + (int)ceil((4/3) * size);
560 /* in case of address mode operations add additional cycles */
561 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
563 In case of stack access and access to fixed addresses add 5 cycles
564 (we assume they are in cache), other memory operations cost 20
567 if (is_ia32_use_frame(irn) || (
568 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
569 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
581 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
583 * @param irn The original operation
584 * @param i Index of the argument we want the inverse operation to yield
585 * @param inverse struct to be filled with the resulting inverse op
586 * @param obstack The obstack to use for allocation of the returned nodes array
587 * @return The inverse operation or NULL if operation invertible
589 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
592 ir_node *block, *noreg, *nomem;
595 /* we cannot invert non-ia32 irns */
596 if (! is_ia32_irn(irn))
599 /* operand must always be a real operand (not base, index or mem) */
600 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
603 /* we don't invert address mode operations */
604 if (get_ia32_op_type(irn) != ia32_Normal)
607 /* TODO: adjust for new immediates... */
608 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
612 block = get_nodes_block(irn);
613 mode = get_irn_mode(irn);
614 irn_mode = get_irn_mode(irn);
615 noreg = get_irn_n(irn, 0);
617 dbg = get_irn_dbg_info(irn);
619 /* initialize structure */
620 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
624 switch (get_ia32_irn_opcode(irn)) {
627 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
628 /* we have an add with a const here */
629 /* invers == add with negated const */
630 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
632 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
633 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
634 set_ia32_commutative(inverse->nodes[0]);
636 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
637 /* we have an add with a symconst here */
638 /* invers == sub with const */
639 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
641 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
644 /* normal add: inverse == sub */
645 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
652 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
653 /* we have a sub with a const/symconst here */
654 /* invers == add with this const */
655 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
656 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
657 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
661 if (i == n_ia32_binary_left) {
662 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
665 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
673 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
674 /* xor with const: inverse = xor */
675 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
676 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
677 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
681 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
687 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
692 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
697 /* inverse operation not supported */
704 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
706 if(mode_is_float(mode))
713 * Get the mode that should be used for spilling value node
715 static ir_mode *get_spill_mode(const ir_node *node)
717 ir_mode *mode = get_irn_mode(node);
718 return get_spill_mode_mode(mode);
722 * Checks whether an addressmode reload for a node with mode mode is compatible
723 * with a spillslot of mode spill_mode
725 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
727 return !mode_is_float(mode) || mode == spillmode;
731 * Check if irn can load its operand at position i from memory (source addressmode).
732 * @param irn The irn to be checked
733 * @param i The operands position
734 * @return Non-Zero if operand can be loaded
736 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
738 ir_node *op = get_irn_n(irn, i);
739 const ir_mode *mode = get_irn_mode(op);
740 const ir_mode *spillmode = get_spill_mode(op);
742 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
743 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
744 !ia32_is_spillmode_compatible(mode, spillmode) ||
745 is_ia32_use_frame(irn)) /* must not already use frame */
748 switch (get_ia32_am_support(irn)) {
753 if (i != n_ia32_unary_op)
759 case n_ia32_binary_left: {
760 const arch_register_req_t *req;
761 if (!is_ia32_commutative(irn))
764 /* we can't swap left/right for limited registers
765 * (As this (currently) breaks constraint handling copies)
767 req = get_ia32_in_req(irn, n_ia32_binary_left);
768 if (req->type & arch_register_req_type_limited)
773 case n_ia32_binary_right:
782 panic("Unknown AM type");
785 /* HACK: must not already use "real" memory.
786 * This can happen for Call and Div */
787 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
793 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
797 ir_mode *dest_op_mode;
799 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
801 set_ia32_op_type(irn, ia32_AddrModeS);
803 load_mode = get_irn_mode(get_irn_n(irn, i));
804 dest_op_mode = get_ia32_ls_mode(irn);
805 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
806 set_ia32_ls_mode(irn, load_mode);
808 set_ia32_use_frame(irn);
809 set_ia32_need_stackent(irn);
811 if (i == n_ia32_binary_left &&
812 get_ia32_am_support(irn) == ia32_am_binary &&
813 /* immediates are only allowed on the right side */
814 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
815 ia32_swap_left_right(irn);
816 i = n_ia32_binary_right;
819 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
821 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
822 set_irn_n(irn, n_ia32_mem, spill);
823 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
824 set_ia32_is_reload(irn);
827 static const be_abi_callbacks_t ia32_abi_callbacks = {
830 ia32_abi_get_between_type,
835 /* fill register allocator interface */
837 static const arch_irn_ops_t ia32_irn_ops = {
838 ia32_get_irn_reg_req,
840 ia32_get_frame_entity,
841 ia32_set_frame_entity,
842 ia32_set_frame_offset,
845 ia32_get_op_estimated_cost,
846 ia32_possible_memory_operand,
847 ia32_perform_memory_operand,
850 /**************************************************
853 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
854 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
855 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
856 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
859 **************************************************/
861 static ir_entity *mcount = NULL;
863 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
865 static void ia32_before_abi(void *self) {
866 lower_mode_b_config_t lower_mode_b_config = {
867 mode_Iu, /* lowered mode */
868 mode_Bu, /* preferred mode for set */
869 0, /* don't lower direct compares */
871 ia32_code_gen_t *cg = self;
873 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
875 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
877 if (mcount == NULL) {
878 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
879 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
880 /* FIXME: enter the right ld_ident here */
881 set_entity_ld_ident(mcount, get_entity_ident(mcount));
882 set_entity_visibility(mcount, visibility_external_allocated);
884 instrument_initcall(cg->irg, mcount);
889 * Transforms the standard firm graph into
892 static void ia32_prepare_graph(void *self)
894 ia32_code_gen_t *cg = self;
895 ir_graph *irg = cg->irg;
897 /* do local optimizations */
898 optimize_graph_df(irg);
900 /* we have to do cfopt+remove_critical_edges as we can't have Bad-blocks
901 * or critical edges in the backend */
903 remove_critical_cf_edges(irg);
905 /* TODO: we often have dead code reachable through out-edges here. So for
906 * now we rebuild edges (as we need correct user count for code selection)
909 edges_deactivate(cg->irg);
910 edges_activate(cg->irg);
914 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
916 switch (be_transformer) {
917 case TRANSFORMER_DEFAULT:
918 /* transform remaining nodes into assembler instructions */
919 ia32_transform_graph(cg);
923 case TRANSFORMER_PBQP:
924 case TRANSFORMER_RAND:
925 /* transform nodes into assembler instructions by PBQP magic */
926 ia32_transform_graph_by_pbqp(cg);
931 panic("invalid transformer");
934 /* do local optimizations (mainly CSE) */
935 optimize_graph_df(cg->irg);
938 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
940 /* optimize address mode */
941 ia32_optimize_graph(cg);
943 /* do code placement, to optimize the position of constants */
947 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
950 ir_node *turn_back_am(ir_node *node)
952 dbg_info *dbgi = get_irn_dbg_info(node);
953 ir_node *block = get_nodes_block(node);
954 ir_node *base = get_irn_n(node, n_ia32_base);
955 ir_node *index = get_irn_n(node, n_ia32_index);
956 ir_node *mem = get_irn_n(node, n_ia32_mem);
959 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
960 ir_node *load_res = new_rd_Proj(dbgi, block, load, mode_Iu, pn_ia32_Load_res);
962 ia32_copy_am_attrs(load, node);
963 if (is_ia32_is_reload(node))
964 set_ia32_is_reload(load);
965 set_irn_n(node, n_ia32_mem, new_NoMem());
967 switch (get_ia32_am_support(node)) {
969 set_irn_n(node, n_ia32_unary_op, load_res);
973 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
974 set_irn_n(node, n_ia32_binary_left, load_res);
976 set_irn_n(node, n_ia32_binary_right, load_res);
981 panic("Unknown AM type");
983 noreg = ia32_new_NoReg_gp(ia32_current_cg);
984 set_irn_n(node, n_ia32_base, noreg);
985 set_irn_n(node, n_ia32_index, noreg);
986 set_ia32_am_offs_int(node, 0);
987 set_ia32_am_sc(node, NULL);
988 set_ia32_am_scale(node, 0);
989 clear_ia32_am_sc_sign(node);
991 /* rewire mem-proj */
992 if (get_irn_mode(node) == mode_T) {
993 const ir_edge_t *edge;
994 foreach_out_edge(node, edge) {
995 ir_node *out = get_edge_src_irn(edge);
996 if (get_irn_mode(out) == mode_M) {
997 set_Proj_pred(out, load);
998 set_Proj_proj(out, pn_ia32_Load_M);
1004 set_ia32_op_type(node, ia32_Normal);
1005 if (sched_is_scheduled(node))
1006 sched_add_before(node, load);
1011 static ir_node *flags_remat(ir_node *node, ir_node *after)
1013 /* we should turn back source address mode when rematerializing nodes */
1014 ia32_op_type_t type;
1018 if (is_Block(after)) {
1021 block = get_nodes_block(after);
1024 type = get_ia32_op_type(node);
1026 case ia32_AddrModeS:
1030 case ia32_AddrModeD:
1031 /* TODO implement this later... */
1032 panic("found DestAM with flag user %+F this should not happen", node);
1035 default: assert(type == ia32_Normal); break;
1038 copy = exact_copy(node);
1039 set_nodes_block(copy, block);
1040 sched_add_after(after, copy);
1046 * Called before the register allocator.
1048 static void ia32_before_ra(void *self) {
1049 ia32_code_gen_t *cg = self;
1051 /* setup fpu rounding modes */
1052 ia32_setup_fpu_mode(cg);
1055 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1058 ia32_add_missing_keeps(cg);
1063 * Transforms a be_Reload into a ia32 Load.
1065 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1066 ir_graph *irg = get_irn_irg(node);
1067 dbg_info *dbg = get_irn_dbg_info(node);
1068 ir_node *block = get_nodes_block(node);
1069 ir_entity *ent = be_get_frame_entity(node);
1070 ir_mode *mode = get_irn_mode(node);
1071 ir_mode *spillmode = get_spill_mode(node);
1072 ir_node *noreg = ia32_new_NoReg_gp(cg);
1073 ir_node *sched_point = NULL;
1074 ir_node *ptr = get_irg_frame(irg);
1075 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1076 ir_node *new_op, *proj;
1077 const arch_register_t *reg;
1079 if (sched_is_scheduled(node)) {
1080 sched_point = sched_prev(node);
1083 if (mode_is_float(spillmode)) {
1084 if (ia32_cg_config.use_sse2)
1085 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
1087 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
1089 else if (get_mode_size_bits(spillmode) == 128) {
1090 /* Reload 128 bit SSE registers */
1091 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
1094 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1096 set_ia32_op_type(new_op, ia32_AddrModeS);
1097 set_ia32_ls_mode(new_op, spillmode);
1098 set_ia32_frame_ent(new_op, ent);
1099 set_ia32_use_frame(new_op);
1100 set_ia32_is_reload(new_op);
1102 DBG_OPT_RELOAD2LD(node, new_op);
1104 proj = new_rd_Proj(dbg, block, new_op, mode, pn_ia32_Load_res);
1107 sched_add_after(sched_point, new_op);
1111 /* copy the register from the old node to the new Load */
1112 reg = arch_get_irn_register(node);
1113 arch_set_irn_register(proj, reg);
1115 SET_IA32_ORIG_NODE(new_op, node);
1117 exchange(node, proj);
1121 * Transforms a be_Spill node into a ia32 Store.
1123 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1124 ir_graph *irg = get_irn_irg(node);
1125 dbg_info *dbg = get_irn_dbg_info(node);
1126 ir_node *block = get_nodes_block(node);
1127 ir_entity *ent = be_get_frame_entity(node);
1128 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1129 ir_mode *mode = get_spill_mode(spillval);
1130 ir_node *noreg = ia32_new_NoReg_gp(cg);
1131 ir_node *nomem = new_NoMem();
1132 ir_node *ptr = get_irg_frame(irg);
1133 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1135 ir_node *sched_point = NULL;
1137 if (sched_is_scheduled(node)) {
1138 sched_point = sched_prev(node);
1141 /* No need to spill unknown values... */
1142 if(is_ia32_Unknown_GP(val) ||
1143 is_ia32_Unknown_VFP(val) ||
1144 is_ia32_Unknown_XMM(val)) {
1149 exchange(node, store);
1153 if (mode_is_float(mode)) {
1154 if (ia32_cg_config.use_sse2)
1155 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1157 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1158 } else if (get_mode_size_bits(mode) == 128) {
1159 /* Spill 128 bit SSE registers */
1160 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1161 } else if (get_mode_size_bits(mode) == 8) {
1162 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1164 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1167 set_ia32_op_type(store, ia32_AddrModeD);
1168 set_ia32_ls_mode(store, mode);
1169 set_ia32_frame_ent(store, ent);
1170 set_ia32_use_frame(store);
1171 set_ia32_is_spill(store);
1172 SET_IA32_ORIG_NODE(store, node);
1173 DBG_OPT_SPILL2ST(node, store);
1176 sched_add_after(sched_point, store);
1180 exchange(node, store);
1183 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1184 dbg_info *dbg = get_irn_dbg_info(node);
1185 ir_node *block = get_nodes_block(node);
1186 ir_node *noreg = ia32_new_NoReg_gp(cg);
1187 ir_graph *irg = get_irn_irg(node);
1188 ir_node *frame = get_irg_frame(irg);
1190 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1192 set_ia32_frame_ent(push, ent);
1193 set_ia32_use_frame(push);
1194 set_ia32_op_type(push, ia32_AddrModeS);
1195 set_ia32_ls_mode(push, mode_Is);
1196 set_ia32_is_spill(push);
1198 sched_add_before(schedpoint, push);
1202 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1203 dbg_info *dbg = get_irn_dbg_info(node);
1204 ir_node *block = get_nodes_block(node);
1205 ir_node *noreg = ia32_new_NoReg_gp(cg);
1206 ir_graph *irg = get_irn_irg(node);
1207 ir_node *frame = get_irg_frame(irg);
1209 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
1211 set_ia32_frame_ent(pop, ent);
1212 set_ia32_use_frame(pop);
1213 set_ia32_op_type(pop, ia32_AddrModeD);
1214 set_ia32_ls_mode(pop, mode_Is);
1215 set_ia32_is_reload(pop);
1217 sched_add_before(schedpoint, pop);
1222 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1224 dbg_info *dbg = get_irn_dbg_info(node);
1225 ir_node *block = get_nodes_block(node);
1226 ir_mode *spmode = mode_Iu;
1227 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1230 sp = new_rd_Proj(dbg, block, pred, spmode, pos);
1231 arch_set_irn_register(sp, spreg);
1237 * Transform MemPerm, currently we do this the ugly way and produce
1238 * push/pop into/from memory cascades. This is possible without using
1241 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
1243 ir_node *block = get_nodes_block(node);
1244 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1245 int arity = be_get_MemPerm_entity_arity(node);
1246 ir_node **pops = ALLOCAN(ir_node*, arity);
1250 const ir_edge_t *edge;
1251 const ir_edge_t *next;
1254 for(i = 0; i < arity; ++i) {
1255 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1256 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1257 ir_type *enttype = get_entity_type(inent);
1258 unsigned entsize = get_type_size_bytes(enttype);
1259 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1260 ir_node *mem = get_irn_n(node, i + 1);
1263 /* work around cases where entities have different sizes */
1264 if(entsize2 < entsize)
1266 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1268 push = create_push(cg, node, node, sp, mem, inent);
1269 sp = create_spproj(node, push, pn_ia32_Push_stack);
1271 /* add another push after the first one */
1272 push = create_push(cg, node, node, sp, mem, inent);
1273 add_ia32_am_offs_int(push, 4);
1274 sp = create_spproj(node, push, pn_ia32_Push_stack);
1277 set_irn_n(node, i, new_Bad());
1281 for(i = arity - 1; i >= 0; --i) {
1282 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1283 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1284 ir_type *enttype = get_entity_type(outent);
1285 unsigned entsize = get_type_size_bytes(enttype);
1286 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1289 /* work around cases where entities have different sizes */
1290 if(entsize2 < entsize)
1292 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1294 pop = create_pop(cg, node, node, sp, outent);
1295 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1297 add_ia32_am_offs_int(pop, 4);
1299 /* add another pop after the first one */
1300 pop = create_pop(cg, node, node, sp, outent);
1301 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1308 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], block, 1, in);
1309 sched_add_before(node, keep);
1311 /* exchange memprojs */
1312 foreach_out_edge_safe(node, edge, next) {
1313 ir_node *proj = get_edge_src_irn(edge);
1314 int p = get_Proj_proj(proj);
1318 set_Proj_pred(proj, pops[p]);
1319 set_Proj_proj(proj, pn_ia32_Pop_M);
1322 /* remove memperm */
1323 arity = get_irn_arity(node);
1324 for(i = 0; i < arity; ++i) {
1325 set_irn_n(node, i, new_Bad());
1331 * Block-Walker: Calls the transform functions Spill and Reload.
1333 static void ia32_after_ra_walker(ir_node *block, void *env) {
1334 ir_node *node, *prev;
1335 ia32_code_gen_t *cg = env;
1337 /* beware: the schedule is changed here */
1338 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1339 prev = sched_prev(node);
1341 if (be_is_Reload(node)) {
1342 transform_to_Load(cg, node);
1343 } else if (be_is_Spill(node)) {
1344 transform_to_Store(cg, node);
1345 } else if (be_is_MemPerm(node)) {
1346 transform_MemPerm(cg, node);
1352 * Collects nodes that need frame entities assigned.
1354 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1356 be_fec_env_t *env = data;
1357 const ir_mode *mode;
1360 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1361 mode = get_spill_mode_mode(get_irn_mode(node));
1362 align = get_mode_size_bytes(mode);
1363 } else if (is_ia32_irn(node) &&
1364 get_ia32_frame_ent(node) == NULL &&
1365 is_ia32_use_frame(node)) {
1366 if (is_ia32_need_stackent(node))
1369 switch (get_ia32_irn_opcode(node)) {
1371 case iro_ia32_Load: {
1372 const ia32_attr_t *attr = get_ia32_attr_const(node);
1374 if (attr->data.need_32bit_stackent) {
1376 } else if (attr->data.need_64bit_stackent) {
1379 mode = get_ia32_ls_mode(node);
1380 if (is_ia32_is_reload(node))
1381 mode = get_spill_mode_mode(mode);
1383 align = get_mode_size_bytes(mode);
1387 case iro_ia32_vfild:
1389 case iro_ia32_xLoad: {
1390 mode = get_ia32_ls_mode(node);
1395 case iro_ia32_FldCW: {
1396 /* although 2 byte would be enough 4 byte performs best */
1404 panic("unexpected frame user while collection frame entity nodes");
1406 case iro_ia32_FnstCW:
1407 case iro_ia32_Store8Bit:
1408 case iro_ia32_Store:
1411 case iro_ia32_vfist:
1412 case iro_ia32_vfisttp:
1414 case iro_ia32_xStore:
1415 case iro_ia32_xStoreSimple:
1422 be_node_needs_frame_entity(env, node, mode, align);
1426 * We transform Spill and Reload here. This needs to be done before
1427 * stack biasing otherwise we would miss the corrected offset for these nodes.
1429 static void ia32_after_ra(void *self) {
1430 ia32_code_gen_t *cg = self;
1431 ir_graph *irg = cg->irg;
1432 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1434 /* create and coalesce frame entities */
1435 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1436 be_assign_entities(fec_env);
1437 be_free_frame_entity_coalescer(fec_env);
1439 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1443 * Last touchups for the graph before emit: x87 simulation to replace the
1444 * virtual with real x87 instructions, creating a block schedule and peephole
1447 static void ia32_finish(void *self) {
1448 ia32_code_gen_t *cg = self;
1449 ir_graph *irg = cg->irg;
1451 ia32_finish_irg(irg, cg);
1453 /* we might have to rewrite x87 virtual registers */
1454 if (cg->do_x87_sim) {
1455 x87_simulate_graph(cg->birg);
1458 /* do peephole optimisations */
1459 ia32_peephole_optimization(cg);
1461 /* create block schedule, this also removes empty blocks which might
1462 * produce critical edges */
1463 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1467 * Emits the code, closes the output file and frees
1468 * the code generator interface.
1470 static void ia32_codegen(void *self) {
1471 ia32_code_gen_t *cg = self;
1472 ir_graph *irg = cg->irg;
1474 ia32_gen_routine(cg, irg);
1478 /* remove it from the isa */
1481 assert(ia32_current_cg == cg);
1482 ia32_current_cg = NULL;
1484 /* de-allocate code generator */
1485 del_set(cg->reg_set);
1490 * Returns the node representing the PIC base.
1492 static ir_node *ia32_get_pic_base(void *self) {
1494 ia32_code_gen_t *cg = self;
1495 ir_node *get_eip = cg->get_eip;
1496 if (get_eip != NULL)
1499 block = get_irg_start_block(cg->irg);
1500 get_eip = new_bd_ia32_GetEIP(NULL, block);
1501 cg->get_eip = get_eip;
1503 be_dep_on_frame(get_eip);
1507 static void *ia32_cg_init(be_irg_t *birg);
1509 static const arch_code_generator_if_t ia32_code_gen_if = {
1511 ia32_get_pic_base, /* return node used as base in pic code addresses */
1512 ia32_before_abi, /* before abi introduce hook */
1515 ia32_before_ra, /* before register allocation hook */
1516 ia32_after_ra, /* after register allocation hook */
1517 ia32_finish, /* called before codegen */
1518 ia32_codegen /* emit && done */
1522 * Initializes a IA32 code generator.
1524 static void *ia32_cg_init(be_irg_t *birg) {
1525 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1526 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1528 cg->impl = &ia32_code_gen_if;
1529 cg->irg = birg->irg;
1530 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1533 cg->blk_sched = NULL;
1534 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1535 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1538 /* Linux gprof implementation needs base pointer */
1539 birg->main_env->options->omit_fp = 0;
1546 if (isa->name_obst) {
1547 obstack_free(isa->name_obst, NULL);
1548 obstack_init(isa->name_obst);
1552 cur_reg_set = cg->reg_set;
1554 assert(ia32_current_cg == NULL);
1555 ia32_current_cg = cg;
1557 return (arch_code_generator_t *)cg;
1562 /*****************************************************************
1563 * ____ _ _ _____ _____
1564 * | _ \ | | | | |_ _|/ ____| /\
1565 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1566 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1567 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1568 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1570 *****************************************************************/
1573 * Set output modes for GCC
1575 static const tarval_mode_info mo_integer = {
1582 * set the tarval output mode of all integer modes to decimal
1584 static void set_tarval_output_modes(void)
1588 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1589 ir_mode *mode = get_irp_mode(i);
1591 if (mode_is_int(mode))
1592 set_tarval_mode_output_option(mode, &mo_integer);
1596 const arch_isa_if_t ia32_isa_if;
1599 * The template that generates a new ISA object.
1600 * Note that this template can be changed by command line
1603 static ia32_isa_t ia32_isa_template = {
1605 &ia32_isa_if, /* isa interface implementation */
1606 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1607 &ia32_gp_regs[REG_EBP], /* base pointer register */
1608 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1609 -1, /* stack direction */
1610 2, /* power of two stack alignment, 2^2 == 4 */
1611 NULL, /* main environment */
1612 7, /* costs for a spill instruction */
1613 5, /* costs for a reload instruction */
1615 NULL, /* 16bit register names */
1616 NULL, /* 8bit register names */
1617 NULL, /* 8bit register names high */
1620 NULL, /* current code generator */
1621 NULL, /* abstract machine */
1623 NULL, /* name obstack */
1627 static void init_asm_constraints(void)
1629 be_init_default_asm_constraint_flags();
1631 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1632 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1633 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1634 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1635 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1636 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1637 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1638 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1639 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1640 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1641 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1642 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1643 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1644 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1645 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1646 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1647 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1648 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1649 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1650 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1652 /* no support for autodecrement/autoincrement */
1653 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1654 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1655 /* no float consts */
1656 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1657 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1658 /* makes no sense on x86 */
1659 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1660 /* no support for sse consts yet */
1661 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1662 /* no support for x87 consts yet */
1663 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1664 /* no support for mmx registers yet */
1665 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1666 /* not available in 32bit mode */
1667 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1668 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1670 /* no code yet to determine register class needed... */
1671 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1675 * Initializes the backend ISA.
1677 static arch_env_t *ia32_init(FILE *file_handle) {
1678 static int inited = 0;
1686 set_tarval_output_modes();
1688 isa = XMALLOC(ia32_isa_t);
1689 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1691 if(mode_fpcw == NULL) {
1692 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1695 ia32_register_init();
1696 ia32_create_opcodes(&ia32_irn_ops);
1698 be_emit_init(file_handle);
1699 isa->regs_16bit = pmap_create();
1700 isa->regs_8bit = pmap_create();
1701 isa->regs_8bit_high = pmap_create();
1702 isa->types = pmap_create();
1703 isa->tv_ent = pmap_create();
1704 isa->cpu = ia32_init_machine_description();
1706 ia32_build_16bit_reg_map(isa->regs_16bit);
1707 ia32_build_8bit_reg_map(isa->regs_8bit);
1708 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1711 isa->name_obst = XMALLOC(struct obstack);
1712 obstack_init(isa->name_obst);
1715 /* enter the ISA object into the intrinsic environment */
1716 intrinsic_env.isa = isa;
1718 /* emit asm includes */
1719 n = get_irp_n_asms();
1720 for (i = 0; i < n; ++i) {
1721 be_emit_cstring("#APP\n");
1722 be_emit_ident(get_irp_asm(i));
1723 be_emit_cstring("\n#NO_APP\n");
1726 /* needed for the debug support */
1727 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1728 be_emit_cstring(".Ltext0:\n");
1729 be_emit_write_line();
1731 /* we mark referenced global entities, so we can only emit those which
1732 * are actually referenced. (Note: you mustn't use the type visited flag
1733 * elsewhere in the backend)
1735 inc_master_type_visited();
1737 return &isa->arch_env;
1743 * Closes the output file and frees the ISA structure.
1745 static void ia32_done(void *self) {
1746 ia32_isa_t *isa = self;
1748 /* emit now all global declarations */
1749 be_gas_emit_decls(isa->arch_env.main_env, 1);
1751 pmap_destroy(isa->regs_16bit);
1752 pmap_destroy(isa->regs_8bit);
1753 pmap_destroy(isa->regs_8bit_high);
1754 pmap_destroy(isa->tv_ent);
1755 pmap_destroy(isa->types);
1758 obstack_free(isa->name_obst, NULL);
1768 * Return the number of register classes for this architecture.
1769 * We report always these:
1770 * - the general purpose registers
1771 * - the SSE floating point register set
1772 * - the virtual floating point registers
1773 * - the SSE vector register set
1775 static unsigned ia32_get_n_reg_class(const void *self) {
1781 * Return the register class for index i.
1783 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1787 assert(i < N_CLASSES);
1788 return &ia32_reg_classes[i];
1792 * Get the register class which shall be used to store a value of a given mode.
1793 * @param self The this pointer.
1794 * @param mode The mode in question.
1795 * @return A register class which can hold values of the given mode.
1797 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1798 const ir_mode *mode)
1802 if (mode_is_float(mode)) {
1803 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1806 return &ia32_reg_classes[CLASS_ia32_gp];
1810 * Get the ABI restrictions for procedure calls.
1811 * @param self The this pointer.
1812 * @param method_type The type of the method (procedure) in question.
1813 * @param abi The abi object to be modified
1815 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1823 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1827 /* set abi flags for calls */
1828 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1829 call_flags.bits.store_args_sequential = 0;
1830 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1831 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1832 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1834 /* set parameter passing style */
1835 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1837 cc = get_method_calling_convention(method_type);
1838 if (get_method_variadicity(method_type) == variadicity_variadic) {
1839 /* pass all parameters of a variadic function on the stack */
1840 cc = cc_cdecl_set | (cc & cc_this_call);
1842 if (get_method_additional_properties(method_type) & mtp_property_private &&
1843 ia32_cg_config.optimize_cc) {
1844 /* set the fast calling conventions (allowing up to 3) */
1845 cc = SET_FASTCALL(cc) | 3;
1849 /* we have to pop the shadow parameter ourself for compound calls */
1850 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1851 && !(cc & cc_reg_param)) {
1852 pop_amount += get_mode_size_bytes(mode_P_data);
1855 n = get_method_n_params(method_type);
1856 for (i = regnum = 0; i < n; i++) {
1858 const arch_register_t *reg = NULL;
1860 tp = get_method_param_type(method_type, i);
1861 mode = get_type_mode(tp);
1863 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1866 be_abi_call_param_reg(abi, i, reg);
1869 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1870 * movl has a shorter opcode than mov[sz][bw]l */
1871 ir_mode *load_mode = mode;
1874 unsigned size = get_mode_size_bytes(mode);
1876 if (cc & cc_callee_clear_stk) {
1877 pop_amount += (size + 3U) & ~3U;
1880 if (size < 4) load_mode = mode_Iu;
1883 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1887 be_abi_call_set_pop(abi, pop_amount);
1889 /* set return registers */
1890 n = get_method_n_ress(method_type);
1892 assert(n <= 2 && "more than two results not supported");
1894 /* In case of 64bit returns, we will have two 32bit values */
1896 tp = get_method_res_type(method_type, 0);
1897 mode = get_type_mode(tp);
1899 assert(!mode_is_float(mode) && "two FP results not supported");
1901 tp = get_method_res_type(method_type, 1);
1902 mode = get_type_mode(tp);
1904 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1906 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1907 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1910 const arch_register_t *reg;
1912 tp = get_method_res_type(method_type, 0);
1913 assert(is_atomic_type(tp));
1914 mode = get_type_mode(tp);
1916 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1918 be_abi_call_res_reg(abi, 0, reg);
1922 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1926 if(!is_ia32_irn(irn)) {
1930 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1931 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1932 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1933 || is_ia32_Immediate(irn))
1940 * Initializes the code generator interface.
1942 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1945 return &ia32_code_gen_if;
1949 * Returns the estimated execution time of an ia32 irn.
1951 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1953 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1956 list_sched_selector_t ia32_sched_selector;
1959 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1961 static const list_sched_selector_t *ia32_get_list_sched_selector(
1962 const void *self, list_sched_selector_t *selector)
1965 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1966 ia32_sched_selector.exectime = ia32_sched_exectime;
1967 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1968 return &ia32_sched_selector;
1971 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1978 * Returns the necessary byte alignment for storing a register of given class.
1980 static int ia32_get_reg_class_alignment(const void *self,
1981 const arch_register_class_t *cls)
1983 ir_mode *mode = arch_register_class_mode(cls);
1984 int bytes = get_mode_size_bytes(mode);
1987 if (mode_is_float(mode) && bytes > 8)
1992 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1993 const void *self, const ir_node *irn)
1995 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1996 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1997 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2000 static const be_execution_unit_t *_allowed_units_GP[] = {
2001 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2002 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2003 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2004 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2005 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2006 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2007 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2010 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2011 &be_machine_execution_units_DUMMY[0],
2014 static const be_execution_unit_t **_units_callret[] = {
2015 _allowed_units_BRANCH,
2018 static const be_execution_unit_t **_units_other[] = {
2022 static const be_execution_unit_t **_units_dummy[] = {
2023 _allowed_units_DUMMY,
2026 const be_execution_unit_t ***ret;
2029 if (is_ia32_irn(irn)) {
2030 ret = get_ia32_exec_units(irn);
2031 } else if (is_be_node(irn)) {
2032 if (be_is_Return(irn)) {
2033 ret = _units_callret;
2034 } else if (be_is_Barrier(irn)) {
2048 * Return the abstract ia32 machine.
2050 static const be_machine_t *ia32_get_machine(const void *self) {
2051 const ia32_isa_t *isa = self;
2056 * Return irp irgs in the desired order.
2058 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2065 static void ia32_mark_remat(const void *self, ir_node *node) {
2067 if (is_ia32_irn(node)) {
2068 set_ia32_is_remat(node);
2073 * Check for Abs or -Abs.
2075 static int psi_is_Abs_or_Nabs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) {
2082 /* must be <, <=, >=, > */
2083 pnc = get_Proj_proj(sel);
2084 if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
2085 pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
2088 l = get_Cmp_left(cmp);
2089 r = get_Cmp_right(cmp);
2091 /* must be x cmp 0 */
2092 if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
2095 if ((!is_Minus(t) || get_Minus_op(t) != f) &&
2096 (!is_Minus(f) || get_Minus_op(f) != t))
2102 * Check for Abs only
2104 static int psi_is_Abs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) {
2111 /* must be <, <=, >=, > */
2112 pnc = get_Proj_proj(sel);
2113 if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
2114 pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
2117 l = get_Cmp_left(cmp);
2118 r = get_Cmp_right(cmp);
2120 /* must be x cmp 0 */
2121 if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
2124 if ((!is_Minus(t) || get_Minus_op(t) != f) &&
2125 (!is_Minus(f) || get_Minus_op(f) != t))
2128 if (pnc & pn_Cmp_Gt) {
2129 /* x >= 0 ? -x : x is NABS */
2133 /* x < 0 ? x : -x is NABS */
2142 * Allows or disallows the creation of Mux nodes for the given Phi nodes.
2144 * @param sel A selector of a Cond.
2145 * @param phi_list List of Phi nodes about to be converted (linked via get_Phi_next() field)
2146 * @param i First data predecessor involved in if conversion
2147 * @param j Second data predecessor involved in if conversion
2149 * @return 1 if allowed, 0 otherwise
2151 static int ia32_is_mux_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2158 /* we can't handle Muxs with 64bit compares yet */
2160 cmp = get_Proj_pred(sel);
2162 ir_node *left = get_Cmp_left(cmp);
2163 ir_mode *cmp_mode = get_irn_mode(left);
2164 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32) {
2165 /* 64bit Abs IS supported */
2166 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2167 ir_node *t = get_Phi_pred(phi, i);
2168 ir_node *f = get_Phi_pred(phi, j);
2170 if (! psi_is_Abs(cmp, sel, t, f))
2176 /* we do not support nodes without Cmp yet */
2180 /* we do not support nodes without Cmp yet */
2184 pn = get_Proj_proj(sel);
2185 cl = get_Cmp_left(cmp);
2186 cr = get_Cmp_right(cmp);
2188 if (ia32_cg_config.use_cmov) {
2189 if (ia32_cg_config.use_sse2) {
2190 /* check the Phi nodes: no 64bit and no floating point cmov */
2191 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2192 ir_mode *mode = get_irn_mode(phi);
2194 if (mode_is_float(mode)) {
2195 /* check for Min, Max */
2196 ir_node *t = get_Phi_pred(phi, i);
2197 ir_node *f = get_Phi_pred(phi, j);
2199 /* SSE2 supports Min & Max */
2200 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2201 if (cl == t && cr == f) {
2202 /* Mux(a <=/>= b, a, b) => MIN, MAX */
2204 } else if (cl == f && cr == t) {
2205 /* Mux(a <=/>= b, b, a) => MAX, MIN */
2210 } else if (get_mode_size_bits(mode) > 32) {
2216 /* check the Phi nodes: no 64bit and no floating point cmov */
2217 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2218 ir_mode *mode = get_irn_mode(phi);
2220 if (mode_is_float(mode)) {
2221 ir_node *t = get_Phi_pred(phi, i);
2222 ir_node *f = get_Phi_pred(phi, j);
2224 /* always support Mux(!float, C1, C2) */
2225 if (is_Const(t) && is_Const(f) && !mode_is_float(get_irn_mode(cl))) {
2226 switch (be_transformer) {
2227 case TRANSFORMER_DEFAULT:
2228 /* always support Mux(!float, C1, C2) */
2230 #ifdef FIRM_GRGEN_BE
2231 case TRANSFORMER_PBQP:
2232 case TRANSFORMER_RAND:
2233 /* no support for Mux(*, C1, C2) */
2237 panic("invalid transformer");
2240 /* only abs or nabs supported */
2241 if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
2243 } else if (get_mode_size_bits(mode) > 32)
2249 } else { /* No Cmov, only some special cases */
2251 /* Now some supported cases here */
2252 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2253 ir_mode *mode = get_irn_mode(phi);
2256 t = get_Phi_pred(phi, i);
2257 f = get_Phi_pred(phi, j);
2259 if (mode_is_float(mode)) {
2260 /* always support Mux(!float, C1, C2) */
2261 if (is_Const(t) && is_Const(f) &&
2262 !mode_is_float(get_irn_mode(cl))) {
2263 switch (be_transformer) {
2264 case TRANSFORMER_DEFAULT:
2265 /* always support Mux(!float, C1, C2) */
2267 #ifdef FIRM_GRGEN_BE
2268 case TRANSFORMER_PBQP:
2269 case TRANSFORMER_RAND:
2270 /* no support for Mux(*, C1, C2) */
2274 panic("invalid transformer");
2277 /* only abs or nabs supported */
2278 if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
2280 } else if (get_mode_size_bits(mode) > 32) {
2285 if (is_Const(t) && is_Const(f)) {
2286 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2287 /* always support Mux(x, C1, C2) */
2290 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2292 if (cl == t && cr == f) {
2293 /* Mux(a <=/>= b, a, b) => Min, Max */
2296 if (cl == f && cr == t) {
2297 /* Mux(a <=/>= b, b, a) => Max, Min */
2301 if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2302 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2303 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2304 /* Mux(a >=u b, a - b, 0) unsigned Doz */
2307 if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2308 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2309 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2310 /* Mux(a <=u b, 0, a - b) unsigned Doz */
2313 if (is_Const(cr) && is_Const_null(cr)) {
2314 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2315 /* Mux(a <=/>= 0 ? a : -a) Nabs/Abs */
2317 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2318 /* Mux(a <=/>= 0 ? -a : a) Abs/Nabs */
2325 /* all checks passed */
2331 static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
2336 /* we already added all our simple flags to the flags modifier list in
2337 * init, so this flag we don't know. */
2338 return ASM_CONSTRAINT_FLAG_INVALID;
2341 static int ia32_is_valid_clobber(const void *self, const char *clobber)
2345 return ia32_get_clobber_register(clobber) != NULL;
2349 * Create the trampoline code.
2351 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2353 ir_node *st, *p = trampoline;
2354 ir_mode *mode = get_irn_mode(p);
2357 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
2358 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2359 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2360 st = new_r_Store(block, mem, p, env, 0);
2361 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2362 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2364 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
2365 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2366 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2367 st = new_r_Store(block, mem, p, callee, 0);
2368 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2369 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2375 * Returns the libFirm configuration parameter for this backend.
2377 static const backend_params *ia32_get_libfirm_params(void) {
2378 static const ir_settings_if_conv_t ifconv = {
2379 4, /* maxdepth, doesn't matter for Mux-conversion */
2380 ia32_is_mux_allowed /* allows or disallows Mux creation for given selector */
2382 static const ir_settings_arch_dep_t ad = {
2383 1, /* also use subs */
2384 4, /* maximum shifts */
2385 31, /* maximum shift amount */
2386 ia32_evaluate_insn, /* evaluate the instruction sequence */
2388 1, /* allow Mulhs */
2389 1, /* allow Mulus */
2390 32, /* Mulh allowed up to 32 bit */
2392 static backend_params p = {
2393 1, /* need dword lowering */
2394 1, /* support inline assembly */
2395 NULL, /* will be set later */
2396 ia32_create_intrinsic_fkt,
2397 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2398 NULL, /* ifconv info will be set below */
2399 NULL, /* float arithmetic mode, will be set below */
2400 12, /* size of trampoline code */
2401 4, /* alignment of trampoline code */
2402 ia32_create_trampoline_fkt,
2403 4 /* alignment of stack parameter */
2406 ia32_setup_cg_config();
2408 /* doesn't really belong here, but this is the earliest place the backend
2410 init_asm_constraints();
2413 p.if_conv_info = &ifconv;
2414 if (! ia32_cg_config.use_sse2)
2415 p.mode_float_arithmetic = mode_E;
2419 static const lc_opt_enum_int_items_t gas_items[] = {
2420 { "elf", GAS_FLAVOUR_ELF },
2421 { "mingw", GAS_FLAVOUR_MINGW },
2422 { "yasm", GAS_FLAVOUR_YASM },
2423 { "macho", GAS_FLAVOUR_MACH_O },
2427 static lc_opt_enum_int_var_t gas_var = {
2428 (int*) &be_gas_flavour, gas_items
2431 #ifdef FIRM_GRGEN_BE
2432 static const lc_opt_enum_int_items_t transformer_items[] = {
2433 { "default", TRANSFORMER_DEFAULT },
2434 { "pbqp", TRANSFORMER_PBQP },
2435 { "random", TRANSFORMER_RAND },
2439 static lc_opt_enum_int_var_t transformer_var = {
2440 (int*)&be_transformer, transformer_items
2444 static const lc_opt_table_entry_t ia32_options[] = {
2445 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2446 #ifdef FIRM_GRGEN_BE
2447 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2449 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2450 &ia32_isa_template.arch_env.stack_alignment),
2454 const arch_isa_if_t ia32_isa_if = {
2457 ia32_handle_intrinsics,
2458 ia32_get_n_reg_class,
2460 ia32_get_reg_class_for_mode,
2462 ia32_get_code_generator_if,
2463 ia32_get_list_sched_selector,
2464 ia32_get_ilp_sched_selector,
2465 ia32_get_reg_class_alignment,
2466 ia32_get_libfirm_params,
2467 ia32_get_allowed_execution_units,
2471 ia32_parse_asm_constraint,
2472 ia32_is_valid_clobber
2475 void be_init_arch_ia32(void)
2477 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2478 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2480 lc_opt_add_table(ia32_grp, ia32_options);
2481 be_register_isa_if("ia32", &ia32_isa_if);
2483 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2485 ia32_init_emitter();
2487 ia32_init_optimize();
2488 ia32_init_transform();
2490 ia32_init_architecture();
2493 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);