2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
28 #include "lc_opts_enum.h"
36 #include "iredges_t.h"
49 #include "iroptimize.h"
50 #include "instrument.h"
53 #include "lower_calls.h"
54 #include "lower_mode_b.h"
55 #include "lower_softfloat.h"
65 #include "beblocksched.h"
66 #include "bespillutil.h"
67 #include "bespillslots.h"
72 #include "betranshlp.h"
73 #include "belistsched.h"
74 #include "beabihelper.h"
77 #include "bearch_ia32_t.h"
79 #include "ia32_new_nodes.h"
80 #include "gen_ia32_regalloc_if.h"
81 #include "ia32_common_transform.h"
82 #include "ia32_transform.h"
83 #include "ia32_emitter.h"
84 #include "ia32_optimize.h"
86 #include "ia32_dbg_stat.h"
87 #include "ia32_finish.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
94 transformer_t be_transformer = TRANSFORMER_DEFAULT;
97 ir_mode *ia32_mode_fpcw;
101 /** The current omit-fp state */
102 static ir_type *omit_fp_between_type = NULL;
103 static ir_type *between_type = NULL;
104 static ir_entity *old_bp_ent = NULL;
105 static ir_entity *ret_addr_ent = NULL;
106 static ir_entity *omit_fp_ret_addr_ent = NULL;
109 * The environment for the intrinsic mapping.
111 static ia32_intrinsic_env_t intrinsic_env = {
113 NULL, /* the irg, these entities belong to */
114 NULL, /* entity for __divdi3 library call */
115 NULL, /* entity for __moddi3 library call */
116 NULL, /* entity for __udivdi3 library call */
117 NULL, /* entity for __umoddi3 library call */
121 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
124 * Used to create per-graph unique pseudo nodes.
126 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
127 create_const_node_func func,
128 const arch_register_t* reg)
130 ir_node *block, *res;
135 block = get_irg_start_block(irg);
136 res = func(NULL, block);
137 arch_set_irn_register(res, reg);
143 /* Creates the unique per irg GP NoReg node. */
144 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
146 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
147 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
148 &ia32_registers[REG_GP_NOREG]);
151 ir_node *ia32_new_NoReg_fp(ir_graph *irg)
153 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
154 return create_const(irg, &irg_data->noreg_fp, new_bd_ia32_NoReg_FP,
155 &ia32_registers[REG_FP_NOREG]);
158 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
160 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
161 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
162 &ia32_registers[REG_XMM_NOREG]);
165 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
167 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
168 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
169 &ia32_registers[REG_FPCW]);
174 * Returns the admissible noreg register node for input register pos of node irn.
176 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
178 ir_graph *irg = get_irn_irg(irn);
179 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
181 assert(req != NULL && "Missing register requirements");
182 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
183 return ia32_new_NoReg_gp(irg);
185 if (ia32_cg_config.use_sse2) {
186 return ia32_new_NoReg_xmm(irg);
188 return ia32_new_NoReg_fp(irg);
192 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
194 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
197 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
199 if (is_be_node(node))
200 be_node_set_frame_entity(node, entity);
202 set_ia32_frame_ent(node, entity);
205 static void ia32_set_frame_offset(ir_node *irn, int bias)
207 if (get_ia32_frame_ent(irn) == NULL)
210 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
211 ir_graph *irg = get_irn_irg(irn);
212 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
213 if (layout->sp_relative) {
214 /* Pop nodes modify the stack pointer before calculating the
215 * destination address, so fix this here
220 add_ia32_am_offs_int(irn, bias);
223 static int ia32_get_sp_bias(const ir_node *node)
225 if (is_ia32_Call(node))
226 return -(int)get_ia32_call_attr_const(node)->pop;
228 if (is_ia32_Push(node))
231 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
234 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
235 return SP_BIAS_RESET;
242 * Build the between type and entities if not already build.
244 static void ia32_build_between_type(void)
246 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
247 if (between_type == NULL) {
248 ir_type *old_bp_type = new_type_primitive(mode_Iu);
249 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
251 between_type = new_type_struct(IDENT("ia32_between_type"));
252 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
253 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
255 set_entity_offset(old_bp_ent, 0);
256 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
257 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
258 set_type_state(between_type, layout_fixed);
260 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
261 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
263 set_entity_offset(omit_fp_ret_addr_ent, 0);
264 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
265 set_type_state(omit_fp_between_type, layout_fixed);
271 * Produces the type which sits between the stack args and the locals on the stack.
272 * it will contain the return address and space to store the old base pointer.
273 * @return The Firm type modeling the ABI between type.
275 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
277 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
278 ia32_build_between_type();
279 return layout->sp_relative ? omit_fp_between_type : between_type;
283 * Return the stack entity that contains the return address.
285 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
287 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
288 ia32_build_between_type();
289 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
293 * Return the stack entity that contains the frame address.
295 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
297 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
298 ia32_build_between_type();
299 return layout->sp_relative ? NULL : old_bp_ent;
303 * Get the estimated cycle count for @p irn.
305 * @param self The this pointer.
306 * @param irn The node.
308 * @return The estimated cycle count for this operation
310 static int ia32_get_op_estimated_cost(const ir_node *irn)
313 ia32_op_type_t op_tp;
317 if (!is_ia32_irn(irn))
320 assert(is_ia32_irn(irn));
322 cost = get_ia32_latency(irn);
323 op_tp = get_ia32_op_type(irn);
325 if (is_ia32_CopyB(irn)) {
328 else if (is_ia32_CopyB_i(irn)) {
329 int size = get_ia32_copyb_size(irn);
330 cost = 20 + (int)ceil((4/3) * size);
332 /* in case of address mode operations add additional cycles */
333 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
335 In case of stack access and access to fixed addresses add 5 cycles
336 (we assume they are in cache), other memory operations cost 20
339 if (is_ia32_use_frame(irn) || (
340 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
341 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
352 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
354 if (mode_is_float(mode))
361 * Get the mode that should be used for spilling value node
363 static ir_mode *get_spill_mode(const ir_node *node)
365 ir_mode *mode = get_irn_mode(node);
366 return get_spill_mode_mode(mode);
370 * Checks whether an addressmode reload for a node with mode mode is compatible
371 * with a spillslot of mode spill_mode
373 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
375 return !mode_is_float(mode) || mode == spillmode;
379 * Check if irn can load its operand at position i from memory (source addressmode).
380 * @param irn The irn to be checked
381 * @param i The operands position
382 * @return Non-Zero if operand can be loaded
384 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
386 ir_node *op = get_irn_n(irn, i);
387 const ir_mode *mode = get_irn_mode(op);
388 const ir_mode *spillmode = get_spill_mode(op);
390 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
391 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
392 !ia32_is_spillmode_compatible(mode, spillmode) ||
393 is_ia32_use_frame(irn)) /* must not already use frame */
396 switch (get_ia32_am_support(irn)) {
401 if (i != n_ia32_unary_op)
407 case n_ia32_binary_left: {
408 const arch_register_req_t *req;
409 if (!is_ia32_commutative(irn))
412 /* we can't swap left/right for limited registers
413 * (As this (currently) breaks constraint handling copies)
415 req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
416 if (req->type & arch_register_req_type_limited)
421 case n_ia32_binary_right:
430 panic("Unknown AM type");
433 /* HACK: must not already use "real" memory.
434 * This can happen for Call and Div */
435 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
441 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
445 ir_mode *dest_op_mode;
447 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
449 set_ia32_op_type(irn, ia32_AddrModeS);
451 load_mode = get_irn_mode(get_irn_n(irn, i));
452 dest_op_mode = get_ia32_ls_mode(irn);
453 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
454 set_ia32_ls_mode(irn, load_mode);
456 set_ia32_use_frame(irn);
457 set_ia32_need_stackent(irn);
459 if (i == n_ia32_binary_left &&
460 get_ia32_am_support(irn) == ia32_am_binary &&
461 /* immediates are only allowed on the right side */
462 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
463 ia32_swap_left_right(irn);
464 i = n_ia32_binary_right;
467 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
469 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
470 set_irn_n(irn, n_ia32_mem, spill);
471 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
472 set_ia32_is_reload(irn);
475 static const be_abi_callbacks_t ia32_abi_callbacks = {
476 ia32_abi_get_between_type,
479 /* register allocator interface */
480 static const arch_irn_ops_t ia32_irn_ops = {
481 ia32_get_frame_entity,
482 ia32_set_frame_offset,
484 ia32_get_op_estimated_cost,
485 ia32_possible_memory_operand,
486 ia32_perform_memory_operand,
489 static ir_entity *mcount = NULL;
490 static int gprof = 0;
492 static void ia32_before_abi(ir_graph *irg)
495 if (mcount == NULL) {
496 ir_type *tp = new_type_method(0, 0);
497 ident *id = new_id_from_str("mcount");
498 mcount = new_entity(get_glob_type(), id, tp);
499 /* FIXME: enter the right ld_ident here */
500 set_entity_ld_ident(mcount, get_entity_ident(mcount));
501 set_entity_visibility(mcount, ir_visibility_external);
503 instrument_initcall(irg, mcount);
508 * Transforms the standard firm graph into
511 static void ia32_prepare_graph(ir_graph *irg)
513 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
516 switch (be_transformer) {
517 case TRANSFORMER_DEFAULT:
518 /* transform remaining nodes into assembler instructions */
519 ia32_transform_graph(irg);
522 case TRANSFORMER_PBQP:
523 case TRANSFORMER_RAND:
524 /* transform nodes into assembler instructions by PBQP magic */
525 ia32_transform_graph_by_pbqp(irg);
529 panic("invalid transformer");
532 ia32_transform_graph(irg);
535 /* do local optimizations (mainly CSE) */
536 optimize_graph_df(irg);
537 /* backend code expects that outedges are always enabled */
541 dump_ir_graph(irg, "transformed");
543 /* optimize address mode */
544 ia32_optimize_graph(irg);
546 /* do code placement, to optimize the position of constants */
548 /* backend code expects that outedges are always enabled */
552 dump_ir_graph(irg, "place");
555 ir_node *ia32_turn_back_am(ir_node *node)
557 dbg_info *dbgi = get_irn_dbg_info(node);
558 ir_graph *irg = get_irn_irg(node);
559 ir_node *block = get_nodes_block(node);
560 ir_node *base = get_irn_n(node, n_ia32_base);
561 ir_node *idx = get_irn_n(node, n_ia32_index);
562 ir_node *mem = get_irn_n(node, n_ia32_mem);
565 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
566 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
568 ia32_copy_am_attrs(load, node);
569 if (is_ia32_is_reload(node))
570 set_ia32_is_reload(load);
571 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
573 switch (get_ia32_am_support(node)) {
575 set_irn_n(node, n_ia32_unary_op, load_res);
579 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
580 set_irn_n(node, n_ia32_binary_left, load_res);
582 set_irn_n(node, n_ia32_binary_right, load_res);
587 panic("Unknown AM type");
589 noreg = ia32_new_NoReg_gp(current_ir_graph);
590 set_irn_n(node, n_ia32_base, noreg);
591 set_irn_n(node, n_ia32_index, noreg);
592 set_ia32_am_offs_int(node, 0);
593 set_ia32_am_sc(node, NULL);
594 set_ia32_am_scale(node, 0);
595 clear_ia32_am_sc_sign(node);
597 /* rewire mem-proj */
598 if (get_irn_mode(node) == mode_T) {
599 foreach_out_edge(node, edge) {
600 ir_node *out = get_edge_src_irn(edge);
601 if (get_irn_mode(out) == mode_M) {
602 set_Proj_pred(out, load);
603 set_Proj_proj(out, pn_ia32_Load_M);
609 set_ia32_op_type(node, ia32_Normal);
610 if (sched_is_scheduled(node))
611 sched_add_before(node, load);
616 static ir_node *flags_remat(ir_node *node, ir_node *after)
618 /* we should turn back source address mode when rematerializing nodes */
623 if (is_Block(after)) {
626 block = get_nodes_block(after);
629 type = get_ia32_op_type(node);
632 ia32_turn_back_am(node);
636 /* TODO implement this later... */
637 panic("found DestAM with flag user %+F this should not happen", node);
639 default: assert(type == ia32_Normal); break;
642 copy = exact_copy(node);
643 set_nodes_block(copy, block);
644 sched_add_after(after, copy);
650 * Called before the register allocator.
652 static void ia32_before_ra(ir_graph *irg)
654 /* setup fpu rounding modes */
655 ia32_setup_fpu_mode(irg);
658 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
661 be_add_missing_keeps(irg);
666 * Transforms a be_Reload into a ia32 Load.
668 static void transform_to_Load(ir_node *node)
670 ir_graph *irg = get_irn_irg(node);
671 dbg_info *dbgi = get_irn_dbg_info(node);
672 ir_node *block = get_nodes_block(node);
673 ir_entity *ent = be_get_frame_entity(node);
674 ir_mode *mode = get_irn_mode(node);
675 ir_mode *spillmode = get_spill_mode(node);
676 ir_node *noreg = ia32_new_NoReg_gp(irg);
677 ir_node *sched_point = NULL;
678 ir_node *ptr = get_irg_frame(irg);
679 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
680 ir_node *new_op, *proj;
681 const arch_register_t *reg;
683 if (sched_is_scheduled(node)) {
684 sched_point = sched_prev(node);
687 if (mode_is_float(spillmode)) {
688 if (ia32_cg_config.use_sse2)
689 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
691 new_op = new_bd_ia32_fld(dbgi, block, ptr, noreg, mem, spillmode);
693 else if (get_mode_size_bits(spillmode) == 128) {
694 /* Reload 128 bit SSE registers */
695 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
698 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
700 set_ia32_op_type(new_op, ia32_AddrModeS);
701 set_ia32_ls_mode(new_op, spillmode);
702 set_ia32_frame_ent(new_op, ent);
703 set_ia32_use_frame(new_op);
704 set_ia32_is_reload(new_op);
706 DBG_OPT_RELOAD2LD(node, new_op);
708 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
711 sched_add_after(sched_point, new_op);
715 /* copy the register from the old node to the new Load */
716 reg = arch_get_irn_register(node);
717 arch_set_irn_register(proj, reg);
719 SET_IA32_ORIG_NODE(new_op, node);
721 exchange(node, proj);
725 * Transforms a be_Spill node into a ia32 Store.
727 static void transform_to_Store(ir_node *node)
729 ir_graph *irg = get_irn_irg(node);
730 dbg_info *dbgi = get_irn_dbg_info(node);
731 ir_node *block = get_nodes_block(node);
732 ir_entity *ent = be_get_frame_entity(node);
733 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
734 ir_mode *mode = get_spill_mode(spillval);
735 ir_node *noreg = ia32_new_NoReg_gp(irg);
736 ir_node *nomem = get_irg_no_mem(irg);
737 ir_node *ptr = get_irg_frame(irg);
738 ir_node *val = get_irn_n(node, n_be_Spill_val);
741 ir_node *sched_point = NULL;
743 if (sched_is_scheduled(node)) {
744 sched_point = sched_prev(node);
747 if (mode_is_float(mode)) {
748 if (ia32_cg_config.use_sse2) {
749 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
750 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
752 store = new_bd_ia32_fst(dbgi, block, ptr, noreg, nomem, val, mode);
753 res = new_r_Proj(store, mode_M, pn_ia32_fst_M);
755 } else if (get_mode_size_bits(mode) == 128) {
756 /* Spill 128 bit SSE registers */
757 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
758 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
759 } else if (get_mode_size_bits(mode) == 8) {
760 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
761 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
763 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
764 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
767 set_ia32_op_type(store, ia32_AddrModeD);
768 set_ia32_ls_mode(store, mode);
769 set_ia32_frame_ent(store, ent);
770 set_ia32_use_frame(store);
771 set_ia32_is_spill(store);
772 SET_IA32_ORIG_NODE(store, node);
773 DBG_OPT_SPILL2ST(node, store);
776 sched_add_after(sched_point, store);
783 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
785 dbg_info *dbgi = get_irn_dbg_info(node);
786 ir_node *block = get_nodes_block(node);
787 ir_graph *irg = get_irn_irg(node);
788 ir_node *noreg = ia32_new_NoReg_gp(irg);
789 ir_node *frame = get_irg_frame(irg);
791 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
793 set_ia32_frame_ent(push, ent);
794 set_ia32_use_frame(push);
795 set_ia32_op_type(push, ia32_AddrModeS);
796 set_ia32_ls_mode(push, mode_Is);
797 set_ia32_is_spill(push);
799 sched_add_before(schedpoint, push);
803 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
805 dbg_info *dbgi = get_irn_dbg_info(node);
806 ir_node *block = get_nodes_block(node);
807 ir_graph *irg = get_irn_irg(node);
808 ir_node *noreg = ia32_new_NoReg_gp(irg);
809 ir_node *frame = get_irg_frame(irg);
811 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
812 get_irg_no_mem(irg), sp);
814 set_ia32_frame_ent(pop, ent);
815 set_ia32_use_frame(pop);
816 set_ia32_op_type(pop, ia32_AddrModeD);
817 set_ia32_ls_mode(pop, mode_Is);
818 set_ia32_is_reload(pop);
820 sched_add_before(schedpoint, pop);
825 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
827 dbg_info *dbgi = get_irn_dbg_info(node);
828 ir_mode *spmode = mode_Iu;
829 const arch_register_t *spreg = &ia32_registers[REG_ESP];
832 sp = new_rd_Proj(dbgi, pred, spmode, pos);
833 arch_set_irn_register(sp, spreg);
839 * Transform MemPerm, currently we do this the ugly way and produce
840 * push/pop into/from memory cascades. This is possible without using
843 static void transform_MemPerm(ir_node *node)
845 ir_node *block = get_nodes_block(node);
846 ir_graph *irg = get_irn_irg(node);
847 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
848 int arity = be_get_MemPerm_entity_arity(node);
849 ir_node **pops = ALLOCAN(ir_node*, arity);
855 for (i = 0; i < arity; ++i) {
856 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
857 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
858 ir_type *enttype = get_entity_type(inent);
859 unsigned entsize = get_type_size_bytes(enttype);
860 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
861 ir_node *mem = get_irn_n(node, i + 1);
864 /* work around cases where entities have different sizes */
865 if (entsize2 < entsize)
867 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
869 push = create_push(node, node, sp, mem, inent);
870 sp = create_spproj(node, push, pn_ia32_Push_stack);
872 /* add another push after the first one */
873 push = create_push(node, node, sp, mem, inent);
874 add_ia32_am_offs_int(push, 4);
875 sp = create_spproj(node, push, pn_ia32_Push_stack);
878 set_irn_n(node, i, new_r_Bad(irg, mode_X));
882 for (i = arity - 1; i >= 0; --i) {
883 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
884 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
885 ir_type *enttype = get_entity_type(outent);
886 unsigned entsize = get_type_size_bytes(enttype);
887 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
890 /* work around cases where entities have different sizes */
891 if (entsize2 < entsize)
893 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
895 pop = create_pop(node, node, sp, outent);
896 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
898 add_ia32_am_offs_int(pop, 4);
900 /* add another pop after the first one */
901 pop = create_pop(node, node, sp, outent);
902 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
909 keep = be_new_Keep(block, 1, in);
910 sched_add_before(node, keep);
912 /* exchange memprojs */
913 foreach_out_edge_safe(node, edge) {
914 ir_node *proj = get_edge_src_irn(edge);
915 int p = get_Proj_proj(proj);
919 set_Proj_pred(proj, pops[p]);
920 set_Proj_proj(proj, pn_ia32_Pop_M);
929 * Block-Walker: Calls the transform functions Spill and Reload.
931 static void ia32_after_ra_walker(ir_node *block, void *env)
933 ir_node *node, *prev;
936 /* beware: the schedule is changed here */
937 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
938 prev = sched_prev(node);
940 if (be_is_Reload(node)) {
941 transform_to_Load(node);
942 } else if (be_is_Spill(node)) {
943 transform_to_Store(node);
944 } else if (be_is_MemPerm(node)) {
945 transform_MemPerm(node);
951 * Collects nodes that need frame entities assigned.
953 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
955 be_fec_env_t *env = (be_fec_env_t*)data;
959 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
960 mode = get_spill_mode_mode(get_irn_mode(node));
961 align = get_mode_size_bytes(mode);
962 } else if (is_ia32_irn(node) &&
963 get_ia32_frame_ent(node) == NULL &&
964 is_ia32_use_frame(node)) {
965 if (is_ia32_need_stackent(node))
968 switch (get_ia32_irn_opcode(node)) {
970 case iro_ia32_Load: {
971 const ia32_attr_t *attr = get_ia32_attr_const(node);
973 if (attr->data.need_32bit_stackent) {
975 } else if (attr->data.need_64bit_stackent) {
978 mode = get_ia32_ls_mode(node);
979 if (is_ia32_is_reload(node))
980 mode = get_spill_mode_mode(mode);
982 align = get_mode_size_bytes(mode);
988 case iro_ia32_xLoad: {
989 mode = get_ia32_ls_mode(node);
994 case iro_ia32_FldCW: {
995 /* although 2 byte would be enough 4 byte performs best */
1003 panic("unexpected frame user while collection frame entity nodes");
1005 case iro_ia32_FnstCW:
1006 case iro_ia32_Store8Bit:
1007 case iro_ia32_Store:
1010 case iro_ia32_fisttp:
1011 case iro_ia32_xStore:
1012 case iro_ia32_xStoreSimple:
1019 be_node_needs_frame_entity(env, node, mode, align);
1022 static int determine_ebp_input(ir_node *ret)
1024 const arch_register_t *bp = &ia32_registers[REG_EBP];
1025 int arity = get_irn_arity(ret);
1028 for (i = 0; i < arity; ++i) {
1029 ir_node *input = get_irn_n(ret, i);
1030 if (arch_get_irn_register(input) == bp)
1033 panic("no ebp input found at %+F", ret);
1036 static void introduce_epilog(ir_node *ret)
1038 const arch_register_t *sp = &ia32_registers[REG_ESP];
1039 const arch_register_t *bp = &ia32_registers[REG_EBP];
1040 ir_graph *irg = get_irn_irg(ret);
1041 ir_type *frame_type = get_irg_frame_type(irg);
1042 unsigned frame_size = get_type_size_bytes(frame_type);
1043 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1044 ir_node *block = get_nodes_block(ret);
1045 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1046 ir_node *curr_sp = first_sp;
1047 ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
1049 if (!layout->sp_relative) {
1050 int n_ebp = determine_ebp_input(ret);
1051 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1052 if (ia32_cg_config.use_leave) {
1053 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1054 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1055 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1056 arch_set_irn_register(curr_bp, bp);
1057 arch_set_irn_register(curr_sp, sp);
1058 sched_add_before(ret, leave);
1061 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1062 /* copy ebp to esp */
1063 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1064 arch_set_irn_register(curr_sp, sp);
1065 sched_add_before(ret, curr_sp);
1068 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1069 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1070 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1071 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1072 arch_set_irn_register(curr_bp, bp);
1073 arch_set_irn_register(curr_sp, sp);
1074 sched_add_before(ret, pop);
1076 set_irn_n(ret, n_be_Return_mem, curr_mem);
1078 set_irn_n(ret, n_ebp, curr_bp);
1080 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1081 sched_add_before(ret, incsp);
1084 set_irn_n(ret, n_be_Return_sp, curr_sp);
1086 /* keep verifier happy... */
1087 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1088 kill_node(first_sp);
1093 * put the Prolog code at the beginning, epilog code before each return
1095 static void introduce_prolog_epilog(ir_graph *irg)
1097 const arch_register_t *sp = &ia32_registers[REG_ESP];
1098 const arch_register_t *bp = &ia32_registers[REG_EBP];
1099 ir_node *start = get_irg_start(irg);
1100 ir_node *block = get_nodes_block(start);
1101 ir_type *frame_type = get_irg_frame_type(irg);
1102 unsigned frame_size = get_type_size_bytes(frame_type);
1103 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1104 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1105 ir_node *curr_sp = initial_sp;
1106 ir_mode *mode_gp = mode_Iu;
1108 if (!layout->sp_relative) {
1110 ir_node *mem = get_irg_initial_mem(irg);
1111 ir_node *noreg = ia32_new_NoReg_gp(irg);
1112 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1113 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, initial_bp, initial_sp);
1116 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1117 arch_set_irn_register(curr_sp, sp);
1118 sched_add_after(start, push);
1120 /* move esp to ebp */
1121 ir_node *const curr_bp = be_new_Copy(block, curr_sp);
1122 sched_add_after(push, curr_bp);
1123 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1124 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1125 sched_add_after(curr_bp, curr_sp);
1126 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1127 edges_reroute_except(initial_bp, curr_bp, push);
1129 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1130 edges_reroute_except(initial_sp, incsp, push);
1131 sched_add_after(curr_sp, incsp);
1133 /* make sure the initial IncSP is really used by someone */
1134 if (get_irn_n_edges(incsp) <= 1) {
1135 ir_node *in[] = { incsp };
1136 ir_node *keep = be_new_Keep(block, 1, in);
1137 sched_add_after(incsp, keep);
1140 layout->initial_bias = -4;
1142 ir_node *const incsp = be_new_IncSP(sp, block, initial_sp, frame_size, 0);
1143 edges_reroute_except(initial_sp, incsp, incsp);
1144 sched_add_after(start, incsp);
1147 /* introduce epilog for every return node */
1149 ir_node *end_block = get_irg_end_block(irg);
1150 int arity = get_irn_arity(end_block);
1153 for (i = 0; i < arity; ++i) {
1154 ir_node *ret = get_irn_n(end_block, i);
1155 assert(be_is_Return(ret));
1156 introduce_epilog(ret);
1162 * Last touchups for the graph before emit: x87 simulation to replace the
1163 * virtual with real x87 instructions, creating a block schedule and peephole
1166 static void ia32_finish_graph(ir_graph *irg)
1168 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1169 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1170 bool at_begin = stack_layout->sp_relative ? true : false;
1171 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1173 /* create and coalesce frame entities */
1174 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1175 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1176 be_free_frame_entity_coalescer(fec_env);
1178 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1180 introduce_prolog_epilog(irg);
1182 /* fix stack entity offsets */
1183 be_abi_fix_stack_nodes(irg);
1184 be_abi_fix_stack_bias(irg);
1186 /* fix 2-address code constraints */
1187 ia32_finish_irg(irg);
1189 /* we might have to rewrite x87 virtual registers */
1190 if (irg_data->do_x87_sim) {
1191 ia32_x87_simulate_graph(irg);
1194 /* do peephole optimisations */
1195 ia32_peephole_optimization(irg);
1197 be_remove_dead_nodes_from_schedule(irg);
1199 /* create block schedule, this also removes empty blocks which might
1200 * produce critical edges */
1201 irg_data->blk_sched = be_create_block_schedule(irg);
1205 * Emits the code, closes the output file and frees
1206 * the code generator interface.
1208 static void ia32_emit(ir_graph *irg)
1210 if (ia32_cg_config.emit_machcode) {
1211 ia32_gen_binary_routine(irg);
1213 ia32_gen_routine(irg);
1218 * Returns the node representing the PIC base.
1220 static ir_node *ia32_get_pic_base(ir_graph *irg)
1222 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1224 ir_node *get_eip = irg_data->get_eip;
1225 if (get_eip != NULL)
1228 block = get_irg_start_block(irg);
1229 get_eip = new_bd_ia32_GetEIP(NULL, block);
1230 irg_data->get_eip = get_eip;
1236 * Initializes a IA32 code generator.
1238 static void ia32_init_graph(ir_graph *irg)
1240 struct obstack *obst = be_get_be_obst(irg);
1241 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1243 irg_data->dump = (be_options.dump_flags & DUMP_BE) ? 1 : 0;
1246 /* Linux gprof implementation needs base pointer */
1247 be_options.omit_fp = 0;
1250 be_birg_from_irg(irg)->isa_link = irg_data;
1253 static const tarval_mode_info mo_integer = {
1260 * set the tarval output mode of all integer modes to decimal
1262 static void set_tarval_output_modes(void)
1266 for (i = ir_get_n_modes(); i > 0;) {
1267 ir_mode *mode = ir_get_mode(--i);
1269 if (mode_is_int(mode))
1270 set_tarval_mode_output_option(mode, &mo_integer);
1274 extern const arch_isa_if_t ia32_isa_if;
1276 static void init_asm_constraints(void)
1278 be_init_default_asm_constraint_flags();
1280 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1281 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1282 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1283 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1284 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1285 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1286 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1287 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1288 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1289 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1290 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1291 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1292 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1293 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1294 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1295 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1296 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1297 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1298 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1299 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1301 /* no support for autodecrement/autoincrement */
1302 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1303 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1304 /* no float consts */
1305 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1306 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1307 /* makes no sense on x86 */
1308 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1309 /* no support for sse consts yet */
1310 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1311 /* no support for x87 consts yet */
1312 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1313 /* no support for mmx registers yet */
1314 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1315 /* not available in 32bit mode */
1316 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1317 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1319 /* no code yet to determine register class needed... */
1320 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1324 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1326 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1331 ir_relation relation;
1336 cmp_l = get_Cmp_left(sel);
1337 cmp_r = get_Cmp_right(sel);
1338 if (!mode_is_float(get_irn_mode(cmp_l)))
1341 /* check for min/max. They're defined as (C-Semantik):
1342 * min(a, b) = a < b ? a : b
1343 * or min(a, b) = a <= b ? a : b
1344 * max(a, b) = a > b ? a : b
1345 * or max(a, b) = a >= b ? a : b
1346 * (Note we only handle float min/max here)
1348 relation = get_Cmp_relation(sel);
1350 case ir_relation_greater_equal:
1351 case ir_relation_greater:
1353 if (cmp_l == mux_true && cmp_r == mux_false)
1356 case ir_relation_less_equal:
1357 case ir_relation_less:
1359 if (cmp_l == mux_true && cmp_r == mux_false)
1362 case ir_relation_unordered_greater_equal:
1363 case ir_relation_unordered_greater:
1365 if (cmp_l == mux_false && cmp_r == mux_true)
1368 case ir_relation_unordered_less_equal:
1369 case ir_relation_unordered_less:
1371 if (cmp_l == mux_false && cmp_r == mux_true)
1382 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1384 ir_mode *mode = get_irn_mode(mux_true);
1387 if (!mode_is_int(mode) && !mode_is_reference(mode)
1391 if (is_Const(mux_true) && is_Const(mux_false)) {
1392 /* we can create a set plus up two 3 instructions for any combination
1400 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1405 if (!mode_is_float(get_irn_mode(mux_true)))
1408 return is_Const(mux_true) && is_Const(mux_false);
1411 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1418 ir_relation relation;
1423 mode = get_irn_mode(mux_true);
1424 if (mode_is_signed(mode) || mode_is_float(mode))
1427 relation = get_Cmp_relation(sel);
1428 cmp_left = get_Cmp_left(sel);
1429 cmp_right = get_Cmp_right(sel);
1431 /* "move" zero constant to false input */
1432 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1433 ir_node *tmp = mux_false;
1434 mux_false = mux_true;
1436 relation = get_negated_relation(relation);
1438 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1440 if (!is_Sub(mux_true))
1442 sub_left = get_Sub_left(mux_true);
1443 sub_right = get_Sub_right(mux_true);
1445 /* Mux(a >=u b, 0, a-b) */
1446 if ((relation & ir_relation_greater)
1447 && sub_left == cmp_left && sub_right == cmp_right)
1449 /* Mux(a <=u b, 0, b-a) */
1450 if ((relation & ir_relation_less)
1451 && sub_left == cmp_right && sub_right == cmp_left)
1457 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1462 /* middleend can handle some things */
1463 if (ir_is_optimizable_mux(sel, mux_false, mux_true))
1465 /* we can handle Set for all modes and compares */
1466 if (mux_is_set(sel, mux_true, mux_false))
1468 /* SSE has own min/max operations */
1469 if (ia32_cg_config.use_sse2
1470 && mux_is_float_min_max(sel, mux_true, mux_false))
1472 /* we can handle Mux(?, Const[f], Const[f]) */
1473 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1474 #ifdef FIRM_GRGEN_BE
1475 /* well, some code selectors can't handle it */
1476 if (be_transformer != TRANSFORMER_PBQP
1477 || be_transformer != TRANSFORMER_RAND)
1484 /* no support for 64bit inputs to cmov */
1485 mode = get_irn_mode(mux_true);
1486 if (get_mode_size_bits(mode) > 32)
1488 /* we can handle Abs for all modes and compares (except 64bit) */
1489 if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
1491 /* we can't handle MuxF yet */
1492 if (mode_is_float(mode))
1495 if (mux_is_doz(sel, mux_true, mux_false))
1498 /* Check Cmp before the node */
1500 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1502 /* we can't handle 64bit compares */
1503 if (get_mode_size_bits(cmp_mode) > 32)
1506 /* we can't handle float compares */
1507 if (mode_is_float(cmp_mode))
1511 /* did we disable cmov generation? */
1512 if (!ia32_cg_config.use_cmov)
1515 /* we can use a cmov */
1520 * Create the trampoline code.
1522 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
1524 ir_graph *const irg = get_irn_irg(block);
1525 ir_node * p = trampoline;
1526 ir_mode *const mode = get_irn_mode(p);
1527 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
1528 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
1532 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
1533 mem = new_r_Proj(st, mode_M, pn_Store_M);
1534 p = new_r_Add(block, p, one, mode);
1535 st = new_r_Store(block, mem, p, env, cons_none);
1536 mem = new_r_Proj(st, mode_M, pn_Store_M);
1537 p = new_r_Add(block, p, four, mode);
1539 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
1540 mem = new_r_Proj(st, mode_M, pn_Store_M);
1541 p = new_r_Add(block, p, one, mode);
1542 st = new_r_Store(block, mem, p, callee, cons_none);
1543 mem = new_r_Proj(st, mode_M, pn_Store_M);
1548 static const ir_settings_arch_dep_t ia32_arch_dep = {
1549 1, /* also use subs */
1550 4, /* maximum shifts */
1551 63, /* maximum shift amount */
1552 ia32_evaluate_insn, /* evaluate the instruction sequence */
1554 1, /* allow Mulhs */
1555 1, /* allow Mulus */
1556 32, /* Mulh allowed up to 32 bit */
1558 static backend_params ia32_backend_params = {
1559 1, /* support inline assembly */
1560 1, /* support Rotl nodes */
1561 0, /* little endian */
1562 1, /* modulo shift efficient */
1563 0, /* non-modulo shift not efficient */
1564 &ia32_arch_dep, /* will be set later */
1565 ia32_is_mux_allowed,
1566 32, /* machine_size */
1567 NULL, /* float arithmetic mode, will be set below */
1568 NULL, /* long long type */
1569 NULL, /* unsigned long long type */
1570 NULL, /* long double type */
1571 12, /* size of trampoline code */
1572 4, /* alignment of trampoline code */
1573 ia32_create_trampoline_fkt,
1574 4 /* alignment of stack parameter */
1578 * Initializes the backend ISA.
1580 static void ia32_init(void)
1582 ir_mode *mode_long_long;
1583 ir_mode *mode_unsigned_long_long;
1584 ir_type *type_long_long;
1585 ir_type *type_unsigned_long_long;
1587 ia32_setup_cg_config();
1589 init_asm_constraints();
1591 ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
1593 /* note mantissa is 64bit but with explicitely encoded 1 so the really
1594 * usable part as counted by firm is only 63 bits */
1595 ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
1596 ia32_type_E = new_type_primitive(ia32_mode_E);
1597 set_type_size_bytes(ia32_type_E, 12);
1598 set_type_alignment_bytes(ia32_type_E, 4);
1600 mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
1601 type_long_long = new_type_primitive(mode_long_long);
1602 mode_unsigned_long_long
1603 = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
1604 type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long);
1606 ia32_backend_params.type_long_long = type_long_long;
1607 ia32_backend_params.type_unsigned_long_long = type_unsigned_long_long;
1609 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
1610 ia32_backend_params.mode_float_arithmetic = NULL;
1611 ia32_backend_params.type_long_double = NULL;
1613 ia32_backend_params.mode_float_arithmetic = ia32_mode_E;
1614 ia32_backend_params.type_long_double = ia32_type_E;
1617 ia32_register_init();
1618 obstack_init(&opcodes_obst);
1619 ia32_create_opcodes(&ia32_irn_ops);
1622 static void ia32_finish(void)
1624 if (between_type != NULL) {
1625 free_type(between_type);
1626 between_type = NULL;
1628 ia32_free_opcodes();
1629 obstack_free(&opcodes_obst, NULL);
1633 * The template that generates a new ISA object.
1634 * Note that this template can be changed by command line
1637 static ia32_isa_t ia32_isa_template = {
1639 &ia32_isa_if, /* isa interface implementation */
1644 &ia32_registers[REG_ESP], /* stack pointer register */
1645 &ia32_registers[REG_EBP], /* base pointer register */
1646 2, /* power of two stack alignment, 2^2 == 4 */
1647 NULL, /* main environment */
1648 7, /* costs for a spill instruction */
1649 5, /* costs for a reload instruction */
1650 false, /* no custom abi handling */
1653 IA32_FPU_ARCH_X87, /* FPU architecture */
1656 static arch_env_t *ia32_begin_codegeneration(const be_main_env_t *env)
1658 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1660 set_tarval_output_modes();
1662 *isa = ia32_isa_template;
1663 isa->tv_ent = pmap_create();
1665 /* enter the ISA object into the intrinsic environment */
1666 intrinsic_env.isa = isa;
1668 be_emit_init(env->file_handle);
1669 be_gas_begin_compilation_unit(env);
1675 * Closes the output file and frees the ISA structure.
1677 static void ia32_end_codegeneration(void *self)
1679 ia32_isa_t *isa = (ia32_isa_t*)self;
1681 /* emit now all global declarations */
1682 be_gas_end_compilation_unit(isa->base.main_env);
1686 pmap_destroy(isa->tv_ent);
1691 * Returns the register for parameter nr.
1693 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1694 const ir_mode *mode)
1696 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1697 &ia32_registers[REG_ECX],
1698 &ia32_registers[REG_EDX],
1701 static const unsigned MAXNUM_GPREG_ARGS = 3;
1703 static const arch_register_t *gpreg_param_reg_regparam[] = {
1704 &ia32_registers[REG_EAX],
1705 &ia32_registers[REG_EDX],
1706 &ia32_registers[REG_ECX]
1709 static const arch_register_t *gpreg_param_reg_this[] = {
1710 &ia32_registers[REG_ECX],
1715 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1716 &ia32_registers[REG_XMM0],
1717 &ia32_registers[REG_XMM1],
1718 &ia32_registers[REG_XMM2],
1719 &ia32_registers[REG_XMM3],
1720 &ia32_registers[REG_XMM4],
1721 &ia32_registers[REG_XMM5],
1722 &ia32_registers[REG_XMM6],
1723 &ia32_registers[REG_XMM7]
1726 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1727 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1729 static const unsigned MAXNUM_SSE_ARGS = 8;
1731 if ((cc & cc_this_call) && nr == 0)
1732 return gpreg_param_reg_this[0];
1734 if (! (cc & cc_reg_param))
1737 if (mode_is_float(mode)) {
1738 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1740 if (nr >= MAXNUM_SSE_ARGS)
1743 if (cc & cc_this_call) {
1744 return fpreg_sse_param_reg_this[nr];
1746 return fpreg_sse_param_reg_std[nr];
1747 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1748 unsigned num_regparam;
1750 if (get_mode_size_bits(mode) > 32)
1753 if (nr >= MAXNUM_GPREG_ARGS)
1756 if (cc & cc_this_call) {
1757 return gpreg_param_reg_this[nr];
1759 num_regparam = cc & ~cc_bits;
1760 if (num_regparam == 0) {
1761 /* default fastcall */
1762 return gpreg_param_reg_fastcall[nr];
1764 if (nr < num_regparam)
1765 return gpreg_param_reg_regparam[nr];
1769 panic("unknown argument mode");
1773 * Get the ABI restrictions for procedure calls.
1775 static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
1780 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1782 /* set abi flags for calls */
1783 /* call_flags.try_omit_fp not changed: can handle both settings */
1784 call_flags.call_has_imm = false; /* No call immediate, we handle this by ourselves */
1786 /* set parameter passing style */
1787 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1789 cc = get_method_calling_convention(method_type);
1790 if (get_method_variadicity(method_type) == variadicity_variadic) {
1791 /* pass all parameters of a variadic function on the stack */
1792 cc = cc_cdecl_set | (cc & cc_this_call);
1794 if (get_method_additional_properties(method_type) & mtp_property_private &&
1795 ia32_cg_config.optimize_cc) {
1796 /* set the fast calling conventions (allowing up to 3) */
1797 cc = SET_FASTCALL(cc) | 3;
1801 /* we have to pop the shadow parameter ourself for compound calls */
1802 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1803 && !(cc & cc_reg_param)) {
1804 pop_amount += get_mode_size_bytes(mode_P_data);
1807 n = get_method_n_params(method_type);
1808 for (i = regnum = 0; i < n; i++) {
1809 const arch_register_t *reg = NULL;
1810 ir_type *tp = get_method_param_type(method_type, i);
1811 ir_mode *mode = get_type_mode(tp);
1814 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1817 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1820 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1821 * movl has a shorter opcode than mov[sz][bw]l */
1822 ir_mode *load_mode = mode;
1825 unsigned size = get_mode_size_bytes(mode);
1827 if (cc & cc_callee_clear_stk) {
1828 pop_amount += (size + 3U) & ~3U;
1831 if (size < 4) load_mode = mode_Iu;
1834 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1838 be_abi_call_set_pop(abi, pop_amount);
1840 /* set return registers */
1841 n = get_method_n_ress(method_type);
1843 assert(n <= 2 && "more than two results not supported");
1845 /* In case of 64bit returns, we will have two 32bit values */
1847 ir_type *tp = get_method_res_type(method_type, 0);
1848 ir_mode *mode = get_type_mode(tp);
1850 assert(!mode_is_float(mode) && "two FP results not supported");
1852 tp = get_method_res_type(method_type, 1);
1853 mode = get_type_mode(tp);
1855 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1857 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1858 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1861 ir_type *tp = get_method_res_type(method_type, 0);
1862 ir_mode *mode = get_type_mode(tp);
1863 const arch_register_t *reg;
1864 assert(is_atomic_type(tp));
1866 reg = mode_is_float(mode) ? &ia32_registers[REG_ST0] : &ia32_registers[REG_EAX];
1868 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1872 static void ia32_mark_remat(ir_node *node)
1874 if (is_ia32_irn(node)) {
1875 set_ia32_is_remat(node);
1879 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
1883 /* we already added all our simple flags to the flags modifier list in
1884 * init, so this flag we don't know. */
1885 return ASM_CONSTRAINT_FLAG_INVALID;
1888 static int ia32_is_valid_clobber(const char *clobber)
1890 return ia32_get_clobber_register(clobber) != NULL;
1893 static void ia32_lower_for_target(void)
1895 ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
1896 size_t i, n_irgs = get_irp_n_irgs();
1898 /* perform doubleword lowering */
1899 lwrdw_param_t lower_dw_params = {
1900 1, /* little endian */
1901 64, /* doubleword size */
1902 ia32_create_intrinsic_fkt,
1906 /* lower compound param handling
1907 * Note: we lower compound arguments ourself, since on ia32 we don't
1908 * have hidden parameters but know where to find the structs on the stack.
1909 * (This also forces us to always allocate space for the compound arguments
1910 * on the callframe and we can't just use an arbitrary position on the
1913 lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
1915 /* replace floating point operations by function calls */
1916 if (ia32_cg_config.use_softfloat) {
1917 lower_floating_point();
1920 for (i = 0; i < n_irgs; ++i) {
1921 ir_graph *irg = get_irp_irg(i);
1922 /* break up switches with wide ranges */
1923 lower_switch(irg, 4, 256, mode_gp);
1926 ir_prepare_dw_lowering(&lower_dw_params);
1929 for (i = 0; i < n_irgs; ++i) {
1930 ir_graph *irg = get_irp_irg(i);
1931 /* lower for mode_b stuff */
1932 ir_lower_mode_b(irg, mode_Iu);
1935 for (i = 0; i < n_irgs; ++i) {
1936 ir_graph *irg = get_irp_irg(i);
1937 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
1938 * so we can generate rep movs later, and turn all big CopyBs into
1940 lower_CopyB(irg, 64, 8193, true);
1945 * Returns the libFirm configuration parameter for this backend.
1947 static const backend_params *ia32_get_libfirm_params(void)
1949 return &ia32_backend_params;
1953 * Check if the given register is callee or caller save.
1955 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
1958 /* check for callee saved */
1959 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
1960 switch (reg->index) {
1971 /* check for caller saved */
1972 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
1973 switch (reg->index) {
1981 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
1982 /* all XMM registers are caller save */
1983 return reg->index != REG_XMM_NOREG;
1984 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_fp]) {
1985 /* all FP registers are caller save */
1986 return reg->index != REG_FP_NOREG;
1992 static const lc_opt_enum_int_items_t gas_items[] = {
1993 { "elf", OBJECT_FILE_FORMAT_ELF },
1994 { "mingw", OBJECT_FILE_FORMAT_COFF },
1995 { "macho", OBJECT_FILE_FORMAT_MACH_O },
1999 static lc_opt_enum_int_var_t gas_var = {
2000 (int*) &be_gas_object_file_format, gas_items
2003 #ifdef FIRM_GRGEN_BE
2004 static const lc_opt_enum_int_items_t transformer_items[] = {
2005 { "default", TRANSFORMER_DEFAULT },
2006 { "pbqp", TRANSFORMER_PBQP },
2007 { "random", TRANSFORMER_RAND },
2011 static lc_opt_enum_int_var_t transformer_var = {
2012 (int*)&be_transformer, transformer_items
2016 static const lc_opt_table_entry_t ia32_options[] = {
2017 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2018 #ifdef FIRM_GRGEN_BE
2019 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2021 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2022 &ia32_isa_template.base.stack_alignment),
2023 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2027 const arch_isa_if_t ia32_isa_if = {
2030 ia32_get_libfirm_params,
2031 ia32_lower_for_target,
2032 ia32_parse_asm_constraint,
2033 ia32_is_valid_clobber,
2035 ia32_begin_codegeneration,
2036 ia32_end_codegeneration,
2040 ia32_get_pic_base, /* return node used as base in pic code addresses */
2043 ia32_register_saved_by,
2045 ia32_handle_intrinsics,
2046 ia32_before_abi, /* before abi introduce hook */
2048 ia32_before_ra, /* before register allocation hook */
2049 ia32_finish_graph, /* called before codegen */
2050 ia32_emit, /* emit && done */
2053 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2054 void be_init_arch_ia32(void)
2056 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2057 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2059 lc_opt_add_table(ia32_grp, ia32_options);
2060 be_register_isa_if("ia32", &ia32_isa_if);
2062 ia32_init_emitter();
2064 ia32_init_optimize();
2065 ia32_init_transform();
2067 ia32_init_architecture();