5 #include "pseudo_irg.h"
15 #include "../bearch.h" /* the general register allocator interface */
16 #include "../benode_t.h"
17 #include "bearch_ia32_t.h"
19 #include "ia32_new_nodes.h" /* ia32 nodes interface */
20 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
21 #include "ia32_gen_decls.h" /* interface declaration emitter */
22 #include "ia32_transform.h"
23 #include "ia32_emitter.h"
24 #include "ia32_map_regs.h"
26 #define DEBUG_MODULE "ir.be.isa.ia32"
29 static set *cur_reg_set = NULL;
32 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
34 /**************************************************
37 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
38 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
39 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
40 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
43 **************************************************/
45 static ir_node *my_skip_proj(const ir_node *n) {
51 static int is_Call_Proj(const ir_node *n) {
53 is_Proj(get_Proj_pred(n)) &&
54 get_irn_mode(get_Proj_pred(n)) == mode_T &&
55 is_ia32_Call(get_Proj_pred(get_Proj_pred(n))))
63 static int is_Start_Proj(const ir_node *n) {
65 is_Proj(get_Proj_pred(n)) &&
66 get_irn_mode(get_Proj_pred(n)) == mode_T &&
67 is_Start(get_Proj_pred(get_Proj_pred(n))))
75 static int is_P_frame_base_Proj(const ir_node *n) {
77 is_Start(get_Proj_pred(n)) &&
78 get_Proj_proj(n) == pn_Start_P_frame_base)
86 static int is_used_by_Keep(const ir_node *n) {
87 return be_is_Keep(get_edge_src_irn(get_irn_out_edge_first(n)));
91 * Return register requirements for an ia32 node.
92 * If the node returns a tuple (mode_T) then the proj's
93 * will be asked for this information.
95 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
96 const ia32_register_req_t *irn_req;
97 long node_pos = pos == -1 ? 0 : pos;
98 ir_mode *mode = get_irn_mode(irn);
99 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
100 const ia32_irn_ops_t *ops = self;
102 if (mode == mode_T || mode == mode_M) {
103 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
107 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
110 if (is_Call_Proj(irn) && is_used_by_Keep(irn)) {
111 irn_req = ia32_projnum_reg_req_map[get_Proj_proj(irn)];
112 memcpy(req, &(irn_req->req), sizeof(*req));
115 else if (is_Start_Proj(irn)) {
116 irn_req = ops->cg->reg_param_req[get_Proj_proj(irn)];
117 assert(irn_req && "missing requirement for regparam");
118 memcpy(req, &(irn_req->req), sizeof(*req));
121 else if (is_Proj(irn)) {
123 node_pos = ia32_translate_proj_pos(irn);
129 irn = my_skip_proj(irn);
131 DBG((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
134 if (is_ia32_irn(irn)) {
136 irn_req = get_ia32_in_req(irn, pos);
139 irn_req = get_ia32_out_req(irn, node_pos);
142 DBG((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
144 memcpy(req, &(irn_req->req), sizeof(*req));
146 if (arch_register_req_is(&(irn_req->req), should_be_same) ||
147 arch_register_req_is(&(irn_req->req), should_be_different)) {
148 assert(irn_req->pos >= 0 && "should be same/different constraint for in -> out NYI");
149 req->other = get_irn_n(irn, irn_req->pos);
153 /* treat Phi like Const with default requirements */
155 DBG((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
156 if (mode_is_float(mode))
157 memcpy(req, &(ia32_default_req_ia32_floating_point.req), sizeof(*req));
158 else if (mode_is_int(mode) || mode_is_reference(mode))
159 memcpy(req, &(ia32_default_req_ia32_general_purpose.req), sizeof(*req));
160 else if (mode == mode_T || mode == mode_M) {
161 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
165 assert(0 && "unsupported Phi-Mode");
167 else if (is_Start(irn)) {
168 DBG((mod, LEVEL_1, "returning reqs none for ProjX -> Start (%+F )\n", irn));
170 case pn_Start_X_initial_exec:
171 case pn_Start_P_value_arg_base:
172 case pn_Start_P_globals:
173 case pn_Start_P_frame_base:
174 memcpy(req, &(ia32_default_req_none.req), sizeof(*req));
176 case pn_Start_T_args:
177 assert(0 && "ProjT(pn_Start_T_args) should not be asked");
180 else if (get_irn_op(irn) == op_Return && pos > 0) {
181 DBG((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
182 memcpy(req, &(ia32_default_req_ia32_general_purpose_eax.req), sizeof(*req));
185 DBG((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
193 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
196 if ((is_Call_Proj(irn) && is_used_by_Keep(irn)) ||
197 is_P_frame_base_Proj(irn) ||
200 /* don't skip the proj, we want to take the else below */
202 else if (is_Proj(irn)) {
203 pos = ia32_translate_proj_pos(irn);
204 irn = my_skip_proj(irn);
207 if (is_ia32_irn(irn)) {
208 const arch_register_t **slots;
210 slots = get_ia32_slots(irn);
214 ia32_set_firm_reg(irn, reg, cur_reg_set);
218 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
220 const arch_register_t *reg = NULL;
222 if ((is_Call_Proj(irn) && is_used_by_Keep(irn)) ||
223 is_P_frame_base_Proj(irn) ||
226 /* don't skip the proj, we want to take the else below */
228 else if (is_Proj(irn)) {
229 pos = ia32_translate_proj_pos(irn);
230 irn = my_skip_proj(irn);
233 if (is_ia32_irn(irn)) {
234 const arch_register_t **slots;
235 slots = get_ia32_slots(irn);
239 reg = ia32_get_firm_reg(irn, cur_reg_set);
245 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
246 irn = my_skip_proj(irn);
248 return arch_irn_class_branch;
249 else if (is_ia32_Call(irn))
250 return arch_irn_class_call;
251 else if (is_ia32_irn(irn))
252 return arch_irn_class_normal;
257 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
258 irn = my_skip_proj(irn);
259 if (is_ia32_irn(irn))
260 return get_ia32_flags(irn);
262 ir_printf("don't know flags of %+F\n", irn);
267 /* fill register allocator interface */
269 static const arch_irn_ops_if_t ia32_irn_ops_if = {
270 ia32_get_irn_reg_req,
277 ia32_irn_ops_t ia32_irn_ops = {
284 /**************************************************
287 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
288 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
289 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
290 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
293 **************************************************/
295 static void check_for_alloca(ir_node *irn, void *env) {
296 int *has_alloca = env;
298 if (get_irn_opcode(irn) == iro_Alloc) {
299 if (get_Alloc_where(irn) == stack_alloc) {
306 * Transforms the standard firm graph into
309 static void ia32_prepare_graph(void *self) {
310 ia32_code_gen_t *cg = self;
312 if (! is_pseudo_ir_graph(cg->irg)) {
313 /* If there is a alloca in the irg, we use %ebp for stack addressing */
314 /* instead of %esp, as alloca destroys %esp. */
318 /* check for alloca node */
319 irg_walk_blkwise_graph(cg->irg, check_for_alloca, NULL, &(cg->has_alloca));
321 if (cg->has_alloca) {
322 ia32_general_purpose_regs[REG_EBP].type = arch_register_type_ignore;
325 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
332 * Set the register for P_frame_base Proj to %esp.
334 static void ia32_set_P_frame_base_Proj_reg(ir_node *irn, void *env) {
335 ia32_code_gen_t *cg = env;
337 if (is_P_frame_base_Proj(irn)) {
338 if (cg->has_alloca) {
339 arch_set_irn_register(cg->arch_env, irn, &ia32_general_purpose_regs[REG_EBP]);
342 arch_set_irn_register(cg->arch_env, irn, &ia32_general_purpose_regs[REG_ESP]);
350 * Dummy functions for hooks we don't need but which must be filled.
352 static void ia32_before_sched(void *self) {
355 static void ia32_before_ra(void *self) {
360 * Creates a Store for a Spill
362 static ir_node *ia32_lower_spill(void *self, ir_node *spill) {
363 ia32_code_gen_t *cg = self;
364 unsigned offs = be_get_spill_offset(spill);
365 dbg_info *dbg = get_irn_dbg_info(spill);
366 ir_node *block = get_nodes_block(spill);
367 ir_node *ptr = get_irg_frame(cg->irg);
368 ir_node *val = be_get_Spill_context(spill);
369 ir_node *mem = new_rd_NoMem(cg->irg);
370 ir_mode *mode = get_irn_mode(spill);
373 res = new_rd_ia32_Store(dbg, cg->irg, block, ptr, val, mem, mode);
374 set_ia32_am_offs(res, new_tarval_from_long(offs, mode_Iu));
380 * Create a Load for a Spill
382 static ir_node *ia32_lower_reload(void *self, ir_node *reload) {
383 ia32_code_gen_t *cg = self;
384 dbg_info *dbg = get_irn_dbg_info(reload);
385 ir_node *block = get_nodes_block(reload);
386 ir_node *ptr = get_irg_frame(cg->irg);
387 ir_mode *mode = get_irn_mode(reload);
388 ir_node *store = get_irn_n(reload, 0);
389 tarval *tv = get_ia32_am_offs(store);
392 res = new_rd_ia32_Load(dbg, cg->irg, block, ptr, store, mode);
393 set_ia32_am_offs(res, tv);
399 * Emits the code, closes the output file and frees
400 * the code generator interface.
402 static void ia32_codegen(void *self) {
403 ia32_code_gen_t *cg = self;
404 ir_graph *irg = cg->irg;
407 if (cg->emit_decls) {
408 ia32_gen_decls(cg->out);
412 /* set the stack register */
413 if (! is_pseudo_ir_graph(irg))
414 irg_walk_blkwise_graph(irg, NULL, ia32_set_P_frame_base_Proj_reg, cg);
416 // ia32_finish_irg(irg);
417 ia32_gen_routine(out, irg, cg->arch_env);
421 /* de-allocate code generator */
422 del_set(cg->reg_set);
426 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env);
428 static const arch_code_generator_if_t ia32_code_gen_if = {
431 ia32_before_sched, /* before scheduling hook */
432 ia32_before_ra, /* before register allocation hook */
435 ia32_codegen /* emit && done */
439 * Initializes the code generator.
441 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env) {
442 ia32_isa_t *isa = (ia32_isa_t *)arch_env->isa;
443 ia32_code_gen_t *cg = malloc(sizeof(*cg));
445 cg->impl = &ia32_code_gen_if;
447 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
448 cg->mod = firm_dbg_register("be.transform.ia32");
450 cg->arch_env = arch_env;
454 if (isa->num_codegens > 1)
459 cur_reg_set = cg->reg_set;
461 ia32_irn_ops.cg = cg;
463 return (arch_code_generator_t *)cg;
468 /*****************************************************************
469 * ____ _ _ _____ _____
470 * | _ \ | | | | |_ _|/ ____| /\
471 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
472 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
473 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
474 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
476 *****************************************************************/
479 * Initializes the backend ISA and opens the output file.
481 static void *ia32_init(void) {
482 static int inited = 0;
483 ia32_isa_t *isa = malloc(sizeof(*isa));
485 isa->impl = &ia32_isa_if;
492 isa->num_codegens = 0;
493 isa->reg_projnum_map = new_set(ia32_cmp_reg_projnum_assoc, 1024);
495 ia32_register_init(isa);
496 ia32_create_opcodes();
504 * Closes the output file and frees the ISA structure.
506 static void ia32_done(void *self) {
512 static int ia32_get_n_reg_class(const void *self) {
516 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
517 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
518 return &ia32_reg_classes[i];
521 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
522 return &ia32_irn_ops;
525 const arch_irn_handler_t ia32_irn_handler = {
529 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
530 return &ia32_irn_handler;
533 long ia32_get_call_projnum_for_reg(const void *self, const arch_register_t *reg) {
534 ia32_isa_t *isa = (ia32_isa_t *)self;
535 return ia32_get_reg_projnum(reg, isa->reg_projnum_map);
538 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
539 return is_ia32_irn(irn);
543 * Initializes the code generator interface.
545 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
546 return &ia32_code_gen_if;
549 list_sched_selector_t ia32_sched_selector;
552 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
554 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
555 memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
556 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
557 return &ia32_sched_selector;
561 static void ia32_register_options(lc_opt_entry_t *ent)
564 #endif /* WITH_LIBCORE */
566 const arch_isa_if_t ia32_isa_if = {
568 ia32_register_options,
572 ia32_get_n_reg_class,
574 ia32_get_irn_handler,
575 ia32_get_code_generator_if,
576 ia32_get_list_sched_selector,
577 ia32_get_call_projnum_for_reg