2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
30 #include <libcore/lc_opts.h>
31 #include <libcore/lc_opts_enum.h>
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
54 #include "../beirg_t.h"
55 #include "../benode_t.h"
56 #include "../belower.h"
57 #include "../besched_t.h"
60 #include "../beirgmod.h"
61 #include "../be_dbgout.h"
62 #include "../beblocksched.h"
63 #include "../bemachine.h"
64 #include "../beilpsched.h"
65 #include "../bespillslots.h"
66 #include "../bemodule.h"
67 #include "../begnuas.h"
68 #include "../bestate.h"
69 #include "../beflags.h"
71 #include "bearch_ia32_t.h"
73 #include "ia32_new_nodes.h"
74 #include "gen_ia32_regalloc_if.h"
75 #include "gen_ia32_machine.h"
76 #include "ia32_transform.h"
77 #include "ia32_emitter.h"
78 #include "ia32_map_regs.h"
79 #include "ia32_optimize.h"
81 #include "ia32_dbg_stat.h"
82 #include "ia32_finish.h"
83 #include "ia32_util.h"
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 static set *cur_reg_set = NULL;
91 ir_mode *mode_fpcw = NULL;
92 ia32_code_gen_t *ia32_current_cg = NULL;
95 * The environment for the intrinsic mapping.
97 static ia32_intrinsic_env_t intrinsic_env = {
99 NULL, /* the irg, these entities belong to */
100 NULL, /* entity for first div operand (move into FPU) */
101 NULL, /* entity for second div operand (move into FPU) */
102 NULL, /* entity for converts ll -> d */
103 NULL, /* entity for converts d -> ll */
104 NULL, /* entity for __divdi3 library call */
105 NULL, /* entity for __moddi3 library call */
106 NULL, /* entity for __udivdi3 library call */
107 NULL, /* entity for __umoddi3 library call */
108 NULL, /* bias value for conversion from float to unsigned 64 */
112 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
114 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
115 create_const_node_func func,
116 const arch_register_t* reg)
118 ir_node *block, *res;
123 block = get_irg_start_block(cg->irg);
124 res = func(NULL, cg->irg, block);
125 arch_set_irn_register(cg->arch_env, res, reg);
128 add_irn_dep(get_irg_end(cg->irg), res);
129 /* add_irn_dep(get_irg_start(cg->irg), res); */
134 /* Creates the unique per irg GP NoReg node. */
135 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
136 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
137 &ia32_gp_regs[REG_GP_NOREG]);
140 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
141 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
142 &ia32_vfp_regs[REG_VFP_NOREG]);
145 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
146 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
147 &ia32_xmm_regs[REG_XMM_NOREG]);
150 /* Creates the unique per irg FP NoReg node. */
151 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
152 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
155 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
156 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
157 &ia32_gp_regs[REG_GP_UKNWN]);
160 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
161 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
162 &ia32_vfp_regs[REG_VFP_UKNWN]);
165 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
166 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
167 &ia32_xmm_regs[REG_XMM_UKNWN]);
170 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
171 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
172 &ia32_fp_cw_regs[REG_FPCW]);
177 * Returns gp_noreg or fp_noreg, depending in input requirements.
179 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
180 const arch_register_req_t *req;
182 req = arch_get_register_req(cg->arch_env, irn, pos);
183 assert(req != NULL && "Missing register requirements");
184 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
185 return ia32_new_NoReg_gp(cg);
187 return ia32_new_NoReg_fp(cg);
190 /**************************************************
193 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
194 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
195 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
196 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
199 **************************************************/
202 * Return register requirements for an ia32 node.
203 * If the node returns a tuple (mode_T) then the proj's
204 * will be asked for this information.
206 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
210 long node_pos = pos == -1 ? 0 : pos;
211 ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
214 if (is_Block(node) || mode == mode_X) {
215 return arch_no_register_req;
218 if (mode == mode_T && pos < 0) {
219 return arch_no_register_req;
224 return arch_no_register_req;
227 return arch_no_register_req;
230 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
231 node = skip_Proj_const(node);
234 if (is_ia32_irn(node)) {
235 const arch_register_req_t *req;
237 req = get_ia32_in_req(node, pos);
239 req = get_ia32_out_req(node, node_pos);
246 /* unknowns should be transformed already */
247 assert(!is_Unknown(node));
249 return arch_no_register_req;
252 static void ia32_set_irn_reg(const void *self, ir_node *irn,
253 const arch_register_t *reg)
258 if (get_irn_mode(irn) == mode_X) {
263 pos = get_Proj_proj(irn);
264 irn = skip_Proj(irn);
267 if (is_ia32_irn(irn)) {
268 const arch_register_t **slots;
270 slots = get_ia32_slots(irn);
273 ia32_set_firm_reg(irn, reg, cur_reg_set);
277 static const arch_register_t *ia32_get_irn_reg(const void *self,
281 const arch_register_t *reg = NULL;
286 if (get_irn_mode(irn) == mode_X) {
290 pos = get_Proj_proj(irn);
291 irn = skip_Proj_const(irn);
294 if (is_ia32_irn(irn)) {
295 const arch_register_t **slots;
296 slots = get_ia32_slots(irn);
297 assert(pos < get_ia32_n_res(irn));
300 reg = ia32_get_firm_reg(irn, cur_reg_set);
306 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
307 arch_irn_class_t classification = arch_irn_class_normal;
310 irn = skip_Proj_const(irn);
313 classification |= arch_irn_class_branch;
315 if (! is_ia32_irn(irn))
316 return classification & ~arch_irn_class_normal;
319 classification |= arch_irn_class_load;
322 classification |= arch_irn_class_store;
324 if (is_ia32_need_stackent(irn))
325 classification |= arch_irn_class_reload;
327 return classification;
330 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
331 arch_irn_flags_t flags = arch_irn_flags_none;
335 return arch_irn_flags_ignore;
337 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
338 ir_node *pred = get_Proj_pred(irn);
340 if(is_ia32_irn(pred)) {
341 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
347 if (is_ia32_irn(irn)) {
348 flags |= get_ia32_flags(irn);
355 * The IA32 ABI callback object.
358 be_abi_call_flags_bits_t flags; /**< The call flags. */
359 const arch_isa_t *isa; /**< The ISA handle. */
360 const arch_env_t *aenv; /**< The architecture environment. */
361 ir_graph *irg; /**< The associated graph. */
364 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
366 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
369 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
371 set_ia32_frame_ent(irn, ent);
374 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
375 const ia32_irn_ops_t *ops = self;
377 if (get_ia32_frame_ent(irn)) {
378 if (is_ia32_Pop(irn)) {
379 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
381 /* Pop nodes modify the stack pointer before calculating the destination
382 * address, so fix this here
388 add_ia32_am_offs_int(irn, bias);
392 static int ia32_get_sp_bias(const void *self, const ir_node *node)
396 if (is_ia32_Push(node))
399 if (is_ia32_Pop(node))
406 * Put all registers which are saved by the prologue/epilogue in a set.
408 * @param self The callback object.
409 * @param s The result set.
411 static void ia32_abi_dont_save_regs(void *self, pset *s)
413 ia32_abi_env_t *env = self;
414 if(env->flags.try_omit_fp)
415 pset_insert_ptr(s, env->isa->bp);
419 * Generate the routine prologue.
421 * @param self The callback object.
422 * @param mem A pointer to the mem node. Update this if you define new memory.
423 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
425 * @return The register which shall be used as a stack frame base.
427 * All nodes which define registers in @p reg_map must keep @p reg_map current.
429 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
431 ia32_abi_env_t *env = self;
432 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
433 ia32_code_gen_t *cg = isa->cg;
435 if (! env->flags.try_omit_fp) {
436 ir_node *bl = get_irg_start_block(env->irg);
437 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
438 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
439 ir_node *noreg = ia32_new_NoReg_gp(cg);
442 /* ALL nodes representing bp must be set to ignore. */
443 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
446 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp, curr_bp);
447 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
448 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
450 /* the push must have SP out register */
451 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
452 set_ia32_flags(push, arch_irn_flags_ignore);
454 /* move esp to ebp */
455 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
456 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
457 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
458 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
460 /* beware: the copy must be done before any other sp use */
461 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
462 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
463 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
464 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
466 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
467 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
476 * Generate the routine epilogue.
477 * @param self The callback object.
478 * @param bl The block for the epilog
479 * @param mem A pointer to the mem node. Update this if you define new memory.
480 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
481 * @return The register which shall be used as a stack frame base.
483 * All nodes which define registers in @p reg_map must keep @p reg_map current.
485 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
487 ia32_abi_env_t *env = self;
488 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
489 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
491 if (env->flags.try_omit_fp) {
492 /* simply remove the stack frame here */
493 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
494 add_irn_dep(curr_sp, *mem);
496 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
497 ia32_code_gen_t *cg = isa->cg;
498 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
499 ir_graph *irg = current_ir_graph;
501 if (ARCH_AMD(isa->opt_arch)) {
505 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
506 set_ia32_flags(leave, arch_irn_flags_ignore);
507 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
508 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
510 ir_node *noreg = ia32_new_NoReg_gp(cg);
513 /* the old SP is not needed anymore (kill the proj) */
514 assert(is_Proj(curr_sp));
515 be_kill_node(curr_sp);
517 /* copy ebp to esp */
518 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
519 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
520 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
523 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp);
524 set_ia32_flags(pop, arch_irn_flags_ignore);
525 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
526 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
528 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
530 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
531 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
534 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
535 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
539 * Initialize the callback object.
540 * @param call The call object.
541 * @param aenv The architecture environment.
542 * @param irg The graph with the method.
543 * @return Some pointer. This pointer is passed to all other callback functions as self object.
545 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
547 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
548 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
549 env->flags = fl.bits;
552 env->isa = aenv->isa;
557 * Destroy the callback object.
558 * @param self The callback object.
560 static void ia32_abi_done(void *self) {
565 * Produces the type which sits between the stack args and the locals on the stack.
566 * it will contain the return address and space to store the old base pointer.
567 * @return The Firm type modeling the ABI between type.
569 static ir_type *ia32_abi_get_between_type(void *self)
571 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
572 static ir_type *omit_fp_between_type = NULL;
573 static ir_type *between_type = NULL;
575 ia32_abi_env_t *env = self;
577 if (! between_type) {
578 ir_entity *old_bp_ent;
579 ir_entity *ret_addr_ent;
580 ir_entity *omit_fp_ret_addr_ent;
582 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
583 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
585 between_type = new_type_struct(IDENT("ia32_between_type"));
586 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
587 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
589 set_entity_offset(old_bp_ent, 0);
590 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
591 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
592 set_type_state(between_type, layout_fixed);
594 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
595 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
597 set_entity_offset(omit_fp_ret_addr_ent, 0);
598 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
599 set_type_state(omit_fp_between_type, layout_fixed);
602 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
607 * Get the estimated cycle count for @p irn.
609 * @param self The this pointer.
610 * @param irn The node.
612 * @return The estimated cycle count for this operation
614 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
617 ia32_op_type_t op_tp;
618 const ia32_irn_ops_t *ops = self;
622 if (!is_ia32_irn(irn))
625 assert(is_ia32_irn(irn));
627 cost = get_ia32_latency(irn);
628 op_tp = get_ia32_op_type(irn);
630 if (is_ia32_CopyB(irn)) {
632 if (ARCH_INTEL(ops->cg->arch))
635 else if (is_ia32_CopyB_i(irn)) {
636 int size = get_ia32_copyb_size(irn);
637 cost = 20 + (int)ceil((4/3) * size);
638 if (ARCH_INTEL(ops->cg->arch))
641 /* in case of address mode operations add additional cycles */
642 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
644 In case of stack access and access to fixed addresses add 5 cycles
645 (we assume they are in cache), other memory operations cost 20
648 if(is_ia32_use_frame(irn) ||
649 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
650 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
661 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
663 * @param irn The original operation
664 * @param i Index of the argument we want the inverse operation to yield
665 * @param inverse struct to be filled with the resulting inverse op
666 * @param obstack The obstack to use for allocation of the returned nodes array
667 * @return The inverse operation or NULL if operation invertible
669 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
673 ir_node *block, *noreg, *nomem;
677 /* we cannot invert non-ia32 irns */
678 if (! is_ia32_irn(irn))
681 /* operand must always be a real operand (not base, index or mem) */
682 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
685 /* we don't invert address mode operations */
686 if (get_ia32_op_type(irn) != ia32_Normal)
689 /* TODO: adjust for new immediates... */
690 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
694 irg = get_irn_irg(irn);
695 block = get_nodes_block(irn);
696 mode = get_irn_mode(irn);
697 irn_mode = get_irn_mode(irn);
698 noreg = get_irn_n(irn, 0);
699 nomem = new_r_NoMem(irg);
700 dbg = get_irn_dbg_info(irn);
702 /* initialize structure */
703 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
707 switch (get_ia32_irn_opcode(irn)) {
710 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
711 /* we have an add with a const here */
712 /* invers == add with negated const */
713 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
715 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
716 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
717 set_ia32_commutative(inverse->nodes[0]);
719 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
720 /* we have an add with a symconst here */
721 /* invers == sub with const */
722 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
724 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
727 /* normal add: inverse == sub */
728 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
735 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
736 /* we have a sub with a const/symconst here */
737 /* invers == add with this const */
738 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
739 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
740 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
744 if (i == n_ia32_binary_left) {
745 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
748 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
756 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
757 /* xor with const: inverse = xor */
758 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
759 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
760 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
764 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
770 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
775 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
780 /* inverse operation not supported */
787 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
789 if(mode_is_float(mode))
796 * Get the mode that should be used for spilling value node
798 static ir_mode *get_spill_mode(const ir_node *node)
800 ir_mode *mode = get_irn_mode(node);
801 return get_spill_mode_mode(mode);
805 * Checks whether an addressmode reload for a node with mode mode is compatible
806 * with a spillslot of mode spill_mode
808 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
810 if(mode_is_float(mode)) {
811 return mode == spillmode;
818 * Check if irn can load it's operand at position i from memory (source addressmode).
819 * @param self Pointer to irn ops itself
820 * @param irn The irn to be checked
821 * @param i The operands position
822 * @return Non-Zero if operand can be loaded
824 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
825 ir_node *op = get_irn_n(irn, i);
826 const ir_mode *mode = get_irn_mode(op);
827 const ir_mode *spillmode = get_spill_mode(op);
830 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
831 get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
832 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
833 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
834 ! ia32_is_spillmode_compatible(mode, spillmode) ||
835 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
836 is_ia32_use_frame(irn)) /* must not already use frame */
839 if (i == n_ia32_binary_left) {
840 const arch_register_req_t *req;
841 if(!is_ia32_commutative(irn))
843 /* we can't swap left/right for limited registers
844 * (As this (currently) breaks constraint handling copies)
846 req = get_ia32_in_req(irn, n_ia32_binary_left);
847 if(req->type & arch_register_req_type_limited) {
855 static void ia32_perform_memory_operand(const void *self, ir_node *irn,
856 ir_node *spill, unsigned int i)
858 const ia32_irn_ops_t *ops = self;
859 ia32_code_gen_t *cg = ops->cg;
861 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
863 if (i == n_ia32_binary_left) {
864 ia32_swap_left_right(irn);
867 set_ia32_op_type(irn, ia32_AddrModeS);
868 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
869 set_ia32_use_frame(irn);
870 set_ia32_need_stackent(irn);
872 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
873 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
874 set_irn_n(irn, n_ia32_mem, spill);
876 /* immediates are only allowed on the right side */
877 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
878 ia32_swap_left_right(irn);
882 static const be_abi_callbacks_t ia32_abi_callbacks = {
885 ia32_abi_get_between_type,
886 ia32_abi_dont_save_regs,
891 /* fill register allocator interface */
893 static const arch_irn_ops_if_t ia32_irn_ops_if = {
894 ia32_get_irn_reg_req,
899 ia32_get_frame_entity,
900 ia32_set_frame_entity,
901 ia32_set_frame_offset,
904 ia32_get_op_estimated_cost,
905 ia32_possible_memory_operand,
906 ia32_perform_memory_operand,
909 ia32_irn_ops_t ia32_irn_ops = {
916 /**************************************************
919 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
920 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
921 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
922 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
925 **************************************************/
927 static void ia32_before_abi(void *self) {
928 ia32_code_gen_t *cg = self;
930 ir_lower_mode_b(cg->irg, mode_Iu, 0);
932 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
936 * Transforms the standard firm graph into
939 static void ia32_prepare_graph(void *self) {
940 ia32_code_gen_t *cg = self;
942 /* do local optimisations */
943 optimize_graph_df(cg->irg);
945 /* TODO: we often have dead code reachable through out-edges here. So for
946 * now we rebuild edges (as we need correct user count for code selection)
949 edges_deactivate(cg->irg);
950 edges_activate(cg->irg);
954 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
956 /* transform nodes into assembler instructions */
957 ia32_transform_graph(cg);
959 /* do local optimisations (mainly CSE) */
960 optimize_graph_df(cg->irg);
963 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
965 /* optimize address mode */
966 ia32_optimize_graph(cg);
969 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
971 /* do code placement, to optimize the position of constants */
975 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
979 * Dummy functions for hooks we don't need but which must be filled.
981 static void ia32_before_sched(void *self) {
985 static void turn_back_am(ir_node *node)
987 ir_graph *irg = current_ir_graph;
988 dbg_info *dbgi = get_irn_dbg_info(node);
989 ir_node *block = get_nodes_block(node);
990 ir_node *base = get_irn_n(node, n_ia32_base);
991 ir_node *index = get_irn_n(node, n_ia32_index);
992 ir_node *mem = get_irn_n(node, n_ia32_mem);
993 ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
997 const ir_edge_t *edge;
999 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1000 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1002 ia32_copy_am_attrs(load, node);
1003 set_irn_n(node, n_ia32_mem, new_NoMem());
1005 switch (get_ia32_am_arity(node)) {
1007 set_irn_n(node, n_ia32_unary_op, load_res);
1010 case ia32_am_binary:
1011 if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
1012 assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
1013 is_ia32_Test(node) || is_ia32_Test8Bit(node));
1014 set_irn_n(node, n_ia32_binary_left, load_res);
1016 set_irn_n(node, n_ia32_binary_right, load_res);
1020 case ia32_am_ternary:
1021 set_irn_n(node, n_ia32_binary_right, load_res);
1026 set_irn_n(node, n_ia32_base, noreg);
1027 set_irn_n(node, n_ia32_index, noreg);
1028 set_ia32_am_offs_int(node, 0);
1029 set_ia32_am_sc(node, NULL);
1030 set_ia32_am_scale(node, 0);
1031 clear_ia32_am_sc_sign(node);
1033 /* rewire mem-proj */
1034 if(get_irn_mode(node) == mode_T) {
1036 foreach_out_edge(node, edge) {
1037 ir_node *out = get_edge_src_irn(edge);
1038 if(get_Proj_proj(out) == pn_ia32_mem) {
1044 if(mem_proj != NULL) {
1045 set_Proj_pred(mem_proj, load);
1046 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1050 set_ia32_op_type(node, ia32_Normal);
1051 if(sched_is_scheduled(node))
1052 sched_add_before(node, load);
1055 static ir_node *flags_remat(ir_node *node, ir_node *after)
1057 /* we should turn back source address mode when rematerializing nodes */
1058 ia32_op_type_t type = get_ia32_op_type(node);
1062 if(is_Block(after)) {
1065 block = get_nodes_block(after);
1069 case ia32_AddrModeS: turn_back_am(node); break;
1071 case ia32_AddrModeD:
1072 /* TODO implement this later... */
1073 panic("found DestAM with flag user %+F this should not happen", node);
1076 default: assert(type == ia32_Normal); break;
1079 copy = exact_copy(node);
1080 set_nodes_block(copy, block);
1081 sched_add_after(after, copy);
1087 * Called before the register allocator.
1088 * Calculate a block schedule here. We need it for the x87
1089 * simulator and the emitter.
1091 static void ia32_before_ra(void *self) {
1092 ia32_code_gen_t *cg = self;
1094 /* setup fpu rounding modes */
1095 ia32_setup_fpu_mode(cg);
1098 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1101 ia32_add_missing_keeps(cg);
1106 * Transforms a be_Reload into a ia32 Load.
1108 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1109 ir_graph *irg = get_irn_irg(node);
1110 dbg_info *dbg = get_irn_dbg_info(node);
1111 ir_node *block = get_nodes_block(node);
1112 ir_entity *ent = be_get_frame_entity(node);
1113 ir_mode *mode = get_irn_mode(node);
1114 ir_mode *spillmode = get_spill_mode(node);
1115 ir_node *noreg = ia32_new_NoReg_gp(cg);
1116 ir_node *sched_point = NULL;
1117 ir_node *ptr = get_irg_frame(irg);
1118 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1119 ir_node *new_op, *proj;
1120 const arch_register_t *reg;
1122 if (sched_is_scheduled(node)) {
1123 sched_point = sched_prev(node);
1126 if (mode_is_float(spillmode)) {
1128 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1130 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1132 else if (get_mode_size_bits(spillmode) == 128) {
1133 // Reload 128 bit sse registers
1134 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1137 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1139 set_ia32_op_type(new_op, ia32_AddrModeS);
1140 set_ia32_ls_mode(new_op, spillmode);
1141 set_ia32_frame_ent(new_op, ent);
1142 set_ia32_use_frame(new_op);
1144 DBG_OPT_RELOAD2LD(node, new_op);
1146 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1149 sched_add_after(sched_point, new_op);
1153 /* copy the register from the old node to the new Load */
1154 reg = arch_get_irn_register(cg->arch_env, node);
1155 arch_set_irn_register(cg->arch_env, new_op, reg);
1157 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1159 exchange(node, proj);
1163 * Transforms a be_Spill node into a ia32 Store.
1165 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1166 ir_graph *irg = get_irn_irg(node);
1167 dbg_info *dbg = get_irn_dbg_info(node);
1168 ir_node *block = get_nodes_block(node);
1169 ir_entity *ent = be_get_frame_entity(node);
1170 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1171 ir_mode *mode = get_spill_mode(spillval);
1172 ir_node *noreg = ia32_new_NoReg_gp(cg);
1173 ir_node *nomem = new_rd_NoMem(irg);
1174 ir_node *ptr = get_irg_frame(irg);
1175 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1177 ir_node *sched_point = NULL;
1179 if (sched_is_scheduled(node)) {
1180 sched_point = sched_prev(node);
1183 /* No need to spill unknown values... */
1184 if(is_ia32_Unknown_GP(val) ||
1185 is_ia32_Unknown_VFP(val) ||
1186 is_ia32_Unknown_XMM(val)) {
1191 exchange(node, store);
1195 if (mode_is_float(mode)) {
1197 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1199 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1200 } else if (get_mode_size_bits(mode) == 128) {
1201 // Spill 128 bit SSE registers
1202 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1203 } else if (get_mode_size_bits(mode) == 8) {
1204 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1206 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1209 set_ia32_op_type(store, ia32_AddrModeD);
1210 set_ia32_ls_mode(store, mode);
1211 set_ia32_frame_ent(store, ent);
1212 set_ia32_use_frame(store);
1213 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1214 DBG_OPT_SPILL2ST(node, store);
1217 sched_add_after(sched_point, store);
1221 exchange(node, store);
1224 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1225 ir_graph *irg = get_irn_irg(node);
1226 dbg_info *dbg = get_irn_dbg_info(node);
1227 ir_node *block = get_nodes_block(node);
1228 ir_node *noreg = ia32_new_NoReg_gp(cg);
1229 ir_node *frame = get_irg_frame(irg);
1231 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, sp, noreg);
1233 set_ia32_frame_ent(push, ent);
1234 set_ia32_use_frame(push);
1235 set_ia32_op_type(push, ia32_AddrModeS);
1236 set_ia32_ls_mode(push, mode_Is);
1238 sched_add_before(schedpoint, push);
1242 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1243 ir_graph *irg = get_irn_irg(node);
1244 dbg_info *dbg = get_irn_dbg_info(node);
1245 ir_node *block = get_nodes_block(node);
1246 ir_node *noreg = ia32_new_NoReg_gp(cg);
1247 ir_node *frame = get_irg_frame(irg);
1249 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1251 set_ia32_frame_ent(pop, ent);
1252 set_ia32_use_frame(pop);
1253 set_ia32_op_type(pop, ia32_AddrModeD);
1254 set_ia32_ls_mode(pop, mode_Is);
1256 sched_add_before(schedpoint, pop);
1261 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1262 ir_graph *irg = get_irn_irg(node);
1263 dbg_info *dbg = get_irn_dbg_info(node);
1264 ir_node *block = get_nodes_block(node);
1265 ir_mode *spmode = mode_Iu;
1266 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1269 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1270 arch_set_irn_register(cg->arch_env, sp, spreg);
1276 * Transform memperm, currently we do this the ugly way and produce
1277 * push/pop into/from memory cascades. This is possible without using
1280 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1281 ir_graph *irg = get_irn_irg(node);
1282 ir_node *block = get_nodes_block(node);
1286 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1287 const ir_edge_t *edge;
1288 const ir_edge_t *next;
1291 arity = be_get_MemPerm_entity_arity(node);
1292 pops = alloca(arity * sizeof(pops[0]));
1295 for(i = 0; i < arity; ++i) {
1296 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1297 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1298 ir_type *enttype = get_entity_type(inent);
1299 int entbits = get_type_size_bits(enttype);
1300 int entbits2 = get_type_size_bits(get_entity_type(outent));
1301 ir_node *mem = get_irn_n(node, i + 1);
1304 /* work around cases where entities have different sizes */
1305 if(entbits2 < entbits)
1307 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1309 push = create_push(cg, node, node, sp, mem, inent);
1310 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1312 // add another push after the first one
1313 push = create_push(cg, node, node, sp, mem, inent);
1314 add_ia32_am_offs_int(push, 4);
1315 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1318 set_irn_n(node, i, new_Bad());
1322 for(i = arity - 1; i >= 0; --i) {
1323 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1324 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1325 ir_type *enttype = get_entity_type(outent);
1326 int entbits = get_type_size_bits(enttype);
1327 int entbits2 = get_type_size_bits(get_entity_type(inent));
1330 /* work around cases where entities have different sizes */
1331 if(entbits2 < entbits)
1333 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1335 pop = create_pop(cg, node, node, sp, outent);
1336 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1338 add_ia32_am_offs_int(pop, 4);
1340 // add another pop after the first one
1341 pop = create_pop(cg, node, node, sp, outent);
1342 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1349 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1350 sched_add_before(node, keep);
1352 // exchange memprojs
1353 foreach_out_edge_safe(node, edge, next) {
1354 ir_node *proj = get_edge_src_irn(edge);
1355 int p = get_Proj_proj(proj);
1359 set_Proj_pred(proj, pops[p]);
1360 set_Proj_proj(proj, pn_ia32_Pop_M);
1364 arity = get_irn_arity(node);
1365 for(i = 0; i < arity; ++i) {
1366 set_irn_n(node, i, new_Bad());
1372 * Block-Walker: Calls the transform functions Spill and Reload.
1374 static void ia32_after_ra_walker(ir_node *block, void *env) {
1375 ir_node *node, *prev;
1376 ia32_code_gen_t *cg = env;
1378 /* beware: the schedule is changed here */
1379 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1380 prev = sched_prev(node);
1382 if (be_is_Reload(node)) {
1383 transform_to_Load(cg, node);
1384 } else if (be_is_Spill(node)) {
1385 transform_to_Store(cg, node);
1386 } else if(be_is_MemPerm(node)) {
1387 transform_MemPerm(cg, node);
1393 * Collects nodes that need frame entities assigned.
1395 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1397 be_fec_env_t *env = data;
1399 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1400 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1401 int align = get_mode_size_bytes(mode);
1402 be_node_needs_frame_entity(env, node, mode, align);
1403 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1404 && is_ia32_use_frame(node)) {
1405 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1406 const ir_mode *mode = get_ia32_ls_mode(node);
1407 const ia32_attr_t *attr = get_ia32_attr_const(node);
1408 int align = get_mode_size_bytes(mode);
1410 if(attr->data.need_64bit_stackent) {
1413 if(attr->data.need_32bit_stackent) {
1416 be_node_needs_frame_entity(env, node, mode, align);
1417 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1418 || is_ia32_vfld(node)) {
1419 const ir_mode *mode = get_ia32_ls_mode(node);
1421 be_node_needs_frame_entity(env, node, mode, align);
1422 } else if(is_ia32_FldCW(node)) {
1423 const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
1425 be_node_needs_frame_entity(env, node, mode, align);
1428 assert(is_ia32_St(node) ||
1429 is_ia32_xStoreSimple(node) ||
1430 is_ia32_vfst(node) ||
1431 is_ia32_vfist(node) ||
1432 is_ia32_FnstCW(node));
1439 * We transform Spill and Reload here. This needs to be done before
1440 * stack biasing otherwise we would miss the corrected offset for these nodes.
1442 static void ia32_after_ra(void *self) {
1443 ia32_code_gen_t *cg = self;
1444 ir_graph *irg = cg->irg;
1445 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1447 /* create and coalesce frame entities */
1448 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1449 be_assign_entities(fec_env);
1450 be_free_frame_entity_coalescer(fec_env);
1452 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1456 * Last touchups for the graph before emit: x87 simulation to replace the
1457 * virtual with real x87 instructions, creating a block schedule and peephole
1460 static void ia32_finish(void *self) {
1461 ia32_code_gen_t *cg = self;
1462 ir_graph *irg = cg->irg;
1464 ia32_finish_irg(irg, cg);
1466 /* we might have to rewrite x87 virtual registers */
1467 if (cg->do_x87_sim) {
1468 x87_simulate_graph(cg->arch_env, cg->birg);
1471 /* do peephole optimisations */
1472 ia32_peephole_optimization(cg);
1474 /* create block schedule, this also removes empty blocks which might
1475 * produce critical edges */
1476 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1480 * Emits the code, closes the output file and frees
1481 * the code generator interface.
1483 static void ia32_codegen(void *self) {
1484 ia32_code_gen_t *cg = self;
1485 ir_graph *irg = cg->irg;
1487 ia32_gen_routine(cg, irg);
1491 /* remove it from the isa */
1494 assert(ia32_current_cg == cg);
1495 ia32_current_cg = NULL;
1497 /* de-allocate code generator */
1498 del_set(cg->reg_set);
1502 static void *ia32_cg_init(be_irg_t *birg);
1504 static const arch_code_generator_if_t ia32_code_gen_if = {
1506 ia32_before_abi, /* before abi introduce hook */
1509 ia32_before_sched, /* before scheduling hook */
1510 ia32_before_ra, /* before register allocation hook */
1511 ia32_after_ra, /* after register allocation hook */
1512 ia32_finish, /* called before codegen */
1513 ia32_codegen /* emit && done */
1517 * Initializes a IA32 code generator.
1519 static void *ia32_cg_init(be_irg_t *birg) {
1520 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1521 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1523 cg->impl = &ia32_code_gen_if;
1524 cg->irg = birg->irg;
1525 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1526 cg->arch_env = birg->main_env->arch_env;
1529 cg->blk_sched = NULL;
1530 cg->fp_kind = isa->fp_kind;
1531 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1533 /* copy optimizations from isa for easier access */
1535 cg->arch = isa->arch;
1536 cg->opt_arch = isa->opt_arch;
1542 if (isa->name_obst) {
1543 obstack_free(isa->name_obst, NULL);
1544 obstack_init(isa->name_obst);
1548 cur_reg_set = cg->reg_set;
1550 ia32_irn_ops.cg = cg;
1552 assert(ia32_current_cg == NULL);
1553 ia32_current_cg = cg;
1555 return (arch_code_generator_t *)cg;
1560 /*****************************************************************
1561 * ____ _ _ _____ _____
1562 * | _ \ | | | | |_ _|/ ____| /\
1563 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1564 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1565 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1566 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1568 *****************************************************************/
1571 * Set output modes for GCC
1573 static const tarval_mode_info mo_integer = {
1580 * set the tarval output mode of all integer modes to decimal
1582 static void set_tarval_output_modes(void)
1586 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1587 ir_mode *mode = get_irp_mode(i);
1589 if (mode_is_int(mode))
1590 set_tarval_mode_output_option(mode, &mo_integer);
1594 const arch_isa_if_t ia32_isa_if;
1597 * The template that generates a new ISA object.
1598 * Note that this template can be changed by command line
1601 static ia32_isa_t ia32_isa_template = {
1603 &ia32_isa_if, /* isa interface implementation */
1604 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1605 &ia32_gp_regs[REG_EBP], /* base pointer register */
1606 -1, /* stack direction */
1607 NULL, /* main environment */
1608 7, /* costs for a spill instruction */
1609 5, /* costs for a reload instruction */
1611 NULL, /* 16bit register names */
1612 NULL, /* 8bit register names */
1613 NULL, /* 8bit register names high */
1617 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1619 arch_pentium_4, /* instruction architecture */
1620 arch_pentium_4, /* optimize for architecture */
1621 fp_x87, /* floating point mode */
1622 NULL, /* current code generator */
1624 NULL, /* name obstack */
1625 0 /* name obst size */
1629 static void set_arch_costs(enum cpu_support arch);
1632 * Initializes the backend ISA.
1634 static void *ia32_init(FILE *file_handle) {
1635 static int inited = 0;
1642 set_tarval_output_modes();
1644 isa = xmalloc(sizeof(*isa));
1645 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1647 if(mode_fpcw == NULL) {
1648 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1651 ia32_register_init();
1652 ia32_create_opcodes();
1654 set_arch_costs(isa->opt_arch);
1656 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1657 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1658 /* no SSE2 for these cpu's */
1659 isa->fp_kind = fp_x87;
1661 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1662 /* Pentium 4 don't like inc and dec instructions */
1663 isa->opt &= ~IA32_OPT_INCDEC;
1666 be_emit_init(file_handle);
1667 isa->regs_16bit = pmap_create();
1668 isa->regs_8bit = pmap_create();
1669 isa->regs_8bit_high = pmap_create();
1670 isa->types = pmap_create();
1671 isa->tv_ent = pmap_create();
1672 isa->cpu = ia32_init_machine_description();
1674 ia32_build_16bit_reg_map(isa->regs_16bit);
1675 ia32_build_8bit_reg_map(isa->regs_8bit);
1676 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1679 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1680 obstack_init(isa->name_obst);
1683 /* enter the ISA object into the intrinsic environment */
1684 intrinsic_env.isa = isa;
1685 ia32_handle_intrinsics();
1687 /* needed for the debug support */
1688 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1689 be_emit_cstring(".Ltext0:\n");
1690 be_emit_write_line();
1692 /* we mark referenced global entities, so we can only emit those which
1693 * are actually referenced. (Note: you mustn't use the type visited flag
1694 * elsewhere in the backend)
1696 inc_master_type_visited();
1704 * Closes the output file and frees the ISA structure.
1706 static void ia32_done(void *self) {
1707 ia32_isa_t *isa = self;
1709 /* emit now all global declarations */
1710 be_gas_emit_decls(isa->arch_isa.main_env, 1);
1712 pmap_destroy(isa->regs_16bit);
1713 pmap_destroy(isa->regs_8bit);
1714 pmap_destroy(isa->regs_8bit_high);
1715 pmap_destroy(isa->tv_ent);
1716 pmap_destroy(isa->types);
1719 obstack_free(isa->name_obst, NULL);
1729 * Return the number of register classes for this architecture.
1730 * We report always these:
1731 * - the general purpose registers
1732 * - the SSE floating point register set
1733 * - the virtual floating point registers
1734 * - the SSE vector register set
1736 static unsigned ia32_get_n_reg_class(const void *self) {
1742 * Return the register class for index i.
1744 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1748 assert(i < N_CLASSES);
1749 return &ia32_reg_classes[i];
1753 * Get the register class which shall be used to store a value of a given mode.
1754 * @param self The this pointer.
1755 * @param mode The mode in question.
1756 * @return A register class which can hold values of the given mode.
1758 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1759 const ia32_isa_t *isa = self;
1760 if (mode_is_float(mode)) {
1761 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1764 return &ia32_reg_classes[CLASS_ia32_gp];
1768 * Get the ABI restrictions for procedure calls.
1769 * @param self The this pointer.
1770 * @param method_type The type of the method (procedure) in question.
1771 * @param abi The abi object to be modified
1773 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1774 const ia32_isa_t *isa = self;
1779 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1781 /* set abi flags for calls */
1782 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1783 call_flags.bits.store_args_sequential = 0;
1784 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1785 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1786 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1788 /* set parameter passing style */
1789 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1791 if (get_method_variadicity(method_type) == variadicity_variadic) {
1792 /* pass all parameters of a variadic function on the stack */
1795 cc = get_method_calling_convention(method_type);
1796 if (get_method_additional_properties(method_type) & mtp_property_private
1797 && (ia32_isa_template.opt & IA32_OPT_CC)) {
1798 /* set the calling conventions to register parameter */
1799 cc = (cc & ~cc_bits) | cc_reg_param;
1803 /* we have to pop the shadow parameter ourself for compound calls */
1804 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1805 && !(cc & cc_reg_param)) {
1806 be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
1809 n = get_method_n_params(method_type);
1810 for (i = regnum = 0; i < n; i++) {
1812 const arch_register_t *reg = NULL;
1814 tp = get_method_param_type(method_type, i);
1815 mode = get_type_mode(tp);
1817 reg = ia32_get_RegParam_reg(isa->cg, cc, regnum, mode);
1820 be_abi_call_param_reg(abi, i, reg);
1823 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1824 * movl has a shorter opcode than mov[sz][bw]l */
1825 ir_mode *load_mode = mode;
1826 if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
1827 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1831 /* set return registers */
1832 n = get_method_n_ress(method_type);
1834 assert(n <= 2 && "more than two results not supported");
1836 /* In case of 64bit returns, we will have two 32bit values */
1838 tp = get_method_res_type(method_type, 0);
1839 mode = get_type_mode(tp);
1841 assert(!mode_is_float(mode) && "two FP results not supported");
1843 tp = get_method_res_type(method_type, 1);
1844 mode = get_type_mode(tp);
1846 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1848 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1849 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1852 const arch_register_t *reg;
1854 tp = get_method_res_type(method_type, 0);
1855 assert(is_atomic_type(tp));
1856 mode = get_type_mode(tp);
1858 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1860 be_abi_call_res_reg(abi, 0, reg);
1865 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
1870 return &ia32_irn_ops;
1873 const arch_irn_handler_t ia32_irn_handler = {
1877 const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
1880 return &ia32_irn_handler;
1883 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1887 if(!is_ia32_irn(irn)) {
1891 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1892 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1893 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1894 || is_ia32_Immediate(irn))
1901 * Initializes the code generator interface.
1903 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1906 return &ia32_code_gen_if;
1910 * Returns the estimated execution time of an ia32 irn.
1912 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1913 const arch_env_t *arch_env = env;
1914 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1917 list_sched_selector_t ia32_sched_selector;
1920 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1922 static const list_sched_selector_t *ia32_get_list_sched_selector(
1923 const void *self, list_sched_selector_t *selector)
1926 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1927 ia32_sched_selector.exectime = ia32_sched_exectime;
1928 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1929 return &ia32_sched_selector;
1932 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1939 * Returns the necessary byte alignment for storing a register of given class.
1941 static int ia32_get_reg_class_alignment(const void *self,
1942 const arch_register_class_t *cls)
1944 ir_mode *mode = arch_register_class_mode(cls);
1945 int bytes = get_mode_size_bytes(mode);
1948 if (mode_is_float(mode) && bytes > 8)
1953 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1954 const void *self, const ir_node *irn)
1956 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1957 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1958 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1961 static const be_execution_unit_t *_allowed_units_GP[] = {
1962 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1963 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1964 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1965 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1966 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1967 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1968 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1971 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1972 &be_machine_execution_units_DUMMY[0],
1975 static const be_execution_unit_t **_units_callret[] = {
1976 _allowed_units_BRANCH,
1979 static const be_execution_unit_t **_units_other[] = {
1983 static const be_execution_unit_t **_units_dummy[] = {
1984 _allowed_units_DUMMY,
1987 const be_execution_unit_t ***ret;
1990 if (is_ia32_irn(irn)) {
1991 ret = get_ia32_exec_units(irn);
1993 else if (is_be_node(irn)) {
1994 if (be_is_Call(irn) || be_is_Return(irn)) {
1995 ret = _units_callret;
1997 else if (be_is_Barrier(irn)) {
2012 * Return the abstract ia32 machine.
2014 static const be_machine_t *ia32_get_machine(const void *self) {
2015 const ia32_isa_t *isa = self;
2020 * Return irp irgs in the desired order.
2022 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2030 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2031 * @return 1 if allowed, 0 otherwise
2033 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2041 /* we can't handle psis with 64bit compares yet */
2043 ir_node *pred = get_Proj_pred(sel);
2045 ir_node *left = get_Cmp_left(pred);
2046 ir_mode *cmp_mode = get_irn_mode(left);
2047 if(!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2052 /* check the Phi nodes */
2053 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2054 ir_mode *mode = get_irn_mode(phi);
2056 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2063 typedef struct insn_const {
2064 int add_cost; /**< cost of an add instruction */
2065 int lea_cost; /**< cost of a lea instruction */
2066 int const_shf_cost; /**< cost of a constant shift instruction */
2067 int cost_mul_start; /**< starting cost of a multiply instruction */
2068 int cost_mul_bit; /**< cost of multiply for every set bit */
2071 /* costs for the i386 */
2072 static const insn_const i386_cost = {
2073 1, /* cost of an add instruction */
2074 1, /* cost of a lea instruction */
2075 2, /* cost of a constant shift instruction */
2076 6, /* starting cost of a multiply instruction */
2077 1 /* cost of multiply for every set bit */
2080 /* costs for the i486 */
2081 static const insn_const i486_cost = {
2082 1, /* cost of an add instruction */
2083 1, /* cost of a lea instruction */
2084 2, /* cost of a constant shift instruction */
2085 12, /* starting cost of a multiply instruction */
2086 1 /* cost of multiply for every set bit */
2089 /* costs for the Pentium */
2090 static const insn_const pentium_cost = {
2091 1, /* cost of an add instruction */
2092 1, /* cost of a lea instruction */
2093 1, /* cost of a constant shift instruction */
2094 11, /* starting cost of a multiply instruction */
2095 0 /* cost of multiply for every set bit */
2098 /* costs for the Pentium Pro */
2099 static const insn_const pentiumpro_cost = {
2100 1, /* cost of an add instruction */
2101 1, /* cost of a lea instruction */
2102 1, /* cost of a constant shift instruction */
2103 4, /* starting cost of a multiply instruction */
2104 0 /* cost of multiply for every set bit */
2107 /* costs for the K6 */
2108 static const insn_const k6_cost = {
2109 1, /* cost of an add instruction */
2110 2, /* cost of a lea instruction */
2111 1, /* cost of a constant shift instruction */
2112 3, /* starting cost of a multiply instruction */
2113 0 /* cost of multiply for every set bit */
2116 /* costs for the Athlon */
2117 static const insn_const athlon_cost = {
2118 1, /* cost of an add instruction */
2119 2, /* cost of a lea instruction */
2120 1, /* cost of a constant shift instruction */
2121 5, /* starting cost of a multiply instruction */
2122 0 /* cost of multiply for every set bit */
2125 /* costs for the Pentium 4 */
2126 static const insn_const pentium4_cost = {
2127 1, /* cost of an add instruction */
2128 3, /* cost of a lea instruction */
2129 4, /* cost of a constant shift instruction */
2130 15, /* starting cost of a multiply instruction */
2131 0 /* cost of multiply for every set bit */
2134 /* costs for the Core */
2135 static const insn_const core_cost = {
2136 1, /* cost of an add instruction */
2137 1, /* cost of a lea instruction */
2138 1, /* cost of a constant shift instruction */
2139 10, /* starting cost of a multiply instruction */
2140 0 /* cost of multiply for every set bit */
2143 /* costs for the generic */
2144 static const insn_const generic_cost = {
2145 1, /* cost of an add instruction */
2146 2, /* cost of a lea instruction */
2147 1, /* cost of a constant shift instruction */
2148 4, /* starting cost of a multiply instruction */
2149 0 /* cost of multiply for every set bit */
2152 static const insn_const *arch_costs = &generic_cost;
2154 static void set_arch_costs(enum cpu_support arch) {
2157 arch_costs = &i386_cost;
2160 arch_costs = &i486_cost;
2163 case arch_pentium_mmx:
2164 arch_costs = &pentium_cost;
2166 case arch_pentium_pro:
2167 case arch_pentium_2:
2168 case arch_pentium_3:
2169 arch_costs = &pentiumpro_cost;
2171 case arch_pentium_4:
2172 arch_costs = &pentium4_cost;
2174 case arch_pentium_m:
2175 arch_costs = &pentiumpro_cost;
2178 arch_costs = &core_cost;
2181 arch_costs = &k6_cost;
2184 case arch_athlon_xp:
2185 case arch_athlon_64:
2187 arch_costs = &athlon_cost;
2191 arch_costs = &generic_cost;
2196 * Evaluate a given simple instruction.
2198 static int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
2203 cost = arch_costs->cost_mul_start;
2204 if (arch_costs->cost_mul_bit > 0) {
2205 char *bitstr = get_tarval_bitpattern(tv);
2208 for (i = 0; bitstr[i] != '\0'; ++i) {
2209 if (bitstr[i] == '1') {
2210 cost += arch_costs->cost_mul_bit;
2217 return arch_costs->lea_cost;
2220 return arch_costs->add_cost;
2222 return arch_costs->const_shf_cost;
2224 return arch_costs->add_cost;
2231 * Returns the libFirm configuration parameter for this backend.
2233 static const backend_params *ia32_get_libfirm_params(void) {
2234 static const ir_settings_if_conv_t ifconv = {
2235 4, /* maxdepth, doesn't matter for Psi-conversion */
2236 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2238 static const ir_settings_arch_dep_t ad = {
2239 1, /* also use subs */
2240 4, /* maximum shifts */
2241 31, /* maximum shift amount */
2242 ia32_evaluate_insn, /* evaluate the instruction sequence */
2244 1, /* allow Mulhs */
2245 1, /* allow Mulus */
2246 32 /* Mulh allowed up to 32 bit */
2248 static backend_params p = {
2249 1, /* need dword lowering */
2250 1, /* support inline assembly */
2251 NULL, /* no additional opcodes */
2252 NULL, /* will be set later */
2253 ia32_create_intrinsic_fkt,
2254 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2255 NULL, /* will be set below */
2259 p.if_conv_info = &ifconv;
2263 /* instruction set architectures. */
2264 static const lc_opt_enum_int_items_t arch_items[] = {
2265 { "386", arch_i386, },
2266 { "486", arch_i486, },
2267 { "pentium", arch_pentium, },
2268 { "586", arch_pentium, },
2269 { "pentiumpro", arch_pentium_pro, },
2270 { "686", arch_pentium_pro, },
2271 { "pentiummmx", arch_pentium_mmx, },
2272 { "pentium2", arch_pentium_2, },
2273 { "p2", arch_pentium_2, },
2274 { "pentium3", arch_pentium_3, },
2275 { "p3", arch_pentium_3, },
2276 { "pentium4", arch_pentium_4, },
2277 { "p4", arch_pentium_4, },
2278 { "pentiumm", arch_pentium_m, },
2279 { "pm", arch_pentium_m, },
2280 { "core", arch_core, },
2282 { "athlon", arch_athlon, },
2283 { "athlon-xp", arch_athlon_xp, },
2284 { "athlon64", arch_athlon_64, },
2285 { "opteron", arch_opteron, },
2286 { "generic", arch_generic, },
2290 static lc_opt_enum_int_var_t arch_var = {
2291 &ia32_isa_template.arch, arch_items
2294 static lc_opt_enum_int_var_t opt_arch_var = {
2295 &ia32_isa_template.opt_arch, arch_items
2298 static const lc_opt_enum_int_items_t fp_unit_items[] = {
2300 { "sse2", fp_sse2 },
2304 static lc_opt_enum_int_var_t fp_unit_var = {
2305 &ia32_isa_template.fp_kind, fp_unit_items
2308 static const lc_opt_enum_int_items_t gas_items[] = {
2309 { "normal", GAS_FLAVOUR_NORMAL },
2310 { "mingw", GAS_FLAVOUR_MINGW },
2314 static lc_opt_enum_int_var_t gas_var = {
2315 (int*) &be_gas_flavour, gas_items
2318 static const lc_opt_table_entry_t ia32_options[] = {
2319 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
2320 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
2321 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
2322 LC_OPT_ENT_NEGBIT("nooptcc", "do not optimize calling convention", &ia32_isa_template.opt, IA32_OPT_CC),
2323 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2327 const arch_isa_if_t ia32_isa_if = {
2330 ia32_get_n_reg_class,
2332 ia32_get_reg_class_for_mode,
2334 ia32_get_irn_handler,
2335 ia32_get_code_generator_if,
2336 ia32_get_list_sched_selector,
2337 ia32_get_ilp_sched_selector,
2338 ia32_get_reg_class_alignment,
2339 ia32_get_libfirm_params,
2340 ia32_get_allowed_execution_units,
2345 void ia32_init_emitter(void);
2346 void ia32_init_finish(void);
2347 void ia32_init_optimize(void);
2348 void ia32_init_transform(void);
2349 void ia32_init_x87(void);
2351 void be_init_arch_ia32(void)
2353 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2354 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2356 lc_opt_add_table(ia32_grp, ia32_options);
2357 be_register_isa_if("ia32", &ia32_isa_if);
2359 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2361 ia32_init_emitter();
2363 ia32_init_optimize();
2364 ia32_init_transform();
2368 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);