2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
38 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
55 #include "../beirg_t.h"
56 #include "../benode_t.h"
57 #include "../belower.h"
58 #include "../besched_t.h"
61 #include "../beirgmod.h"
62 #include "../be_dbgout.h"
63 #include "../beblocksched.h"
64 #include "../bemachine.h"
65 #include "../beilpsched.h"
66 #include "../bespillslots.h"
67 #include "../bemodule.h"
68 #include "../begnuas.h"
69 #include "../bestate.h"
70 #include "../beflags.h"
71 #include "../betranshlp.h"
73 #include "bearch_ia32_t.h"
75 #include "ia32_new_nodes.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "gen_ia32_machine.h"
78 #include "ia32_common_transform.h"
79 #include "ia32_transform.h"
80 #include "ia32_emitter.h"
81 #include "ia32_map_regs.h"
82 #include "ia32_optimize.h"
84 #include "ia32_dbg_stat.h"
85 #include "ia32_finish.h"
86 #include "ia32_util.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
94 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
97 static set *cur_reg_set = NULL;
99 ir_mode *mode_fpcw = NULL;
100 ia32_code_gen_t *ia32_current_cg = NULL;
103 * The environment for the intrinsic mapping.
105 static ia32_intrinsic_env_t intrinsic_env = {
107 NULL, /* the irg, these entities belong to */
108 NULL, /* entity for first div operand (move into FPU) */
109 NULL, /* entity for second div operand (move into FPU) */
110 NULL, /* entity for converts ll -> d */
111 NULL, /* entity for converts d -> ll */
112 NULL, /* entity for __divdi3 library call */
113 NULL, /* entity for __moddi3 library call */
114 NULL, /* entity for __udivdi3 library call */
115 NULL, /* entity for __umoddi3 library call */
116 NULL, /* bias value for conversion from float to unsigned 64 */
120 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
122 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
123 create_const_node_func func,
124 const arch_register_t* reg)
126 ir_node *block, *res;
131 block = get_irg_start_block(cg->irg);
132 res = func(NULL, cg->irg, block);
133 arch_set_irn_register(res, reg);
136 add_irn_dep(get_irg_end(cg->irg), res);
137 /* add_irn_dep(get_irg_start(cg->irg), res); */
142 /* Creates the unique per irg GP NoReg node. */
143 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
144 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
145 &ia32_gp_regs[REG_GP_NOREG]);
148 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
149 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
150 &ia32_vfp_regs[REG_VFP_NOREG]);
153 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
154 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
155 &ia32_xmm_regs[REG_XMM_NOREG]);
158 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
159 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
160 &ia32_gp_regs[REG_GP_UKNWN]);
163 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
164 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
165 &ia32_vfp_regs[REG_VFP_UKNWN]);
168 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
169 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
170 &ia32_xmm_regs[REG_XMM_UKNWN]);
173 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
174 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
175 &ia32_fp_cw_regs[REG_FPCW]);
180 * Returns the admissible noreg register node for input register pos of node irn.
182 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
184 const arch_register_req_t *req = arch_get_register_req(irn, pos);
186 assert(req != NULL && "Missing register requirements");
187 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
188 return ia32_new_NoReg_gp(cg);
190 if (ia32_cg_config.use_sse2) {
191 return ia32_new_NoReg_xmm(cg);
193 return ia32_new_NoReg_vfp(cg);
197 /**************************************************
200 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
201 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
202 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
203 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
206 **************************************************/
209 * Return register requirements for an ia32 node.
210 * If the node returns a tuple (mode_T) then the proj's
211 * will be asked for this information.
213 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
216 ir_mode *mode = get_irn_mode(node);
219 if (mode == mode_X || is_Block(node)) {
220 return arch_no_register_req;
223 if (mode == mode_T && pos < 0) {
224 return arch_no_register_req;
227 node_pos = pos == -1 ? 0 : pos;
229 if (mode == mode_M || pos >= 0) {
230 return arch_no_register_req;
233 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
234 node = skip_Proj_const(node);
237 if (is_ia32_irn(node)) {
238 const arch_register_req_t *req;
240 req = get_ia32_in_req(node, pos);
242 req = get_ia32_out_req(node, node_pos);
249 /* unknowns should be transformed already */
250 assert(!is_Unknown(node));
251 return arch_no_register_req;
254 static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
258 if (get_irn_mode(irn) == mode_X) {
263 pos = get_Proj_proj(irn);
264 irn = skip_Proj(irn);
267 if (is_ia32_irn(irn)) {
268 const arch_register_t **slots;
270 slots = get_ia32_slots(irn);
273 ia32_set_firm_reg(irn, reg, cur_reg_set);
277 static const arch_register_t *ia32_get_irn_reg(const ir_node *irn)
282 if (get_irn_mode(irn) == mode_X) {
286 pos = get_Proj_proj(irn);
287 irn = skip_Proj_const(irn);
290 if (is_ia32_irn(irn)) {
291 const arch_register_t **slots = get_ia32_slots(irn);
292 assert(pos < get_ia32_n_res(irn));
295 return ia32_get_firm_reg(irn, cur_reg_set);
299 static arch_irn_class_t ia32_classify(const ir_node *irn) {
300 arch_irn_class_t classification = 0;
302 irn = skip_Proj_const(irn);
305 classification |= arch_irn_class_branch;
307 if (! is_ia32_irn(irn))
308 return classification;
310 if (is_ia32_is_reload(irn))
311 classification |= arch_irn_class_reload;
313 if (is_ia32_is_spill(irn))
314 classification |= arch_irn_class_spill;
316 if (is_ia32_is_remat(irn))
317 classification |= arch_irn_class_remat;
319 return classification;
322 static arch_irn_flags_t ia32_get_flags(const ir_node *irn) {
323 arch_irn_flags_t flags = arch_irn_flags_none;
326 return arch_irn_flags_ignore;
328 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
329 ir_node *pred = get_Proj_pred(irn);
331 if(is_ia32_irn(pred)) {
332 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
338 if (is_ia32_irn(irn)) {
339 flags |= get_ia32_flags(irn);
346 * The IA32 ABI callback object.
349 be_abi_call_flags_bits_t flags; /**< The call flags. */
350 const arch_env_t *aenv; /**< The architecture environment. */
351 ir_graph *irg; /**< The associated graph. */
354 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
355 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
358 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
359 set_ia32_frame_ent(irn, ent);
362 static void ia32_set_frame_offset(ir_node *irn, int bias)
364 if (get_ia32_frame_ent(irn) == NULL)
367 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
368 ia32_code_gen_t *cg = ia32_current_cg;
369 int omit_fp = be_abi_omit_fp(cg->birg->abi);
371 /* Pop nodes modify the stack pointer before calculating the
372 * destination address, so fix this here
377 add_ia32_am_offs_int(irn, bias);
380 static int ia32_get_sp_bias(const ir_node *node)
382 if (is_ia32_Call(node))
383 return -(int)get_ia32_call_attr_const(node)->pop;
385 if (is_ia32_Push(node))
388 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
395 * Put all registers which are saved by the prologue/epilogue in a set.
397 * @param self The callback object.
398 * @param s The result set.
400 static void ia32_abi_dont_save_regs(void *self, pset *s)
402 ia32_abi_env_t *env = self;
403 if(env->flags.try_omit_fp)
404 pset_insert_ptr(s, env->aenv->bp);
408 * Generate the routine prologue.
410 * @param self The callback object.
411 * @param mem A pointer to the mem node. Update this if you define new memory.
412 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
413 * @param stack_bias Points to the current stack bias, can be modified if needed.
415 * @return The register which shall be used as a stack frame base.
417 * All nodes which define registers in @p reg_map must keep @p reg_map current.
419 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
421 ia32_abi_env_t *env = self;
422 ia32_code_gen_t *cg = ia32_current_cg;
423 const arch_env_t *arch_env = env->aenv;
425 if (! env->flags.try_omit_fp) {
426 ir_graph *irg =env->irg;
427 ir_node *bl = get_irg_start_block(irg);
428 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
429 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
430 ir_node *noreg = ia32_new_NoReg_gp(cg);
433 /* ALL nodes representing bp must be set to ignore. */
434 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
437 push = new_rd_ia32_Push(NULL, irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
438 curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
439 *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
441 /* the push must have SP out register */
442 arch_set_irn_register(curr_sp, arch_env->sp);
443 set_ia32_flags(push, arch_irn_flags_ignore);
445 /* this modifies the stack bias, because we pushed 32bit */
448 /* move esp to ebp */
449 curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
450 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
451 arch_set_irn_register(curr_bp, arch_env->bp);
452 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
454 /* beware: the copy must be done before any other sp use */
455 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
456 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp);
457 arch_set_irn_register(curr_sp, arch_env->sp);
458 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
460 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
461 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
470 * Generate the routine epilogue.
471 * @param self The callback object.
472 * @param bl The block for the epilog
473 * @param mem A pointer to the mem node. Update this if you define new memory.
474 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
475 * @return The register which shall be used as a stack frame base.
477 * All nodes which define registers in @p reg_map must keep @p reg_map current.
479 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
481 ia32_abi_env_t *env = self;
482 const arch_env_t *arch_env = env->aenv;
483 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
484 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
485 ir_graph *irg = env->irg;
487 if (env->flags.try_omit_fp) {
488 /* simply remove the stack frame here */
489 curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
491 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
493 if (ia32_cg_config.use_leave) {
497 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_bp);
498 set_ia32_flags(leave, arch_irn_flags_ignore);
499 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
500 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
504 /* the old SP is not needed anymore (kill the proj) */
505 assert(is_Proj(curr_sp));
508 /* copy ebp to esp */
509 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
510 arch_set_irn_register(curr_sp, arch_env->sp);
511 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
514 pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
515 set_ia32_flags(pop, arch_irn_flags_ignore);
516 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
517 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
519 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
521 arch_set_irn_register(curr_sp, arch_env->sp);
522 arch_set_irn_register(curr_bp, arch_env->bp);
525 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
526 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
530 * Initialize the callback object.
531 * @param call The call object.
532 * @param aenv The architecture environment.
533 * @param irg The graph with the method.
534 * @return Some pointer. This pointer is passed to all other callback functions as self object.
536 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
538 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
539 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
540 env->flags = fl.bits;
547 * Destroy the callback object.
548 * @param self The callback object.
550 static void ia32_abi_done(void *self) {
555 * Produces the type which sits between the stack args and the locals on the stack.
556 * it will contain the return address and space to store the old base pointer.
557 * @return The Firm type modeling the ABI between type.
559 static ir_type *ia32_abi_get_between_type(void *self)
561 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
562 static ir_type *omit_fp_between_type = NULL;
563 static ir_type *between_type = NULL;
565 ia32_abi_env_t *env = self;
567 if (! between_type) {
568 ir_entity *old_bp_ent;
569 ir_entity *ret_addr_ent;
570 ir_entity *omit_fp_ret_addr_ent;
572 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
573 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
575 between_type = new_type_struct(IDENT("ia32_between_type"));
576 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
577 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
579 set_entity_offset(old_bp_ent, 0);
580 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
581 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
582 set_type_state(between_type, layout_fixed);
584 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
585 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
587 set_entity_offset(omit_fp_ret_addr_ent, 0);
588 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
589 set_type_state(omit_fp_between_type, layout_fixed);
592 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
597 * Get the estimated cycle count for @p irn.
599 * @param self The this pointer.
600 * @param irn The node.
602 * @return The estimated cycle count for this operation
604 static int ia32_get_op_estimated_cost(const ir_node *irn)
607 ia32_op_type_t op_tp;
611 if (!is_ia32_irn(irn))
614 assert(is_ia32_irn(irn));
616 cost = get_ia32_latency(irn);
617 op_tp = get_ia32_op_type(irn);
619 if (is_ia32_CopyB(irn)) {
622 else if (is_ia32_CopyB_i(irn)) {
623 int size = get_ia32_copyb_size(irn);
624 cost = 20 + (int)ceil((4/3) * size);
626 /* in case of address mode operations add additional cycles */
627 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
629 In case of stack access and access to fixed addresses add 5 cycles
630 (we assume they are in cache), other memory operations cost 20
633 if (is_ia32_use_frame(irn) || (
634 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
635 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
647 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
649 * @param irn The original operation
650 * @param i Index of the argument we want the inverse operation to yield
651 * @param inverse struct to be filled with the resulting inverse op
652 * @param obstack The obstack to use for allocation of the returned nodes array
653 * @return The inverse operation or NULL if operation invertible
655 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
659 ir_node *block, *noreg, *nomem;
662 /* we cannot invert non-ia32 irns */
663 if (! is_ia32_irn(irn))
666 /* operand must always be a real operand (not base, index or mem) */
667 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
670 /* we don't invert address mode operations */
671 if (get_ia32_op_type(irn) != ia32_Normal)
674 /* TODO: adjust for new immediates... */
675 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
679 irg = get_irn_irg(irn);
680 block = get_nodes_block(irn);
681 mode = get_irn_mode(irn);
682 irn_mode = get_irn_mode(irn);
683 noreg = get_irn_n(irn, 0);
684 nomem = new_r_NoMem(irg);
685 dbg = get_irn_dbg_info(irn);
687 /* initialize structure */
688 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
692 switch (get_ia32_irn_opcode(irn)) {
695 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
696 /* we have an add with a const here */
697 /* invers == add with negated const */
698 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
700 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
701 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
702 set_ia32_commutative(inverse->nodes[0]);
704 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
705 /* we have an add with a symconst here */
706 /* invers == sub with const */
707 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
709 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
712 /* normal add: inverse == sub */
713 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
720 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
721 /* we have a sub with a const/symconst here */
722 /* invers == add with this const */
723 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
724 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
725 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
729 if (i == n_ia32_binary_left) {
730 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
733 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
741 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
742 /* xor with const: inverse = xor */
743 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
744 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
745 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
749 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
755 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
760 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
765 /* inverse operation not supported */
772 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
774 if(mode_is_float(mode))
781 * Get the mode that should be used for spilling value node
783 static ir_mode *get_spill_mode(const ir_node *node)
785 ir_mode *mode = get_irn_mode(node);
786 return get_spill_mode_mode(mode);
790 * Checks whether an addressmode reload for a node with mode mode is compatible
791 * with a spillslot of mode spill_mode
793 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
795 return !mode_is_float(mode) || mode == spillmode;
799 * Check if irn can load its operand at position i from memory (source addressmode).
800 * @param irn The irn to be checked
801 * @param i The operands position
802 * @return Non-Zero if operand can be loaded
804 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
806 ir_node *op = get_irn_n(irn, i);
807 const ir_mode *mode = get_irn_mode(op);
808 const ir_mode *spillmode = get_spill_mode(op);
810 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
811 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
812 !ia32_is_spillmode_compatible(mode, spillmode) ||
813 is_ia32_use_frame(irn)) /* must not already use frame */
816 switch (get_ia32_am_support(irn)) {
821 if (i != n_ia32_unary_op)
827 case n_ia32_binary_left: {
828 const arch_register_req_t *req;
829 if (!is_ia32_commutative(irn))
832 /* we can't swap left/right for limited registers
833 * (As this (currently) breaks constraint handling copies)
835 req = get_ia32_in_req(irn, n_ia32_binary_left);
836 if (req->type & arch_register_req_type_limited)
841 case n_ia32_binary_right:
850 panic("Unknown AM type");
853 /* HACK: must not already use "real" memory.
854 * This can happen for Call and Div */
855 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
861 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
865 ir_mode *dest_op_mode;
867 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
869 set_ia32_op_type(irn, ia32_AddrModeS);
871 load_mode = get_irn_mode(get_irn_n(irn, i));
872 dest_op_mode = get_ia32_ls_mode(irn);
873 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
874 set_ia32_ls_mode(irn, load_mode);
876 set_ia32_use_frame(irn);
877 set_ia32_need_stackent(irn);
879 if (i == n_ia32_binary_left &&
880 get_ia32_am_support(irn) == ia32_am_binary &&
881 /* immediates are only allowed on the right side */
882 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
883 ia32_swap_left_right(irn);
884 i = n_ia32_binary_right;
887 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
889 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
890 set_irn_n(irn, n_ia32_mem, spill);
891 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
892 set_ia32_is_reload(irn);
895 static const be_abi_callbacks_t ia32_abi_callbacks = {
898 ia32_abi_get_between_type,
899 ia32_abi_dont_save_regs,
904 /* fill register allocator interface */
906 static const arch_irn_ops_t ia32_irn_ops = {
907 ia32_get_irn_reg_req,
912 ia32_get_frame_entity,
913 ia32_set_frame_entity,
914 ia32_set_frame_offset,
917 ia32_get_op_estimated_cost,
918 ia32_possible_memory_operand,
919 ia32_perform_memory_operand,
922 /**************************************************
925 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
926 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
927 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
928 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
931 **************************************************/
933 static ir_entity *mcount = NULL;
935 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
937 static void ia32_before_abi(void *self) {
938 lower_mode_b_config_t lower_mode_b_config = {
939 mode_Iu, /* lowered mode */
940 mode_Bu, /* preferred mode for set */
941 0, /* don't lower direct compares */
943 ia32_code_gen_t *cg = self;
945 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
947 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
949 if (mcount == NULL) {
950 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
951 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
952 /* FIXME: enter the right ld_ident here */
953 set_entity_ld_ident(mcount, get_entity_ident(mcount));
954 set_entity_visibility(mcount, visibility_external_allocated);
956 instrument_initcall(cg->irg, mcount);
960 transformer_t be_transformer = TRANSFORMER_DEFAULT;
963 * Transforms the standard firm graph into
966 static void ia32_prepare_graph(void *self) {
967 ia32_code_gen_t *cg = self;
969 /* do local optimizations */
970 optimize_graph_df(cg->irg);
972 /* TODO: we often have dead code reachable through out-edges here. So for
973 * now we rebuild edges (as we need correct user count for code selection)
976 edges_deactivate(cg->irg);
977 edges_activate(cg->irg);
981 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
983 switch (be_transformer) {
984 case TRANSFORMER_DEFAULT:
985 /* transform remaining nodes into assembler instructions */
986 ia32_transform_graph(cg);
990 case TRANSFORMER_PBQP:
991 case TRANSFORMER_RAND:
992 /* transform nodes into assembler instructions by PBQP magic */
993 ia32_transform_graph_by_pbqp(cg);
997 default: panic("invalid transformer");
1000 /* do local optimizations (mainly CSE) */
1001 optimize_graph_df(cg->irg);
1004 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
1006 /* optimize address mode */
1007 ia32_optimize_graph(cg);
1010 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
1012 /* do code placement, to optimize the position of constants */
1013 place_code(cg->irg);
1016 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
1020 * Dummy functions for hooks we don't need but which must be filled.
1022 static void ia32_before_sched(void *self) {
1026 ir_node *turn_back_am(ir_node *node)
1028 ir_graph *irg = current_ir_graph;
1029 dbg_info *dbgi = get_irn_dbg_info(node);
1030 ir_node *block = get_nodes_block(node);
1031 ir_node *base = get_irn_n(node, n_ia32_base);
1032 ir_node *index = get_irn_n(node, n_ia32_index);
1033 ir_node *mem = get_irn_n(node, n_ia32_mem);
1036 ir_node *load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1037 ir_node *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1039 ia32_copy_am_attrs(load, node);
1040 if (is_ia32_is_reload(node))
1041 set_ia32_is_reload(load);
1042 set_irn_n(node, n_ia32_mem, new_NoMem());
1044 switch (get_ia32_am_support(node)) {
1046 set_irn_n(node, n_ia32_unary_op, load_res);
1049 case ia32_am_binary:
1050 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
1051 set_irn_n(node, n_ia32_binary_left, load_res);
1053 set_irn_n(node, n_ia32_binary_right, load_res);
1058 panic("Unknown AM type");
1060 noreg = ia32_new_NoReg_gp(ia32_current_cg);
1061 set_irn_n(node, n_ia32_base, noreg);
1062 set_irn_n(node, n_ia32_index, noreg);
1063 set_ia32_am_offs_int(node, 0);
1064 set_ia32_am_sc(node, NULL);
1065 set_ia32_am_scale(node, 0);
1066 clear_ia32_am_sc_sign(node);
1068 /* rewire mem-proj */
1069 if (get_irn_mode(node) == mode_T) {
1070 const ir_edge_t *edge;
1071 foreach_out_edge(node, edge) {
1072 ir_node *out = get_edge_src_irn(edge);
1073 if (get_irn_mode(out) == mode_M) {
1074 set_Proj_pred(out, load);
1075 set_Proj_proj(out, pn_ia32_Load_M);
1081 set_ia32_op_type(node, ia32_Normal);
1082 if (sched_is_scheduled(node))
1083 sched_add_before(node, load);
1088 static ir_node *flags_remat(ir_node *node, ir_node *after)
1090 /* we should turn back source address mode when rematerializing nodes */
1091 ia32_op_type_t type;
1095 if (is_Block(after)) {
1098 block = get_nodes_block(after);
1101 type = get_ia32_op_type(node);
1103 case ia32_AddrModeS:
1107 case ia32_AddrModeD:
1108 /* TODO implement this later... */
1109 panic("found DestAM with flag user %+F this should not happen", node);
1112 default: assert(type == ia32_Normal); break;
1115 copy = exact_copy(node);
1116 set_nodes_block(copy, block);
1117 sched_add_after(after, copy);
1123 * Called before the register allocator.
1125 static void ia32_before_ra(void *self) {
1126 ia32_code_gen_t *cg = self;
1128 /* setup fpu rounding modes */
1129 ia32_setup_fpu_mode(cg);
1132 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1135 ia32_add_missing_keeps(cg);
1140 * Transforms a be_Reload into a ia32 Load.
1142 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1143 ir_graph *irg = get_irn_irg(node);
1144 dbg_info *dbg = get_irn_dbg_info(node);
1145 ir_node *block = get_nodes_block(node);
1146 ir_entity *ent = be_get_frame_entity(node);
1147 ir_mode *mode = get_irn_mode(node);
1148 ir_mode *spillmode = get_spill_mode(node);
1149 ir_node *noreg = ia32_new_NoReg_gp(cg);
1150 ir_node *sched_point = NULL;
1151 ir_node *ptr = get_irg_frame(irg);
1152 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1153 ir_node *new_op, *proj;
1154 const arch_register_t *reg;
1156 if (sched_is_scheduled(node)) {
1157 sched_point = sched_prev(node);
1160 if (mode_is_float(spillmode)) {
1161 if (ia32_cg_config.use_sse2)
1162 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1164 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1166 else if (get_mode_size_bits(spillmode) == 128) {
1167 /* Reload 128 bit SSE registers */
1168 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1171 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1173 set_ia32_op_type(new_op, ia32_AddrModeS);
1174 set_ia32_ls_mode(new_op, spillmode);
1175 set_ia32_frame_ent(new_op, ent);
1176 set_ia32_use_frame(new_op);
1177 set_ia32_is_reload(new_op);
1179 DBG_OPT_RELOAD2LD(node, new_op);
1181 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1184 sched_add_after(sched_point, new_op);
1188 /* copy the register from the old node to the new Load */
1189 reg = arch_get_irn_register(node);
1190 arch_set_irn_register(new_op, reg);
1192 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1194 exchange(node, proj);
1198 * Transforms a be_Spill node into a ia32 Store.
1200 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1201 ir_graph *irg = get_irn_irg(node);
1202 dbg_info *dbg = get_irn_dbg_info(node);
1203 ir_node *block = get_nodes_block(node);
1204 ir_entity *ent = be_get_frame_entity(node);
1205 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1206 ir_mode *mode = get_spill_mode(spillval);
1207 ir_node *noreg = ia32_new_NoReg_gp(cg);
1208 ir_node *nomem = new_rd_NoMem(irg);
1209 ir_node *ptr = get_irg_frame(irg);
1210 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1212 ir_node *sched_point = NULL;
1214 if (sched_is_scheduled(node)) {
1215 sched_point = sched_prev(node);
1218 /* No need to spill unknown values... */
1219 if(is_ia32_Unknown_GP(val) ||
1220 is_ia32_Unknown_VFP(val) ||
1221 is_ia32_Unknown_XMM(val)) {
1226 exchange(node, store);
1230 if (mode_is_float(mode)) {
1231 if (ia32_cg_config.use_sse2)
1232 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1234 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1235 } else if (get_mode_size_bits(mode) == 128) {
1236 /* Spill 128 bit SSE registers */
1237 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1238 } else if (get_mode_size_bits(mode) == 8) {
1239 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1241 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1244 set_ia32_op_type(store, ia32_AddrModeD);
1245 set_ia32_ls_mode(store, mode);
1246 set_ia32_frame_ent(store, ent);
1247 set_ia32_use_frame(store);
1248 set_ia32_is_spill(store);
1249 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1250 DBG_OPT_SPILL2ST(node, store);
1253 sched_add_after(sched_point, store);
1257 exchange(node, store);
1260 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1261 ir_graph *irg = get_irn_irg(node);
1262 dbg_info *dbg = get_irn_dbg_info(node);
1263 ir_node *block = get_nodes_block(node);
1264 ir_node *noreg = ia32_new_NoReg_gp(cg);
1265 ir_node *frame = get_irg_frame(irg);
1267 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
1269 set_ia32_frame_ent(push, ent);
1270 set_ia32_use_frame(push);
1271 set_ia32_op_type(push, ia32_AddrModeS);
1272 set_ia32_ls_mode(push, mode_Is);
1273 set_ia32_is_spill(push);
1275 sched_add_before(schedpoint, push);
1279 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1280 ir_graph *irg = get_irn_irg(node);
1281 dbg_info *dbg = get_irn_dbg_info(node);
1282 ir_node *block = get_nodes_block(node);
1283 ir_node *noreg = ia32_new_NoReg_gp(cg);
1284 ir_node *frame = get_irg_frame(irg);
1286 ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1288 set_ia32_frame_ent(pop, ent);
1289 set_ia32_use_frame(pop);
1290 set_ia32_op_type(pop, ia32_AddrModeD);
1291 set_ia32_ls_mode(pop, mode_Is);
1292 set_ia32_is_reload(pop);
1294 sched_add_before(schedpoint, pop);
1299 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1301 ir_graph *irg = get_irn_irg(node);
1302 dbg_info *dbg = get_irn_dbg_info(node);
1303 ir_node *block = get_nodes_block(node);
1304 ir_mode *spmode = mode_Iu;
1305 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1308 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1309 arch_set_irn_register(sp, spreg);
1315 * Transform MemPerm, currently we do this the ugly way and produce
1316 * push/pop into/from memory cascades. This is possible without using
1319 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1320 ir_graph *irg = get_irn_irg(node);
1321 ir_node *block = get_nodes_block(node);
1325 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1326 const ir_edge_t *edge;
1327 const ir_edge_t *next;
1330 arity = be_get_MemPerm_entity_arity(node);
1331 pops = alloca(arity * sizeof(pops[0]));
1334 for(i = 0; i < arity; ++i) {
1335 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1336 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1337 ir_type *enttype = get_entity_type(inent);
1338 unsigned entsize = get_type_size_bytes(enttype);
1339 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1340 ir_node *mem = get_irn_n(node, i + 1);
1343 /* work around cases where entities have different sizes */
1344 if(entsize2 < entsize)
1346 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1348 push = create_push(cg, node, node, sp, mem, inent);
1349 sp = create_spproj(node, push, pn_ia32_Push_stack);
1351 /* add another push after the first one */
1352 push = create_push(cg, node, node, sp, mem, inent);
1353 add_ia32_am_offs_int(push, 4);
1354 sp = create_spproj(node, push, pn_ia32_Push_stack);
1357 set_irn_n(node, i, new_Bad());
1361 for(i = arity - 1; i >= 0; --i) {
1362 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1363 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1364 ir_type *enttype = get_entity_type(outent);
1365 unsigned entsize = get_type_size_bytes(enttype);
1366 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1369 /* work around cases where entities have different sizes */
1370 if(entsize2 < entsize)
1372 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1374 pop = create_pop(cg, node, node, sp, outent);
1375 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1377 add_ia32_am_offs_int(pop, 4);
1379 /* add another pop after the first one */
1380 pop = create_pop(cg, node, node, sp, outent);
1381 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1388 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1389 sched_add_before(node, keep);
1391 /* exchange memprojs */
1392 foreach_out_edge_safe(node, edge, next) {
1393 ir_node *proj = get_edge_src_irn(edge);
1394 int p = get_Proj_proj(proj);
1398 set_Proj_pred(proj, pops[p]);
1399 set_Proj_proj(proj, pn_ia32_Pop_M);
1402 /* remove memperm */
1403 arity = get_irn_arity(node);
1404 for(i = 0; i < arity; ++i) {
1405 set_irn_n(node, i, new_Bad());
1411 * Block-Walker: Calls the transform functions Spill and Reload.
1413 static void ia32_after_ra_walker(ir_node *block, void *env) {
1414 ir_node *node, *prev;
1415 ia32_code_gen_t *cg = env;
1417 /* beware: the schedule is changed here */
1418 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1419 prev = sched_prev(node);
1421 if (be_is_Reload(node)) {
1422 transform_to_Load(cg, node);
1423 } else if (be_is_Spill(node)) {
1424 transform_to_Store(cg, node);
1425 } else if (be_is_MemPerm(node)) {
1426 transform_MemPerm(cg, node);
1432 * Collects nodes that need frame entities assigned.
1434 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1436 be_fec_env_t *env = data;
1437 const ir_mode *mode;
1440 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1441 mode = get_spill_mode_mode(get_irn_mode(node));
1442 align = get_mode_size_bytes(mode);
1443 } else if (is_ia32_irn(node) &&
1444 get_ia32_frame_ent(node) == NULL &&
1445 is_ia32_use_frame(node)) {
1446 if (is_ia32_need_stackent(node))
1449 switch (get_ia32_irn_opcode(node)) {
1451 case iro_ia32_Load: {
1452 const ia32_attr_t *attr = get_ia32_attr_const(node);
1454 if (attr->data.need_32bit_stackent) {
1456 } else if (attr->data.need_64bit_stackent) {
1458 } else if (is_ia32_is_reload(node)) {
1459 mode = get_spill_mode_mode(mode);
1461 mode = get_ia32_ls_mode(node);
1463 align = get_mode_size_bytes(mode);
1467 case iro_ia32_vfild:
1469 case iro_ia32_xLoad: {
1470 mode = get_ia32_ls_mode(node);
1475 case iro_ia32_FldCW: {
1476 /* although 2 byte would be enough 4 byte performs best */
1484 panic("unexpected frame user while collection frame entity nodes");
1486 case iro_ia32_FnstCW:
1487 case iro_ia32_Store8Bit:
1488 case iro_ia32_Store:
1491 case iro_ia32_vfist:
1492 case iro_ia32_vfisttp:
1494 case iro_ia32_xStore:
1495 case iro_ia32_xStoreSimple:
1502 be_node_needs_frame_entity(env, node, mode, align);
1506 * We transform Spill and Reload here. This needs to be done before
1507 * stack biasing otherwise we would miss the corrected offset for these nodes.
1509 static void ia32_after_ra(void *self) {
1510 ia32_code_gen_t *cg = self;
1511 ir_graph *irg = cg->irg;
1512 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1514 /* create and coalesce frame entities */
1515 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1516 be_assign_entities(fec_env);
1517 be_free_frame_entity_coalescer(fec_env);
1519 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1523 * Last touchups for the graph before emit: x87 simulation to replace the
1524 * virtual with real x87 instructions, creating a block schedule and peephole
1527 static void ia32_finish(void *self) {
1528 ia32_code_gen_t *cg = self;
1529 ir_graph *irg = cg->irg;
1531 ia32_finish_irg(irg, cg);
1533 /* we might have to rewrite x87 virtual registers */
1534 if (cg->do_x87_sim) {
1535 x87_simulate_graph(cg->birg);
1538 /* do peephole optimisations */
1539 ia32_peephole_optimization(cg);
1541 /* create block schedule, this also removes empty blocks which might
1542 * produce critical edges */
1543 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1547 * Emits the code, closes the output file and frees
1548 * the code generator interface.
1550 static void ia32_codegen(void *self) {
1551 ia32_code_gen_t *cg = self;
1552 ir_graph *irg = cg->irg;
1554 ia32_gen_routine(cg, irg);
1558 /* remove it from the isa */
1561 assert(ia32_current_cg == cg);
1562 ia32_current_cg = NULL;
1564 /* de-allocate code generator */
1565 del_set(cg->reg_set);
1570 * Returns the node representing the PIC base.
1572 static ir_node *ia32_get_pic_base(void *self) {
1574 ia32_code_gen_t *cg = self;
1575 ir_node *get_eip = cg->get_eip;
1576 if (get_eip != NULL)
1579 block = get_irg_start_block(cg->irg);
1580 get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
1581 cg->get_eip = get_eip;
1583 be_dep_on_frame(get_eip);
1587 static void *ia32_cg_init(be_irg_t *birg);
1589 static const arch_code_generator_if_t ia32_code_gen_if = {
1591 ia32_get_pic_base, /* return node used as base in pic code addresses */
1592 ia32_before_abi, /* before abi introduce hook */
1595 ia32_before_sched, /* before scheduling hook */
1596 ia32_before_ra, /* before register allocation hook */
1597 ia32_after_ra, /* after register allocation hook */
1598 ia32_finish, /* called before codegen */
1599 ia32_codegen /* emit && done */
1603 * Initializes a IA32 code generator.
1605 static void *ia32_cg_init(be_irg_t *birg) {
1606 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1607 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1609 cg->impl = &ia32_code_gen_if;
1610 cg->irg = birg->irg;
1611 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1614 cg->blk_sched = NULL;
1615 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1616 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1619 /* Linux gprof implementation needs base pointer */
1620 birg->main_env->options->omit_fp = 0;
1627 if (isa->name_obst) {
1628 obstack_free(isa->name_obst, NULL);
1629 obstack_init(isa->name_obst);
1633 cur_reg_set = cg->reg_set;
1635 assert(ia32_current_cg == NULL);
1636 ia32_current_cg = cg;
1638 return (arch_code_generator_t *)cg;
1643 /*****************************************************************
1644 * ____ _ _ _____ _____
1645 * | _ \ | | | | |_ _|/ ____| /\
1646 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1647 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1648 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1649 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1651 *****************************************************************/
1654 * Set output modes for GCC
1656 static const tarval_mode_info mo_integer = {
1663 * set the tarval output mode of all integer modes to decimal
1665 static void set_tarval_output_modes(void)
1669 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1670 ir_mode *mode = get_irp_mode(i);
1672 if (mode_is_int(mode))
1673 set_tarval_mode_output_option(mode, &mo_integer);
1677 const arch_isa_if_t ia32_isa_if;
1680 * The template that generates a new ISA object.
1681 * Note that this template can be changed by command line
1684 static ia32_isa_t ia32_isa_template = {
1686 &ia32_isa_if, /* isa interface implementation */
1687 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1688 &ia32_gp_regs[REG_EBP], /* base pointer register */
1689 -1, /* stack direction */
1690 2, /* power of two stack alignment, 2^2 == 4 */
1691 NULL, /* main environment */
1692 7, /* costs for a spill instruction */
1693 5, /* costs for a reload instruction */
1695 NULL, /* 16bit register names */
1696 NULL, /* 8bit register names */
1697 NULL, /* 8bit register names high */
1700 NULL, /* current code generator */
1701 NULL, /* abstract machine */
1703 NULL, /* name obstack */
1707 static void init_asm_constraints(void)
1709 be_init_default_asm_constraint_flags();
1711 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1712 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1713 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1714 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1715 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1716 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1717 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1718 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1719 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1720 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1721 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1722 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1723 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1724 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1725 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1726 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1727 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1728 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1729 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1730 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1732 /* no support for autodecrement/autoincrement */
1733 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1734 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1735 /* no float consts */
1736 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1737 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1738 /* makes no sense on x86 */
1739 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1740 /* no support for sse consts yet */
1741 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1742 /* no support for x87 consts yet */
1743 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1744 /* no support for mmx registers yet */
1745 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1746 /* not available in 32bit mode */
1747 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1748 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1750 /* no code yet to determine register class needed... */
1751 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1755 * Initializes the backend ISA.
1757 static arch_env_t *ia32_init(FILE *file_handle) {
1758 static int inited = 0;
1766 set_tarval_output_modes();
1768 isa = XMALLOC(ia32_isa_t);
1769 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1771 if(mode_fpcw == NULL) {
1772 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1775 ia32_register_init();
1776 ia32_create_opcodes(&ia32_irn_ops);
1778 be_emit_init(file_handle);
1779 isa->regs_16bit = pmap_create();
1780 isa->regs_8bit = pmap_create();
1781 isa->regs_8bit_high = pmap_create();
1782 isa->types = pmap_create();
1783 isa->tv_ent = pmap_create();
1784 isa->cpu = ia32_init_machine_description();
1786 ia32_build_16bit_reg_map(isa->regs_16bit);
1787 ia32_build_8bit_reg_map(isa->regs_8bit);
1788 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1791 isa->name_obst = XMALLOC(struct obstack);
1792 obstack_init(isa->name_obst);
1795 /* enter the ISA object into the intrinsic environment */
1796 intrinsic_env.isa = isa;
1797 ia32_handle_intrinsics();
1799 /* emit asm includes */
1800 n = get_irp_n_asms();
1801 for (i = 0; i < n; ++i) {
1802 be_emit_cstring("#APP\n");
1803 be_emit_ident(get_irp_asm(i));
1804 be_emit_cstring("\n#NO_APP\n");
1807 /* needed for the debug support */
1808 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1809 be_emit_cstring(".Ltext0:\n");
1810 be_emit_write_line();
1812 /* we mark referenced global entities, so we can only emit those which
1813 * are actually referenced. (Note: you mustn't use the type visited flag
1814 * elsewhere in the backend)
1816 inc_master_type_visited();
1818 return &isa->arch_env;
1824 * Closes the output file and frees the ISA structure.
1826 static void ia32_done(void *self) {
1827 ia32_isa_t *isa = self;
1829 /* emit now all global declarations */
1830 be_gas_emit_decls(isa->arch_env.main_env, 1);
1832 pmap_destroy(isa->regs_16bit);
1833 pmap_destroy(isa->regs_8bit);
1834 pmap_destroy(isa->regs_8bit_high);
1835 pmap_destroy(isa->tv_ent);
1836 pmap_destroy(isa->types);
1839 obstack_free(isa->name_obst, NULL);
1849 * Return the number of register classes for this architecture.
1850 * We report always these:
1851 * - the general purpose registers
1852 * - the SSE floating point register set
1853 * - the virtual floating point registers
1854 * - the SSE vector register set
1856 static unsigned ia32_get_n_reg_class(const void *self) {
1862 * Return the register class for index i.
1864 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1868 assert(i < N_CLASSES);
1869 return &ia32_reg_classes[i];
1873 * Get the register class which shall be used to store a value of a given mode.
1874 * @param self The this pointer.
1875 * @param mode The mode in question.
1876 * @return A register class which can hold values of the given mode.
1878 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1879 const ir_mode *mode)
1883 if (mode_is_float(mode)) {
1884 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1887 return &ia32_reg_classes[CLASS_ia32_gp];
1891 * Get the ABI restrictions for procedure calls.
1892 * @param self The this pointer.
1893 * @param method_type The type of the method (procedure) in question.
1894 * @param abi The abi object to be modified
1896 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1904 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1908 /* set abi flags for calls */
1909 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1910 call_flags.bits.store_args_sequential = 0;
1911 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1912 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1913 call_flags.bits.call_has_imm = 0; /* No call immediates, we handle this by ourselves */
1915 /* set parameter passing style */
1916 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1918 if (get_method_variadicity(method_type) == variadicity_variadic) {
1919 /* pass all parameters of a variadic function on the stack */
1922 cc = get_method_calling_convention(method_type);
1923 if (get_method_additional_properties(method_type) & mtp_property_private &&
1924 ia32_cg_config.optimize_cc) {
1925 /* set the calling conventions to register parameter */
1926 cc = (cc & ~cc_bits) | cc_reg_param;
1930 /* we have to pop the shadow parameter ourself for compound calls */
1931 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1932 && !(cc & cc_reg_param)) {
1933 pop_amount += get_mode_size_bytes(mode_P_data);
1936 n = get_method_n_params(method_type);
1937 for (i = regnum = 0; i < n; i++) {
1939 const arch_register_t *reg = NULL;
1941 tp = get_method_param_type(method_type, i);
1942 mode = get_type_mode(tp);
1944 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1947 be_abi_call_param_reg(abi, i, reg);
1950 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1951 * movl has a shorter opcode than mov[sz][bw]l */
1952 ir_mode *load_mode = mode;
1955 unsigned size = get_mode_size_bytes(mode);
1957 if (cc & cc_callee_clear_stk) {
1958 pop_amount += (size + 3U) & ~3U;
1961 if (size < 4) load_mode = mode_Iu;
1964 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1968 be_abi_call_set_pop(abi, pop_amount);
1970 /* set return registers */
1971 n = get_method_n_ress(method_type);
1973 assert(n <= 2 && "more than two results not supported");
1975 /* In case of 64bit returns, we will have two 32bit values */
1977 tp = get_method_res_type(method_type, 0);
1978 mode = get_type_mode(tp);
1980 assert(!mode_is_float(mode) && "two FP results not supported");
1982 tp = get_method_res_type(method_type, 1);
1983 mode = get_type_mode(tp);
1985 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1987 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1988 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1991 const arch_register_t *reg;
1993 tp = get_method_res_type(method_type, 0);
1994 assert(is_atomic_type(tp));
1995 mode = get_type_mode(tp);
1997 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1999 be_abi_call_res_reg(abi, 0, reg);
2003 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
2007 if(!is_ia32_irn(irn)) {
2011 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
2012 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
2013 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
2014 || is_ia32_Immediate(irn))
2021 * Initializes the code generator interface.
2023 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
2026 return &ia32_code_gen_if;
2030 * Returns the estimated execution time of an ia32 irn.
2032 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
2034 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
2037 list_sched_selector_t ia32_sched_selector;
2040 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
2042 static const list_sched_selector_t *ia32_get_list_sched_selector(
2043 const void *self, list_sched_selector_t *selector)
2046 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
2047 ia32_sched_selector.exectime = ia32_sched_exectime;
2048 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
2049 return &ia32_sched_selector;
2052 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
2059 * Returns the necessary byte alignment for storing a register of given class.
2061 static int ia32_get_reg_class_alignment(const void *self,
2062 const arch_register_class_t *cls)
2064 ir_mode *mode = arch_register_class_mode(cls);
2065 int bytes = get_mode_size_bytes(mode);
2068 if (mode_is_float(mode) && bytes > 8)
2073 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
2074 const void *self, const ir_node *irn)
2076 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
2077 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
2078 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2081 static const be_execution_unit_t *_allowed_units_GP[] = {
2082 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2083 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2084 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2085 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2086 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2087 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2088 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2091 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2092 &be_machine_execution_units_DUMMY[0],
2095 static const be_execution_unit_t **_units_callret[] = {
2096 _allowed_units_BRANCH,
2099 static const be_execution_unit_t **_units_other[] = {
2103 static const be_execution_unit_t **_units_dummy[] = {
2104 _allowed_units_DUMMY,
2107 const be_execution_unit_t ***ret;
2110 if (is_ia32_irn(irn)) {
2111 ret = get_ia32_exec_units(irn);
2112 } else if (is_be_node(irn)) {
2113 if (be_is_Return(irn)) {
2114 ret = _units_callret;
2115 } else if (be_is_Barrier(irn)) {
2129 * Return the abstract ia32 machine.
2131 static const be_machine_t *ia32_get_machine(const void *self) {
2132 const ia32_isa_t *isa = self;
2137 * Return irp irgs in the desired order.
2139 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2146 static void ia32_mark_remat(const void *self, ir_node *node) {
2148 if (is_ia32_irn(node)) {
2149 set_ia32_is_remat(node);
2154 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2155 * @return 1 if allowed, 0 otherwise
2157 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2160 ir_node *cmp = NULL;
2162 /* we can't handle psis with 64bit compares yet */
2164 cmp = get_Proj_pred(sel);
2166 ir_node *left = get_Cmp_left(cmp);
2167 ir_mode *cmp_mode = get_irn_mode(left);
2168 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2175 if (ia32_cg_config.use_cmov) {
2176 if (ia32_cg_config.use_sse2 && cmp != NULL) {
2177 pn_Cmp pn = get_Proj_proj(sel);
2178 ir_node *cl = get_Cmp_left(cmp);
2179 ir_node *cr = get_Cmp_right(cmp);
2181 /* check the Phi nodes: no 64bit and no floating point cmov */
2182 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2183 ir_mode *mode = get_irn_mode(phi);
2185 if (mode_is_float(mode)) {
2186 /* check for Min, Max */
2187 ir_node *t = get_Phi_pred(phi, i);
2188 ir_node *f = get_Phi_pred(phi, j);
2191 /* SSE2 supports Min & Max */
2192 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2193 if (cl == t && cr == f) {
2194 /* Psi(a <=/>= b, a, b) => MIN, MAX */
2196 } else if (cl == f && cr == t) {
2197 /* Psi(a <=/>= b, b, a) => MAX, MIN */
2204 } else if (get_mode_size_bits(mode) > 32)
2208 /* check the Phi nodes: no 64bit and no floating point cmov */
2209 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2210 ir_mode *mode = get_irn_mode(phi);
2212 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2222 /* No cmov, only some special cases */
2226 /* Now some supported cases here */
2227 pn = get_Proj_proj(sel);
2228 cl = get_Cmp_left(cmp);
2229 cr = get_Cmp_right(cmp);
2231 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2232 ir_mode *mode = get_irn_mode(phi);
2236 t = get_Phi_pred(phi, i);
2237 f = get_Phi_pred(phi, j);
2239 /* no floating point and no 64bit yet */
2240 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2243 if (is_Const(t) && is_Const(f)) {
2244 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2245 /* always support Psi(x, C1, C2) */
2248 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2251 } else if (cl == t && cr == f) {
2252 /* Psi(a <=/>= b, a, b) => Min, Max */
2254 } else if (cl == f && cr == t) {
2255 /* Psi(a <=/>= b, b, a) => Max, Min */
2258 } else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2259 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2260 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2261 /* Psi(a >=u b, a - b, 0) unsigned Doz */
2263 } else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2264 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2265 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2266 /* Psi(a <=u b, 0, a - b) unsigned Doz */
2268 } else if (is_Const(cr) && is_Const_null(cr)) {
2269 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2270 /* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
2272 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2273 /* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
2281 /* all checks passed */
2287 static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
2292 /* we already added all our simple flags to the flags modifier list in
2293 * init, so this flag we don't know. */
2294 return ASM_CONSTRAINT_FLAG_INVALID;
2297 static int ia32_is_valid_clobber(const void *self, const char *clobber)
2301 return ia32_get_clobber_register(clobber) != NULL;
2305 * Returns the libFirm configuration parameter for this backend.
2307 static const backend_params *ia32_get_libfirm_params(void) {
2308 static const ir_settings_if_conv_t ifconv = {
2309 4, /* maxdepth, doesn't matter for Psi-conversion */
2310 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2312 static const ir_settings_arch_dep_t ad = {
2313 1, /* also use subs */
2314 4, /* maximum shifts */
2315 31, /* maximum shift amount */
2316 ia32_evaluate_insn, /* evaluate the instruction sequence */
2318 1, /* allow Mulhs */
2319 1, /* allow Mulus */
2320 32 /* Mulh allowed up to 32 bit */
2322 static backend_params p = {
2323 1, /* need dword lowering */
2324 1, /* support inline assembly */
2325 0, /* no immediate floating point mode. */
2326 NULL, /* no additional opcodes */
2327 NULL, /* will be set later */
2328 ia32_create_intrinsic_fkt,
2329 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2330 NULL, /* will be set below */
2331 NULL /* will be set below */
2334 ia32_setup_cg_config();
2336 /* doesn't really belong here, but this is the earliest place the backend
2338 init_asm_constraints();
2341 p.if_conv_info = &ifconv;
2345 static const lc_opt_enum_int_items_t gas_items[] = {
2346 { "elf", GAS_FLAVOUR_ELF },
2347 { "mingw", GAS_FLAVOUR_MINGW },
2348 { "yasm", GAS_FLAVOUR_YASM },
2349 { "macho", GAS_FLAVOUR_MACH_O },
2353 static lc_opt_enum_int_var_t gas_var = {
2354 (int*) &be_gas_flavour, gas_items
2357 static const lc_opt_enum_int_items_t transformer_items[] = {
2358 { "default", TRANSFORMER_DEFAULT },
2359 #ifdef FIRM_GRGEN_BE
2360 { "pbqp", TRANSFORMER_PBQP },
2361 { "random", TRANSFORMER_RAND },
2366 static lc_opt_enum_int_var_t transformer_var = {
2367 (int*)&be_transformer, transformer_items
2370 static const lc_opt_table_entry_t ia32_options[] = {
2371 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2372 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2373 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2374 &ia32_isa_template.arch_env.stack_alignment),
2378 const arch_isa_if_t ia32_isa_if = {
2381 ia32_get_n_reg_class,
2383 ia32_get_reg_class_for_mode,
2385 ia32_get_code_generator_if,
2386 ia32_get_list_sched_selector,
2387 ia32_get_ilp_sched_selector,
2388 ia32_get_reg_class_alignment,
2389 ia32_get_libfirm_params,
2390 ia32_get_allowed_execution_units,
2394 ia32_parse_asm_constraint,
2395 ia32_is_valid_clobber
2398 void ia32_init_emitter(void);
2399 void ia32_init_finish(void);
2400 void ia32_init_optimize(void);
2401 void ia32_init_transform(void);
2402 void ia32_init_x87(void);
2404 void be_init_arch_ia32(void)
2406 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2407 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2409 lc_opt_add_table(ia32_grp, ia32_options);
2410 be_register_isa_if("ia32", &ia32_isa_if);
2412 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2414 ia32_init_emitter();
2416 ia32_init_optimize();
2417 ia32_init_transform();
2419 ia32_init_architecture();
2422 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);