2 * This is the main ia32 firm backend driver.
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
41 #include "bearch_ia32_t.h"
43 #include "ia32_new_nodes.h" /* ia32 nodes interface */
44 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
45 #include "ia32_gen_decls.h" /* interface declaration emitter */
46 #include "ia32_transform.h"
47 #include "ia32_emitter.h"
48 #include "ia32_map_regs.h"
49 #include "ia32_optimize.h"
52 #define DEBUG_MODULE "firm.be.ia32.isa"
55 static set *cur_reg_set = NULL;
58 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
60 /* Creates the unique per irg GP NoReg node. */
61 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
62 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
65 /* Creates the unique per irg FP NoReg node. */
66 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
67 return be_abi_get_callee_save_irn(cg->birg->abi,
68 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
71 /**************************************************
74 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
75 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
76 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
77 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
80 **************************************************/
82 static ir_node *my_skip_proj(const ir_node *n) {
90 * Return register requirements for an ia32 node.
91 * If the node returns a tuple (mode_T) then the proj's
92 * will be asked for this information.
94 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
95 const ia32_irn_ops_t *ops = self;
96 const ia32_register_req_t *irn_req;
97 long node_pos = pos == -1 ? 0 : pos;
98 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
99 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
101 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
102 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
106 if (mode == mode_T && pos < 0) {
107 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
111 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
115 node_pos = ia32_translate_proj_pos(irn);
121 irn = my_skip_proj(irn);
123 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
126 if (is_ia32_irn(irn)) {
128 irn_req = get_ia32_in_req(irn, pos);
131 irn_req = get_ia32_out_req(irn, node_pos);
134 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
136 memcpy(req, &(irn_req->req), sizeof(*req));
138 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
139 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
140 req->other_same = get_irn_n(irn, irn_req->same_pos);
143 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
144 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
145 req->other_different = get_irn_n(irn, irn_req->different_pos);
149 /* treat Phi like Const with default requirements */
151 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
152 if (mode_is_float(mode)) {
153 if (USE_SSE2(ops->cg))
154 memcpy(req, &(ia32_default_req_ia32_xmm.req), sizeof(*req));
156 memcpy(req, &(ia32_default_req_ia32_vfp.req), sizeof(*req));
158 else if (mode_is_int(mode) || mode_is_reference(mode))
159 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
160 else if (mode == mode_T || mode == mode_M) {
161 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
165 assert(0 && "unsupported Phi-Mode");
168 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
176 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
178 const ia32_irn_ops_t *ops = self;
180 if (get_irn_mode(irn) == mode_X) {
184 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
187 pos = ia32_translate_proj_pos(irn);
188 irn = my_skip_proj(irn);
191 if (is_ia32_irn(irn)) {
192 const arch_register_t **slots;
194 slots = get_ia32_slots(irn);
198 ia32_set_firm_reg(irn, reg, cur_reg_set);
202 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
204 const arch_register_t *reg = NULL;
208 if (get_irn_mode(irn) == mode_X) {
212 pos = ia32_translate_proj_pos(irn);
213 irn = my_skip_proj(irn);
216 if (is_ia32_irn(irn)) {
217 const arch_register_t **slots;
218 slots = get_ia32_slots(irn);
222 reg = ia32_get_firm_reg(irn, cur_reg_set);
228 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
229 irn = my_skip_proj(irn);
231 return arch_irn_class_branch;
232 else if (is_ia32_irn(irn))
233 return arch_irn_class_normal;
238 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
239 irn = my_skip_proj(irn);
240 if (is_ia32_irn(irn))
241 return get_ia32_flags(irn);
247 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
248 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
251 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
253 const ia32_irn_ops_t *ops = self;
255 if (get_ia32_frame_ent(irn)) {
256 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
258 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
259 snprintf(buf, sizeof(buf), "%d", bias);
261 if (get_ia32_op_type(irn) == ia32_Normal) {
262 set_ia32_cnst(irn, buf);
265 add_ia32_am_offs(irn, buf);
267 set_ia32_am_flavour(irn, am_flav);
273 be_abi_call_flags_bits_t flags;
274 const arch_isa_t *isa;
275 const arch_env_t *aenv;
279 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
281 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
282 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
283 env->flags = fl.bits;
286 env->isa = aenv->isa;
290 static void ia32_abi_dont_save_regs(void *self, pset *s)
292 ia32_abi_env_t *env = self;
293 if(env->flags.try_omit_fp)
294 pset_insert_ptr(s, env->isa->bp);
298 * Generate the prologue.
299 * @param self The callback object.
300 * @param mem A pointer to the mem node. Update this if you define new memory.
301 * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
302 * @return The register which shall be used as a stack frame base.
304 * All nodes which define registers in @p reg_map must keep @p reg_map current.
306 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
308 ia32_abi_env_t *env = self;
310 if (!env->flags.try_omit_fp) {
311 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
312 ir_node *bl = get_irg_start_block(env->irg);
313 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
314 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
315 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
319 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_expand);
320 store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
321 set_ia32_am_support(store_bp, ia32_am_Dest);
322 set_ia32_am_flavour(store_bp, ia32_B);
323 set_ia32_op_type(store_bp, ia32_AddrModeD);
324 set_ia32_ls_mode(store_bp, env->isa->bp->reg_class->mode);
325 *mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
327 /* move esp to ebp */
328 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
329 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
330 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
331 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_dont_spill);
333 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
334 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
342 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
344 ia32_abi_env_t *env = self;
345 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
346 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
347 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
349 if (env->flags.try_omit_fp) {
350 /* simply remove the stack frame here */
351 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
356 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
357 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
359 /* copy ebp to esp */
360 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
363 load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
364 set_ia32_am_support(load_bp, ia32_am_Source);
365 set_ia32_am_flavour(load_bp, ia32_B);
366 set_ia32_op_type(load_bp, ia32_AddrModeS);
367 set_ia32_ls_mode(load_bp, mode_bp);
368 curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
369 *mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
370 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
372 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_shrink);
375 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
376 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
380 * Produces the type which sits between the stack args and the locals on the stack.
381 * it will contain the return address and space to store the old base pointer.
382 * @return The Firm type modeling the ABI between type.
384 static ir_type *ia32_abi_get_between_type(void *self)
386 static ir_type *omit_fp_between_type = NULL;
387 static ir_type *between_type = NULL;
389 ia32_abi_env_t *env = self;
393 entity *ret_addr_ent;
394 entity *omit_fp_ret_addr_ent;
396 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
397 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
399 between_type = new_type_class(new_id_from_str("ia32_between_type"));
400 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
401 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
403 set_entity_offset_bytes(old_bp_ent, 0);
404 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
405 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
407 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
408 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
410 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
411 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
414 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
417 static const be_abi_callbacks_t ia32_abi_callbacks = {
420 ia32_abi_get_between_type,
421 ia32_abi_dont_save_regs,
426 /* fill register allocator interface */
428 static const arch_irn_ops_if_t ia32_irn_ops_if = {
429 ia32_get_irn_reg_req,
434 ia32_get_frame_entity,
438 ia32_irn_ops_t ia32_irn_ops = {
445 /**************************************************
448 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
449 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
450 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
451 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
454 **************************************************/
457 * Transforms the standard firm graph into
460 static void ia32_prepare_graph(void *self) {
461 ia32_code_gen_t *cg = self;
462 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
464 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
465 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
466 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
468 DEBUG_ONLY(cg->mod = old_mod;)
471 edges_deactivate(cg->irg);
472 //dead_node_elimination(cg->irg);
473 edges_activate(cg->irg);
475 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
476 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
482 * Insert copies for all ia32 nodes where the should_be_same requirement
484 * Transform Sub into Neg -- Add if IN2 == OUT
486 static void ia32_finish_node(ir_node *irn, void *env) {
487 ia32_code_gen_t *cg = env;
488 const ia32_register_req_t **reqs;
489 const arch_register_t *out_reg, *in_reg, *in2_reg;
491 ir_node *copy, *in_node, *block, *in2_node;
492 ia32_op_type_t op_tp;
494 if (is_ia32_irn(irn)) {
495 /* AM Dest nodes don't produce any values */
496 op_tp = get_ia32_op_type(irn);
497 if (op_tp == ia32_AddrModeD)
500 reqs = get_ia32_out_req_all(irn);
501 n_res = get_ia32_n_res(irn);
502 block = get_nodes_block(irn);
504 /* check all OUT requirements, if there is a should_be_same */
505 if (op_tp == ia32_Normal) {
506 for (i = 0; i < n_res; i++) {
507 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
508 /* get in and out register */
509 out_reg = get_ia32_out_reg(irn, i);
510 in_node = get_irn_n(irn, reqs[i]->same_pos);
511 in_reg = arch_get_irn_register(cg->arch_env, in_node);
512 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
513 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
515 /* don't copy ignore nodes */
516 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
519 /* check if in and out register are equal */
520 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
521 /* in case of a commutative op: just exchange the in's */
522 if (is_ia32_commutative(irn) && REGS_ARE_EQUAL(out_reg, in2_reg)) {
523 set_irn_n(irn, reqs[i]->same_pos, in2_node);
524 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
527 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
528 /* create copy from in register */
529 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
531 /* destination is the out register */
532 arch_set_irn_register(cg->arch_env, copy, out_reg);
534 /* insert copy before the node into the schedule */
535 sched_add_before(irn, copy);
538 set_irn_n(irn, reqs[i]->same_pos, copy);
545 /* If we have a CondJmp with immediate, we need to */
546 /* check if it's the right operand, otherwise we have */
547 /* to change it, as CMP doesn't support immediate as */
549 if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) {
550 long pnc = get_negated_pnc(get_ia32_pncode(irn), get_ia32_res_mode(irn));
551 set_ia32_op_type(irn, ia32_AddrModeD);
552 set_ia32_pncode(irn, pnc);
555 /* check if there is a sub which need to be transformed */
556 ia32_transform_sub_to_neg_add(irn, cg);
558 /* transform a LEA into an Add if possible */
559 ia32_transform_lea_to_add(irn, cg);
563 /* check for peephole optimization */
564 ia32_peephole_optimization(irn, cg);
567 static void ia32_finish_irg_walker(ir_node *block, void *env) {
570 for (irn = sched_first(block); !sched_is_end(irn); irn = next) {
571 next = sched_next(irn);
572 ia32_finish_node(irn, env);
577 * Add Copy nodes for not fulfilled should_be_equal constraints
579 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
580 irg_block_walk_graph(irg, NULL, ia32_finish_irg_walker, cg);
586 * Dummy functions for hooks we don't need but which must be filled.
588 static void ia32_before_sched(void *self) {
592 * Called before the register allocator.
593 * Calculate a block schedule here. We need it for the x87
594 * simulator and the emitter.
596 static void ia32_before_ra(void *self) {
597 ia32_code_gen_t *cg = self;
599 cg->blk_sched = sched_create_block_schedule(cg->irg);
604 * Transforms a be node into a Load.
606 static void transform_to_Load(ia32_transform_env_t *env) {
607 ir_node *irn = env->irn;
608 entity *ent = be_get_frame_entity(irn);
609 ir_mode *mode = env->mode;
610 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
611 ir_node *nomem = new_rd_NoMem(env->irg);
612 ir_node *sched_point = NULL;
613 ir_node *ptr = get_irn_n(irn, 0);
614 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
615 ir_node *new_op, *proj;
616 const arch_register_t *reg;
618 if (sched_is_scheduled(irn)) {
619 sched_point = sched_prev(irn);
622 if (mode_is_float(mode)) {
623 if (USE_SSE2(env->cg))
624 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
626 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
629 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
632 set_ia32_am_support(new_op, ia32_am_Source);
633 set_ia32_op_type(new_op, ia32_AddrModeS);
634 set_ia32_am_flavour(new_op, ia32_B);
635 set_ia32_ls_mode(new_op, mode);
636 set_ia32_frame_ent(new_op, ent);
637 set_ia32_use_frame(new_op);
639 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
642 sched_add_after(sched_point, new_op);
643 sched_add_after(new_op, proj);
648 /* copy the register from the old node to the new Load */
649 reg = arch_get_irn_register(env->cg->arch_env, irn);
650 arch_set_irn_register(env->cg->arch_env, new_op, reg);
652 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
658 * Transforms a be node into a Store.
660 static void transform_to_Store(ia32_transform_env_t *env) {
661 ir_node *irn = env->irn;
662 entity *ent = be_get_frame_entity(irn);
663 ir_mode *mode = env->mode;
664 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
665 ir_node *nomem = new_rd_NoMem(env->irg);
666 ir_node *ptr = get_irn_n(irn, 0);
667 ir_node *val = get_irn_n(irn, 1);
668 ir_node *new_op, *proj;
669 ir_node *sched_point = NULL;
671 if (sched_is_scheduled(irn)) {
672 sched_point = sched_prev(irn);
675 if (mode_is_float(mode)) {
676 if (USE_SSE2(env->cg))
677 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
679 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
681 else if (get_mode_size_bits(mode) == 8) {
682 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
685 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
688 set_ia32_am_support(new_op, ia32_am_Dest);
689 set_ia32_op_type(new_op, ia32_AddrModeD);
690 set_ia32_am_flavour(new_op, ia32_B);
691 set_ia32_ls_mode(new_op, mode);
692 set_ia32_frame_ent(new_op, ent);
693 set_ia32_use_frame(new_op);
695 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, 0);
698 sched_add_after(sched_point, new_op);
699 sched_add_after(new_op, proj);
704 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
710 * Fix the mode of Spill/Reload
712 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
714 if (mode_is_float(mode)) {
726 * Block-Walker: Calls the transform functions Spill and Reload.
728 static void ia32_after_ra_walker(ir_node *block, void *env) {
729 ir_node *node, *prev;
730 ia32_code_gen_t *cg = env;
731 ia32_transform_env_t tenv;
734 tenv.irg = current_ir_graph;
736 DEBUG_ONLY(tenv.mod = cg->mod;)
738 /* beware: the schedule is changed here */
739 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
740 prev = sched_prev(node);
741 if (be_is_Reload(node)) {
742 /* we always reload the whole register */
743 tenv.dbg = get_irn_dbg_info(node);
745 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
746 transform_to_Load(&tenv);
748 else if (be_is_Spill(node)) {
749 /* we always spill the whole register */
750 tenv.dbg = get_irn_dbg_info(node);
752 tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
753 transform_to_Store(&tenv);
759 * We transform Spill and Reload here. This needs to be done before
760 * stack biasing otherwise we would miss the corrected offset for these nodes.
762 * If x87 instruction should be emitted, run the x87 simulator and patch
763 * the virtual instructions. This must obviously be done after register allocation.
765 static void ia32_after_ra(void *self) {
766 ia32_code_gen_t *cg = self;
767 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
769 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
770 if (cg->used_fp == fp_x87) {
771 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
777 * Emits the code, closes the output file and frees
778 * the code generator interface.
780 static void ia32_codegen(void *self) {
781 ia32_code_gen_t *cg = self;
782 ir_graph *irg = cg->irg;
784 ia32_finish_irg(irg, cg);
785 be_dump(irg, "-finished", dump_ir_block_graph_sched);
786 ia32_gen_routine(cg->isa->out, irg, cg);
790 /* remove it from the isa */
793 /* de-allocate code generator */
794 del_set(cg->reg_set);
799 static void *ia32_cg_init(const be_irg_t *birg);
801 static const arch_code_generator_if_t ia32_code_gen_if = {
803 NULL, /* before abi introduce hook */
805 ia32_before_sched, /* before scheduling hook */
806 ia32_before_ra, /* before register allocation hook */
807 ia32_after_ra, /* after register allocation hook */
808 ia32_codegen /* emit && done */
812 * Initializes a IA32 code generator.
814 static void *ia32_cg_init(const be_irg_t *birg) {
815 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
816 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
818 cg->impl = &ia32_code_gen_if;
820 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
821 cg->arch_env = birg->main_env->arch_env;
824 cg->blk_sched = NULL;
825 cg->fp_kind = isa->fp_kind;
826 cg->used_fp = fp_none;
828 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
830 /* set optimizations */
833 cg->opt.placecnst = 1;
841 if (isa->name_obst_size) {
842 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
843 isa->name_obst_size = 0;
844 obstack_free(isa->name_obst, NULL);
845 obstack_init(isa->name_obst);
851 if (isa->num_codegens > 1)
856 cur_reg_set = cg->reg_set;
858 ia32_irn_ops.cg = cg;
860 return (arch_code_generator_t *)cg;
865 /*****************************************************************
866 * ____ _ _ _____ _____
867 * | _ \ | | | | |_ _|/ ____| /\
868 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
869 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
870 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
871 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
873 *****************************************************************/
876 * The template that generates a new ISA object.
877 * Note that this template can be changed by command line
880 static ia32_isa_t ia32_isa_template = {
881 &ia32_isa_if, /* isa interface implementation */
882 &ia32_gp_regs[REG_ESP], /* stack pointer register */
883 &ia32_gp_regs[REG_EBP], /* base pointer register */
884 -1, /* stack direction */
885 0, /* number of code generator objects so far */
886 NULL, /* 16bit register names */
887 NULL, /* 8bit register names */
890 arch_pentium_4, /* instruction architecture */
891 arch_pentium_4, /* optimize for architecture */
892 fp_sse2, /* use sse2 unit */
893 NULL, /* current code generator */
895 NULL, /* name obstack */
896 0 /* name obst size */
901 * Initializes the backend ISA.
903 static void *ia32_init(FILE *file_handle) {
904 static int inited = 0;
910 isa = xmalloc(sizeof(*isa));
911 memcpy(isa, &ia32_isa_template, sizeof(*isa));
913 ia32_register_init(isa);
914 ia32_create_opcodes();
915 ia32_register_copy_attr_func();
917 isa->regs_16bit = pmap_create();
918 isa->regs_8bit = pmap_create();
919 isa->types = pmap_create();
920 isa->tv_ent = pmap_create();
921 isa->out = file_handle;
923 ia32_build_16bit_reg_map(isa->regs_16bit);
924 ia32_build_8bit_reg_map(isa->regs_8bit);
926 /* patch regigter names of x87 registers */
928 ia32_st_regs[0].name = "st";
929 ia32_st_regs[1].name = "st(1)";
930 ia32_st_regs[2].name = "st(2)";
931 ia32_st_regs[3].name = "st(3)";
932 ia32_st_regs[4].name = "st(4)";
933 ia32_st_regs[5].name = "st(5)";
934 ia32_st_regs[6].name = "st(6)";
935 ia32_st_regs[7].name = "st(7)";
939 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
940 obstack_init(isa->name_obst);
941 isa->name_obst_size = 0;
944 fprintf(isa->out, "\t.intel_syntax\n");
954 * Closes the output file and frees the ISA structure.
956 static void ia32_done(void *self) {
957 ia32_isa_t *isa = self;
959 /* emit now all global declarations */
960 ia32_gen_decls(isa->out);
962 pmap_destroy(isa->regs_16bit);
963 pmap_destroy(isa->regs_8bit);
964 pmap_destroy(isa->tv_ent);
965 pmap_destroy(isa->types);
968 //printf("name obst size = %d bytes\n", isa->name_obst_size);
969 obstack_free(isa->name_obst, NULL);
977 * Return the number of register classes for this architecture.
978 * We report always these:
979 * - the general purpose registers
980 * - the floating point register set (depending on the unit used for FP)
981 * - MMX/SSE registers (currently not supported)
983 static int ia32_get_n_reg_class(const void *self) {
988 * Return the register class for index i.
990 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
991 const ia32_isa_t *isa = self;
992 assert(i >= 0 && i < 2 && "Invalid ia32 register class requested.");
994 return &ia32_reg_classes[CLASS_ia32_gp];
995 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
999 * Get the register class which shall be used to store a value of a given mode.
1000 * @param self The this pointer.
1001 * @param mode The mode in question.
1002 * @return A register class which can hold values of the given mode.
1004 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1005 const ia32_isa_t *isa = self;
1006 if (mode_is_float(mode)) {
1007 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1010 return &ia32_reg_classes[CLASS_ia32_gp];
1014 * Get the ABI restrictions for procedure calls.
1015 * @param self The this pointer.
1016 * @param method_type The type of the method (procedure) in question.
1017 * @param abi The abi object to be modified
1019 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1020 const ia32_isa_t *isa = self;
1023 unsigned cc = get_method_calling_convention(method_type);
1024 int n = get_method_n_params(method_type);
1027 int i, ignore_1, ignore_2;
1029 const arch_register_t *reg;
1030 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1032 /* set abi flags for calls */
1033 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1034 call_flags.bits.store_args_sequential = 0; /* use stores instead of push */
1035 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1036 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1037 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1039 /* set stack parameter passing style */
1040 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1042 /* collect the mode for each type */
1043 modes = alloca(n * sizeof(modes[0]));
1045 for (i = 0; i < n; i++) {
1046 tp = get_method_param_type(method_type, i);
1047 modes[i] = get_type_mode(tp);
1050 /* set register parameters */
1051 if (cc & cc_reg_param) {
1052 /* determine the number of parameters passed via registers */
1053 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1055 /* loop over all parameters and set the register requirements */
1056 for (i = 0; i <= biggest_n; i++) {
1057 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1058 assert(reg && "kaputt");
1059 be_abi_call_param_reg(abi, i, reg);
1066 /* set stack parameters */
1067 for (i = stack_idx; i < n; i++) {
1068 be_abi_call_param_stack(abi, i, 1, 0, 0);
1072 /* set return registers */
1073 n = get_method_n_ress(method_type);
1075 assert(n <= 2 && "more than two results not supported");
1077 /* In case of 64bit returns, we will have two 32bit values */
1079 tp = get_method_res_type(method_type, 0);
1080 mode = get_type_mode(tp);
1082 assert(!mode_is_float(mode) && "two FP results not supported");
1084 tp = get_method_res_type(method_type, 1);
1085 mode = get_type_mode(tp);
1087 assert(!mode_is_float(mode) && "two FP results not supported");
1089 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1090 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1093 const arch_register_t *reg;
1095 tp = get_method_res_type(method_type, 0);
1096 assert(is_atomic_type(tp));
1097 mode = get_type_mode(tp);
1099 reg = mode_is_float(mode) ?
1100 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1101 &ia32_gp_regs[REG_EAX];
1103 be_abi_call_res_reg(abi, 0, reg);
1108 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1109 return &ia32_irn_ops;
1112 const arch_irn_handler_t ia32_irn_handler = {
1116 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1117 return &ia32_irn_handler;
1120 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1121 return is_ia32_irn(irn);
1125 * Initializes the code generator interface.
1127 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1128 return &ia32_code_gen_if;
1131 list_sched_selector_t ia32_sched_selector;
1134 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1136 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1137 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1138 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1139 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1140 return &ia32_sched_selector;
1144 * Returns the necessary byte alignment for storing a register of given class.
1146 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1147 ir_mode *mode = arch_register_class_mode(cls);
1148 int bytes = get_mode_size_bytes(mode);
1150 if (mode_is_float(mode) && bytes > 8)
1157 /* instruction set architectures. */
1158 static const lc_opt_enum_int_items_t arch_items[] = {
1159 { "386", arch_i386, },
1160 { "486", arch_i486, },
1161 { "pentium", arch_pentium, },
1162 { "586", arch_pentium, },
1163 { "pentiumpro", arch_pentium_pro, },
1164 { "686", arch_pentium_pro, },
1165 { "pentiummmx", arch_pentium_mmx, },
1166 { "pentiummmx", arch_pentium_mmx, },
1167 { "pentium2", arch_pentium_2, },
1168 { "p2", arch_pentium_2, },
1169 { "pentium3", arch_pentium_3, },
1170 { "p3", arch_pentium_3, },
1171 { "pentium4", arch_pentium_4, },
1172 { "p4", arch_pentium_4, },
1173 { "pentiumm", arch_pentium_m, },
1174 { "pm", arch_pentium_m, },
1175 { "core", arch_core, },
1177 { "athlon", arch_athlon, },
1178 { "athlon64", arch_athlon_64, },
1179 { "opteron", arch_opteron, },
1183 static lc_opt_enum_int_var_t arch_var = {
1184 &ia32_isa_template.arch, arch_items
1187 static lc_opt_enum_int_var_t opt_arch_var = {
1188 &ia32_isa_template.opt_arch, arch_items
1191 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1193 { "sse2", fp_sse2 },
1197 static lc_opt_enum_int_var_t fp_unit_var = {
1198 &ia32_isa_template.fp_kind, fp_unit_items
1201 static const lc_opt_table_entry_t ia32_options[] = {
1202 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1203 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1204 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1209 * Register command line options for the ia32 backend.
1213 * ia32-arch=arch create instruction for arch
1214 * ia32-opt=arch optimize for run on arch
1215 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1217 static void ia32_register_options(lc_opt_entry_t *ent)
1219 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1220 lc_opt_add_table(be_grp_ia32, ia32_options);
1222 #endif /* WITH_LIBCORE */
1224 const arch_isa_if_t ia32_isa_if = {
1227 ia32_get_n_reg_class,
1229 ia32_get_reg_class_for_mode,
1231 ia32_get_irn_handler,
1232 ia32_get_code_generator_if,
1233 ia32_get_list_sched_selector,
1234 ia32_get_reg_class_alignment,
1236 ia32_register_options