2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
38 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
56 #include "../benode_t.h"
57 #include "../belower.h"
58 #include "../besched.h"
61 #include "../beirgmod.h"
62 #include "../be_dbgout.h"
63 #include "../beblocksched.h"
64 #include "../bemachine.h"
65 #include "../beilpsched.h"
66 #include "../bespillslots.h"
67 #include "../bemodule.h"
68 #include "../begnuas.h"
69 #include "../bestate.h"
70 #include "../beflags.h"
71 #include "../betranshlp.h"
72 #include "../belistsched.h"
74 #include "bearch_ia32_t.h"
76 #include "ia32_new_nodes.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "gen_ia32_machine.h"
79 #include "ia32_common_transform.h"
80 #include "ia32_transform.h"
81 #include "ia32_emitter.h"
82 #include "ia32_map_regs.h"
83 #include "ia32_optimize.h"
85 #include "ia32_dbg_stat.h"
86 #include "ia32_finish.h"
87 #include "ia32_util.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
94 transformer_t be_transformer = TRANSFORMER_DEFAULT;
97 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
100 static set *cur_reg_set = NULL;
102 ir_mode *mode_fpcw = NULL;
103 ia32_code_gen_t *ia32_current_cg = NULL;
105 /** The current omit-fp state */
106 static unsigned ia32_curr_fp_ommitted = 0;
107 static ir_type *omit_fp_between_type = NULL;
108 static ir_type *between_type = NULL;
109 static ir_entity *old_bp_ent = NULL;
110 static ir_entity *ret_addr_ent = NULL;
111 static ir_entity *omit_fp_ret_addr_ent = NULL;
114 * The environment for the intrinsic mapping.
116 static ia32_intrinsic_env_t intrinsic_env = {
118 NULL, /* the irg, these entities belong to */
119 NULL, /* entity for __divdi3 library call */
120 NULL, /* entity for __moddi3 library call */
121 NULL, /* entity for __udivdi3 library call */
122 NULL, /* entity for __umoddi3 library call */
126 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
129 * Used to create per-graph unique pseudo nodes.
131 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
132 create_const_node_func func,
133 const arch_register_t* reg)
135 ir_node *block, *res;
140 block = get_irg_start_block(cg->irg);
141 res = func(NULL, block);
142 arch_set_irn_register(res, reg);
148 /* Creates the unique per irg GP NoReg node. */
149 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
150 return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
151 &ia32_gp_regs[REG_GP_NOREG]);
154 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
155 return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
156 &ia32_vfp_regs[REG_VFP_NOREG]);
159 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
160 return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
161 &ia32_xmm_regs[REG_XMM_NOREG]);
164 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
165 return create_const(cg, &cg->unknown_gp, new_bd_ia32_Unknown_GP,
166 &ia32_gp_regs[REG_GP_UKNWN]);
169 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
170 return create_const(cg, &cg->unknown_vfp, new_bd_ia32_Unknown_VFP,
171 &ia32_vfp_regs[REG_VFP_UKNWN]);
174 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
175 return create_const(cg, &cg->unknown_xmm, new_bd_ia32_Unknown_XMM,
176 &ia32_xmm_regs[REG_XMM_UKNWN]);
179 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
180 return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
181 &ia32_fp_cw_regs[REG_FPCW]);
186 * Returns the admissible noreg register node for input register pos of node irn.
188 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
190 const arch_register_req_t *req = arch_get_register_req(irn, pos);
192 assert(req != NULL && "Missing register requirements");
193 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
194 return ia32_new_NoReg_gp(cg);
196 if (ia32_cg_config.use_sse2) {
197 return ia32_new_NoReg_xmm(cg);
199 return ia32_new_NoReg_vfp(cg);
203 /**************************************************
206 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
207 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
208 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
209 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
212 **************************************************/
215 * Return register requirements for an ia32 node.
216 * If the node returns a tuple (mode_T) then the proj's
217 * will be asked for this information.
219 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
222 ir_mode *mode = get_irn_mode(node);
225 if (mode == mode_X || is_Block(node)) {
226 return arch_no_register_req;
229 if (mode == mode_T && pos < 0) {
230 return arch_no_register_req;
233 node_pos = pos == -1 ? 0 : pos;
235 if (mode == mode_M || pos >= 0) {
236 return arch_no_register_req;
239 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
240 node = skip_Proj_const(node);
243 if (is_ia32_irn(node)) {
244 const arch_register_req_t *req;
246 req = get_ia32_in_req(node, pos);
248 req = get_ia32_out_req(node, node_pos);
255 /* unknowns should be transformed already */
256 return arch_no_register_req;
259 static arch_irn_class_t ia32_classify(const ir_node *irn) {
260 arch_irn_class_t classification = 0;
262 irn = skip_Proj_const(irn);
265 classification |= arch_irn_class_branch;
267 if (! is_ia32_irn(irn))
268 return classification;
270 if (is_ia32_is_reload(irn))
271 classification |= arch_irn_class_reload;
273 if (is_ia32_is_spill(irn))
274 classification |= arch_irn_class_spill;
276 if (is_ia32_is_remat(irn))
277 classification |= arch_irn_class_remat;
279 return classification;
283 * The IA32 ABI callback object.
286 be_abi_call_flags_bits_t flags; /**< The call flags. */
287 const arch_env_t *aenv; /**< The architecture environment. */
288 ir_graph *irg; /**< The associated graph. */
291 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
292 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
295 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
296 set_ia32_frame_ent(irn, ent);
299 static void ia32_set_frame_offset(ir_node *irn, int bias)
301 if (get_ia32_frame_ent(irn) == NULL)
304 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
305 ia32_code_gen_t *cg = ia32_current_cg;
306 int omit_fp = be_abi_omit_fp(cg->birg->abi);
308 /* Pop nodes modify the stack pointer before calculating the
309 * destination address, so fix this here
314 add_ia32_am_offs_int(irn, bias);
317 static int ia32_get_sp_bias(const ir_node *node)
319 if (is_ia32_Call(node))
320 return -(int)get_ia32_call_attr_const(node)->pop;
322 if (is_ia32_Push(node))
325 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
332 * Generate the routine prologue.
334 * @param self The callback object.
335 * @param mem A pointer to the mem node. Update this if you define new memory.
336 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
337 * @param stack_bias Points to the current stack bias, can be modified if needed.
339 * @return The register which shall be used as a stack frame base.
341 * All nodes which define registers in @p reg_map must keep @p reg_map current.
343 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
345 ia32_abi_env_t *env = self;
346 ia32_code_gen_t *cg = ia32_current_cg;
347 const arch_env_t *arch_env = env->aenv;
349 ia32_curr_fp_ommitted = env->flags.try_omit_fp;
350 if (! env->flags.try_omit_fp) {
351 ir_node *bl = get_irg_start_block(env->irg);
352 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
353 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
354 ir_node *noreg = ia32_new_NoReg_gp(cg);
357 /* mark bp register as ignore */
358 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
359 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
362 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
363 curr_sp = new_r_Proj(bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
364 *mem = new_r_Proj(bl, push, mode_M, pn_ia32_Push_M);
366 /* the push must have SP out register */
367 arch_set_irn_register(curr_sp, arch_env->sp);
369 /* this modifies the stack bias, because we pushed 32bit */
372 /* move esp to ebp */
373 curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
374 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
375 arch_register_req_type_ignore);
377 /* beware: the copy must be done before any other sp use */
378 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
379 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
380 arch_register_req_type_produces_sp);
382 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
383 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
392 * Generate the routine epilogue.
393 * @param self The callback object.
394 * @param bl The block for the epilog
395 * @param mem A pointer to the mem node. Update this if you define new memory.
396 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
397 * @return The register which shall be used as a stack frame base.
399 * All nodes which define registers in @p reg_map must keep @p reg_map current.
401 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
403 ia32_abi_env_t *env = self;
404 const arch_env_t *arch_env = env->aenv;
405 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
406 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
408 if (env->flags.try_omit_fp) {
409 /* simply remove the stack frame here */
410 curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
412 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
414 if (ia32_cg_config.use_leave) {
418 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
419 curr_bp = new_r_Proj(bl, leave, mode_bp, pn_ia32_Leave_frame);
420 curr_sp = new_r_Proj(bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
424 /* the old SP is not needed anymore (kill the proj) */
425 assert(is_Proj(curr_sp));
428 /* copy ebp to esp */
429 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
430 arch_set_irn_register(curr_sp, arch_env->sp);
431 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
432 arch_register_req_type_ignore);
435 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
436 curr_bp = new_r_Proj(bl, pop, mode_bp, pn_ia32_Pop_res);
437 curr_sp = new_r_Proj(bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
439 *mem = new_r_Proj(bl, pop, mode_M, pn_ia32_Pop_M);
441 arch_set_irn_register(curr_sp, arch_env->sp);
442 arch_set_irn_register(curr_bp, arch_env->bp);
445 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
446 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
450 * Initialize the callback object.
451 * @param call The call object.
452 * @param aenv The architecture environment.
453 * @param irg The graph with the method.
454 * @return Some pointer. This pointer is passed to all other callback functions as self object.
456 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
458 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
459 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
460 env->flags = fl.bits;
467 * Destroy the callback object.
468 * @param self The callback object.
470 static void ia32_abi_done(void *self) {
475 * Build the between type and entities if not already build.
477 static void ia32_build_between_type(void) {
478 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
479 if (! between_type) {
480 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
481 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
483 between_type = new_type_struct(IDENT("ia32_between_type"));
484 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
485 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
487 set_entity_offset(old_bp_ent, 0);
488 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
489 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
490 set_type_state(between_type, layout_fixed);
492 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
493 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
495 set_entity_offset(omit_fp_ret_addr_ent, 0);
496 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
497 set_type_state(omit_fp_between_type, layout_fixed);
503 * Produces the type which sits between the stack args and the locals on the stack.
504 * it will contain the return address and space to store the old base pointer.
505 * @return The Firm type modeling the ABI between type.
507 static ir_type *ia32_abi_get_between_type(void *self)
509 ia32_abi_env_t *env = self;
511 ia32_build_between_type();
512 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
516 * Return the stack entity that contains the return address.
518 ir_entity *ia32_get_return_address_entity(void) {
519 ia32_build_between_type();
520 return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
524 * Return the stack entity that contains the frame address.
526 ir_entity *ia32_get_frame_address_entity(void) {
527 ia32_build_between_type();
528 return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
532 * Get the estimated cycle count for @p irn.
534 * @param self The this pointer.
535 * @param irn The node.
537 * @return The estimated cycle count for this operation
539 static int ia32_get_op_estimated_cost(const ir_node *irn)
542 ia32_op_type_t op_tp;
546 if (!is_ia32_irn(irn))
549 assert(is_ia32_irn(irn));
551 cost = get_ia32_latency(irn);
552 op_tp = get_ia32_op_type(irn);
554 if (is_ia32_CopyB(irn)) {
557 else if (is_ia32_CopyB_i(irn)) {
558 int size = get_ia32_copyb_size(irn);
559 cost = 20 + (int)ceil((4/3) * size);
561 /* in case of address mode operations add additional cycles */
562 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
564 In case of stack access and access to fixed addresses add 5 cycles
565 (we assume they are in cache), other memory operations cost 20
568 if (is_ia32_use_frame(irn) || (
569 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
570 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
582 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
584 * @param irn The original operation
585 * @param i Index of the argument we want the inverse operation to yield
586 * @param inverse struct to be filled with the resulting inverse op
587 * @param obstack The obstack to use for allocation of the returned nodes array
588 * @return The inverse operation or NULL if operation invertible
590 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
593 ir_node *block, *noreg, *nomem;
596 /* we cannot invert non-ia32 irns */
597 if (! is_ia32_irn(irn))
600 /* operand must always be a real operand (not base, index or mem) */
601 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
604 /* we don't invert address mode operations */
605 if (get_ia32_op_type(irn) != ia32_Normal)
608 /* TODO: adjust for new immediates... */
609 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
613 block = get_nodes_block(irn);
614 mode = get_irn_mode(irn);
615 irn_mode = get_irn_mode(irn);
616 noreg = get_irn_n(irn, 0);
618 dbg = get_irn_dbg_info(irn);
620 /* initialize structure */
621 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
625 switch (get_ia32_irn_opcode(irn)) {
628 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
629 /* we have an add with a const here */
630 /* invers == add with negated const */
631 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
633 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
634 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
635 set_ia32_commutative(inverse->nodes[0]);
637 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
638 /* we have an add with a symconst here */
639 /* invers == sub with const */
640 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
642 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
645 /* normal add: inverse == sub */
646 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
653 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
654 /* we have a sub with a const/symconst here */
655 /* invers == add with this const */
656 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
657 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
658 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
662 if (i == n_ia32_binary_left) {
663 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
666 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
674 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
675 /* xor with const: inverse = xor */
676 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
677 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
678 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
682 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
688 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
693 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
698 /* inverse operation not supported */
705 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
707 if(mode_is_float(mode))
714 * Get the mode that should be used for spilling value node
716 static ir_mode *get_spill_mode(const ir_node *node)
718 ir_mode *mode = get_irn_mode(node);
719 return get_spill_mode_mode(mode);
723 * Checks whether an addressmode reload for a node with mode mode is compatible
724 * with a spillslot of mode spill_mode
726 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
728 return !mode_is_float(mode) || mode == spillmode;
732 * Check if irn can load its operand at position i from memory (source addressmode).
733 * @param irn The irn to be checked
734 * @param i The operands position
735 * @return Non-Zero if operand can be loaded
737 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
739 ir_node *op = get_irn_n(irn, i);
740 const ir_mode *mode = get_irn_mode(op);
741 const ir_mode *spillmode = get_spill_mode(op);
743 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
744 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
745 !ia32_is_spillmode_compatible(mode, spillmode) ||
746 is_ia32_use_frame(irn)) /* must not already use frame */
749 switch (get_ia32_am_support(irn)) {
754 if (i != n_ia32_unary_op)
760 case n_ia32_binary_left: {
761 const arch_register_req_t *req;
762 if (!is_ia32_commutative(irn))
765 /* we can't swap left/right for limited registers
766 * (As this (currently) breaks constraint handling copies)
768 req = get_ia32_in_req(irn, n_ia32_binary_left);
769 if (req->type & arch_register_req_type_limited)
774 case n_ia32_binary_right:
783 panic("Unknown AM type");
786 /* HACK: must not already use "real" memory.
787 * This can happen for Call and Div */
788 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
794 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
798 ir_mode *dest_op_mode;
800 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
802 set_ia32_op_type(irn, ia32_AddrModeS);
804 load_mode = get_irn_mode(get_irn_n(irn, i));
805 dest_op_mode = get_ia32_ls_mode(irn);
806 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
807 set_ia32_ls_mode(irn, load_mode);
809 set_ia32_use_frame(irn);
810 set_ia32_need_stackent(irn);
812 if (i == n_ia32_binary_left &&
813 get_ia32_am_support(irn) == ia32_am_binary &&
814 /* immediates are only allowed on the right side */
815 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
816 ia32_swap_left_right(irn);
817 i = n_ia32_binary_right;
820 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
822 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
823 set_irn_n(irn, n_ia32_mem, spill);
824 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
825 set_ia32_is_reload(irn);
828 static const be_abi_callbacks_t ia32_abi_callbacks = {
831 ia32_abi_get_between_type,
836 /* fill register allocator interface */
838 static const arch_irn_ops_t ia32_irn_ops = {
839 ia32_get_irn_reg_req,
841 ia32_get_frame_entity,
842 ia32_set_frame_entity,
843 ia32_set_frame_offset,
846 ia32_get_op_estimated_cost,
847 ia32_possible_memory_operand,
848 ia32_perform_memory_operand,
851 /**************************************************
854 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
855 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
856 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
857 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
860 **************************************************/
862 static ir_entity *mcount = NULL;
864 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
866 static void ia32_before_abi(void *self) {
867 lower_mode_b_config_t lower_mode_b_config = {
868 mode_Iu, /* lowered mode */
869 mode_Bu, /* preferred mode for set */
870 0, /* don't lower direct compares */
872 ia32_code_gen_t *cg = self;
874 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
876 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
878 if (mcount == NULL) {
879 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
880 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
881 /* FIXME: enter the right ld_ident here */
882 set_entity_ld_ident(mcount, get_entity_ident(mcount));
883 set_entity_visibility(mcount, visibility_external_allocated);
885 instrument_initcall(cg->irg, mcount);
890 * Transforms the standard firm graph into
893 static void ia32_prepare_graph(void *self)
895 ia32_code_gen_t *cg = self;
896 ir_graph *irg = cg->irg;
898 /* do local optimizations */
899 optimize_graph_df(irg);
901 /* we have to do cfopt+remove_critical_edges as we can't have Bad-blocks
902 * or critical edges in the backend */
904 remove_critical_cf_edges(irg);
906 /* TODO: we often have dead code reachable through out-edges here. So for
907 * now we rebuild edges (as we need correct user count for code selection)
910 edges_deactivate(cg->irg);
911 edges_activate(cg->irg);
915 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
917 switch (be_transformer) {
918 case TRANSFORMER_DEFAULT:
919 /* transform remaining nodes into assembler instructions */
920 ia32_transform_graph(cg);
924 case TRANSFORMER_PBQP:
925 case TRANSFORMER_RAND:
926 /* transform nodes into assembler instructions by PBQP magic */
927 ia32_transform_graph_by_pbqp(cg);
932 panic("invalid transformer");
935 /* do local optimizations (mainly CSE) */
936 optimize_graph_df(cg->irg);
939 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
941 /* optimize address mode */
942 ia32_optimize_graph(cg);
944 /* do code placement, to optimize the position of constants */
948 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
951 ir_node *turn_back_am(ir_node *node)
953 dbg_info *dbgi = get_irn_dbg_info(node);
954 ir_node *block = get_nodes_block(node);
955 ir_node *base = get_irn_n(node, n_ia32_base);
956 ir_node *index = get_irn_n(node, n_ia32_index);
957 ir_node *mem = get_irn_n(node, n_ia32_mem);
960 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
961 ir_node *load_res = new_rd_Proj(dbgi, block, load, mode_Iu, pn_ia32_Load_res);
963 ia32_copy_am_attrs(load, node);
964 if (is_ia32_is_reload(node))
965 set_ia32_is_reload(load);
966 set_irn_n(node, n_ia32_mem, new_NoMem());
968 switch (get_ia32_am_support(node)) {
970 set_irn_n(node, n_ia32_unary_op, load_res);
974 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
975 set_irn_n(node, n_ia32_binary_left, load_res);
977 set_irn_n(node, n_ia32_binary_right, load_res);
982 panic("Unknown AM type");
984 noreg = ia32_new_NoReg_gp(ia32_current_cg);
985 set_irn_n(node, n_ia32_base, noreg);
986 set_irn_n(node, n_ia32_index, noreg);
987 set_ia32_am_offs_int(node, 0);
988 set_ia32_am_sc(node, NULL);
989 set_ia32_am_scale(node, 0);
990 clear_ia32_am_sc_sign(node);
992 /* rewire mem-proj */
993 if (get_irn_mode(node) == mode_T) {
994 const ir_edge_t *edge;
995 foreach_out_edge(node, edge) {
996 ir_node *out = get_edge_src_irn(edge);
997 if (get_irn_mode(out) == mode_M) {
998 set_Proj_pred(out, load);
999 set_Proj_proj(out, pn_ia32_Load_M);
1005 set_ia32_op_type(node, ia32_Normal);
1006 if (sched_is_scheduled(node))
1007 sched_add_before(node, load);
1012 static ir_node *flags_remat(ir_node *node, ir_node *after)
1014 /* we should turn back source address mode when rematerializing nodes */
1015 ia32_op_type_t type;
1019 if (is_Block(after)) {
1022 block = get_nodes_block(after);
1025 type = get_ia32_op_type(node);
1027 case ia32_AddrModeS:
1031 case ia32_AddrModeD:
1032 /* TODO implement this later... */
1033 panic("found DestAM with flag user %+F this should not happen", node);
1036 default: assert(type == ia32_Normal); break;
1039 copy = exact_copy(node);
1040 set_nodes_block(copy, block);
1041 sched_add_after(after, copy);
1047 * Called before the register allocator.
1049 static void ia32_before_ra(void *self) {
1050 ia32_code_gen_t *cg = self;
1052 /* setup fpu rounding modes */
1053 ia32_setup_fpu_mode(cg);
1056 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1059 ia32_add_missing_keeps(cg);
1064 * Transforms a be_Reload into a ia32 Load.
1066 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1067 ir_graph *irg = get_irn_irg(node);
1068 dbg_info *dbg = get_irn_dbg_info(node);
1069 ir_node *block = get_nodes_block(node);
1070 ir_entity *ent = be_get_frame_entity(node);
1071 ir_mode *mode = get_irn_mode(node);
1072 ir_mode *spillmode = get_spill_mode(node);
1073 ir_node *noreg = ia32_new_NoReg_gp(cg);
1074 ir_node *sched_point = NULL;
1075 ir_node *ptr = get_irg_frame(irg);
1076 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1077 ir_node *new_op, *proj;
1078 const arch_register_t *reg;
1080 if (sched_is_scheduled(node)) {
1081 sched_point = sched_prev(node);
1084 if (mode_is_float(spillmode)) {
1085 if (ia32_cg_config.use_sse2)
1086 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
1088 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
1090 else if (get_mode_size_bits(spillmode) == 128) {
1091 /* Reload 128 bit SSE registers */
1092 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
1095 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1097 set_ia32_op_type(new_op, ia32_AddrModeS);
1098 set_ia32_ls_mode(new_op, spillmode);
1099 set_ia32_frame_ent(new_op, ent);
1100 set_ia32_use_frame(new_op);
1101 set_ia32_is_reload(new_op);
1103 DBG_OPT_RELOAD2LD(node, new_op);
1105 proj = new_rd_Proj(dbg, block, new_op, mode, pn_ia32_Load_res);
1108 sched_add_after(sched_point, new_op);
1112 /* copy the register from the old node to the new Load */
1113 reg = arch_get_irn_register(node);
1114 arch_set_irn_register(proj, reg);
1116 SET_IA32_ORIG_NODE(new_op, node);
1118 exchange(node, proj);
1122 * Transforms a be_Spill node into a ia32 Store.
1124 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1125 ir_graph *irg = get_irn_irg(node);
1126 dbg_info *dbg = get_irn_dbg_info(node);
1127 ir_node *block = get_nodes_block(node);
1128 ir_entity *ent = be_get_frame_entity(node);
1129 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1130 ir_mode *mode = get_spill_mode(spillval);
1131 ir_node *noreg = ia32_new_NoReg_gp(cg);
1132 ir_node *nomem = new_NoMem();
1133 ir_node *ptr = get_irg_frame(irg);
1134 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1136 ir_node *sched_point = NULL;
1138 if (sched_is_scheduled(node)) {
1139 sched_point = sched_prev(node);
1142 /* No need to spill unknown values... */
1143 if(is_ia32_Unknown_GP(val) ||
1144 is_ia32_Unknown_VFP(val) ||
1145 is_ia32_Unknown_XMM(val)) {
1150 exchange(node, store);
1154 if (mode_is_float(mode)) {
1155 if (ia32_cg_config.use_sse2)
1156 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1158 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1159 } else if (get_mode_size_bits(mode) == 128) {
1160 /* Spill 128 bit SSE registers */
1161 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1162 } else if (get_mode_size_bits(mode) == 8) {
1163 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1165 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1168 set_ia32_op_type(store, ia32_AddrModeD);
1169 set_ia32_ls_mode(store, mode);
1170 set_ia32_frame_ent(store, ent);
1171 set_ia32_use_frame(store);
1172 set_ia32_is_spill(store);
1173 SET_IA32_ORIG_NODE(store, node);
1174 DBG_OPT_SPILL2ST(node, store);
1177 sched_add_after(sched_point, store);
1181 exchange(node, store);
1184 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1185 dbg_info *dbg = get_irn_dbg_info(node);
1186 ir_node *block = get_nodes_block(node);
1187 ir_node *noreg = ia32_new_NoReg_gp(cg);
1188 ir_graph *irg = get_irn_irg(node);
1189 ir_node *frame = get_irg_frame(irg);
1191 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1193 set_ia32_frame_ent(push, ent);
1194 set_ia32_use_frame(push);
1195 set_ia32_op_type(push, ia32_AddrModeS);
1196 set_ia32_ls_mode(push, mode_Is);
1197 set_ia32_is_spill(push);
1199 sched_add_before(schedpoint, push);
1203 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1204 dbg_info *dbg = get_irn_dbg_info(node);
1205 ir_node *block = get_nodes_block(node);
1206 ir_node *noreg = ia32_new_NoReg_gp(cg);
1207 ir_graph *irg = get_irn_irg(node);
1208 ir_node *frame = get_irg_frame(irg);
1210 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
1212 set_ia32_frame_ent(pop, ent);
1213 set_ia32_use_frame(pop);
1214 set_ia32_op_type(pop, ia32_AddrModeD);
1215 set_ia32_ls_mode(pop, mode_Is);
1216 set_ia32_is_reload(pop);
1218 sched_add_before(schedpoint, pop);
1223 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1225 dbg_info *dbg = get_irn_dbg_info(node);
1226 ir_node *block = get_nodes_block(node);
1227 ir_mode *spmode = mode_Iu;
1228 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1231 sp = new_rd_Proj(dbg, block, pred, spmode, pos);
1232 arch_set_irn_register(sp, spreg);
1238 * Transform MemPerm, currently we do this the ugly way and produce
1239 * push/pop into/from memory cascades. This is possible without using
1242 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
1244 ir_node *block = get_nodes_block(node);
1245 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1246 int arity = be_get_MemPerm_entity_arity(node);
1247 ir_node **pops = ALLOCAN(ir_node*, arity);
1251 const ir_edge_t *edge;
1252 const ir_edge_t *next;
1255 for(i = 0; i < arity; ++i) {
1256 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1257 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1258 ir_type *enttype = get_entity_type(inent);
1259 unsigned entsize = get_type_size_bytes(enttype);
1260 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1261 ir_node *mem = get_irn_n(node, i + 1);
1264 /* work around cases where entities have different sizes */
1265 if(entsize2 < entsize)
1267 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1269 push = create_push(cg, node, node, sp, mem, inent);
1270 sp = create_spproj(node, push, pn_ia32_Push_stack);
1272 /* add another push after the first one */
1273 push = create_push(cg, node, node, sp, mem, inent);
1274 add_ia32_am_offs_int(push, 4);
1275 sp = create_spproj(node, push, pn_ia32_Push_stack);
1278 set_irn_n(node, i, new_Bad());
1282 for(i = arity - 1; i >= 0; --i) {
1283 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1284 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1285 ir_type *enttype = get_entity_type(outent);
1286 unsigned entsize = get_type_size_bytes(enttype);
1287 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1290 /* work around cases where entities have different sizes */
1291 if(entsize2 < entsize)
1293 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1295 pop = create_pop(cg, node, node, sp, outent);
1296 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1298 add_ia32_am_offs_int(pop, 4);
1300 /* add another pop after the first one */
1301 pop = create_pop(cg, node, node, sp, outent);
1302 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1309 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], block, 1, in);
1310 sched_add_before(node, keep);
1312 /* exchange memprojs */
1313 foreach_out_edge_safe(node, edge, next) {
1314 ir_node *proj = get_edge_src_irn(edge);
1315 int p = get_Proj_proj(proj);
1319 set_Proj_pred(proj, pops[p]);
1320 set_Proj_proj(proj, pn_ia32_Pop_M);
1323 /* remove memperm */
1324 arity = get_irn_arity(node);
1325 for(i = 0; i < arity; ++i) {
1326 set_irn_n(node, i, new_Bad());
1332 * Block-Walker: Calls the transform functions Spill and Reload.
1334 static void ia32_after_ra_walker(ir_node *block, void *env) {
1335 ir_node *node, *prev;
1336 ia32_code_gen_t *cg = env;
1338 /* beware: the schedule is changed here */
1339 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1340 prev = sched_prev(node);
1342 if (be_is_Reload(node)) {
1343 transform_to_Load(cg, node);
1344 } else if (be_is_Spill(node)) {
1345 transform_to_Store(cg, node);
1346 } else if (be_is_MemPerm(node)) {
1347 transform_MemPerm(cg, node);
1353 * Collects nodes that need frame entities assigned.
1355 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1357 be_fec_env_t *env = data;
1358 const ir_mode *mode;
1361 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1362 mode = get_spill_mode_mode(get_irn_mode(node));
1363 align = get_mode_size_bytes(mode);
1364 } else if (is_ia32_irn(node) &&
1365 get_ia32_frame_ent(node) == NULL &&
1366 is_ia32_use_frame(node)) {
1367 if (is_ia32_need_stackent(node))
1370 switch (get_ia32_irn_opcode(node)) {
1372 case iro_ia32_Load: {
1373 const ia32_attr_t *attr = get_ia32_attr_const(node);
1375 if (attr->data.need_32bit_stackent) {
1377 } else if (attr->data.need_64bit_stackent) {
1380 mode = get_ia32_ls_mode(node);
1381 if (is_ia32_is_reload(node))
1382 mode = get_spill_mode_mode(mode);
1384 align = get_mode_size_bytes(mode);
1388 case iro_ia32_vfild:
1390 case iro_ia32_xLoad: {
1391 mode = get_ia32_ls_mode(node);
1396 case iro_ia32_FldCW: {
1397 /* although 2 byte would be enough 4 byte performs best */
1405 panic("unexpected frame user while collection frame entity nodes");
1407 case iro_ia32_FnstCW:
1408 case iro_ia32_Store8Bit:
1409 case iro_ia32_Store:
1412 case iro_ia32_vfist:
1413 case iro_ia32_vfisttp:
1415 case iro_ia32_xStore:
1416 case iro_ia32_xStoreSimple:
1423 be_node_needs_frame_entity(env, node, mode, align);
1427 * We transform Spill and Reload here. This needs to be done before
1428 * stack biasing otherwise we would miss the corrected offset for these nodes.
1430 static void ia32_after_ra(void *self) {
1431 ia32_code_gen_t *cg = self;
1432 ir_graph *irg = cg->irg;
1433 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1435 /* create and coalesce frame entities */
1436 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1437 be_assign_entities(fec_env);
1438 be_free_frame_entity_coalescer(fec_env);
1440 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1444 * Last touchups for the graph before emit: x87 simulation to replace the
1445 * virtual with real x87 instructions, creating a block schedule and peephole
1448 static void ia32_finish(void *self) {
1449 ia32_code_gen_t *cg = self;
1450 ir_graph *irg = cg->irg;
1452 ia32_finish_irg(irg, cg);
1454 /* we might have to rewrite x87 virtual registers */
1455 if (cg->do_x87_sim) {
1456 x87_simulate_graph(cg->birg);
1459 /* do peephole optimisations */
1460 ia32_peephole_optimization(cg);
1462 /* create block schedule, this also removes empty blocks which might
1463 * produce critical edges */
1464 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1468 * Emits the code, closes the output file and frees
1469 * the code generator interface.
1471 static void ia32_codegen(void *self) {
1472 ia32_code_gen_t *cg = self;
1473 ir_graph *irg = cg->irg;
1475 ia32_gen_routine(cg, irg);
1479 /* remove it from the isa */
1482 assert(ia32_current_cg == cg);
1483 ia32_current_cg = NULL;
1485 /* de-allocate code generator */
1486 del_set(cg->reg_set);
1491 * Returns the node representing the PIC base.
1493 static ir_node *ia32_get_pic_base(void *self) {
1495 ia32_code_gen_t *cg = self;
1496 ir_node *get_eip = cg->get_eip;
1497 if (get_eip != NULL)
1500 block = get_irg_start_block(cg->irg);
1501 get_eip = new_bd_ia32_GetEIP(NULL, block);
1502 cg->get_eip = get_eip;
1504 be_dep_on_frame(get_eip);
1508 static void *ia32_cg_init(be_irg_t *birg);
1510 static const arch_code_generator_if_t ia32_code_gen_if = {
1512 ia32_get_pic_base, /* return node used as base in pic code addresses */
1513 ia32_before_abi, /* before abi introduce hook */
1516 ia32_before_ra, /* before register allocation hook */
1517 ia32_after_ra, /* after register allocation hook */
1518 ia32_finish, /* called before codegen */
1519 ia32_codegen /* emit && done */
1523 * Initializes a IA32 code generator.
1525 static void *ia32_cg_init(be_irg_t *birg) {
1526 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1527 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1529 cg->impl = &ia32_code_gen_if;
1530 cg->irg = birg->irg;
1531 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1534 cg->blk_sched = NULL;
1535 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1536 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1539 /* Linux gprof implementation needs base pointer */
1540 birg->main_env->options->omit_fp = 0;
1547 if (isa->name_obst) {
1548 obstack_free(isa->name_obst, NULL);
1549 obstack_init(isa->name_obst);
1553 cur_reg_set = cg->reg_set;
1555 assert(ia32_current_cg == NULL);
1556 ia32_current_cg = cg;
1558 return (arch_code_generator_t *)cg;
1563 /*****************************************************************
1564 * ____ _ _ _____ _____
1565 * | _ \ | | | | |_ _|/ ____| /\
1566 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1567 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1568 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1569 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1571 *****************************************************************/
1574 * Set output modes for GCC
1576 static const tarval_mode_info mo_integer = {
1583 * set the tarval output mode of all integer modes to decimal
1585 static void set_tarval_output_modes(void)
1589 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1590 ir_mode *mode = get_irp_mode(i);
1592 if (mode_is_int(mode))
1593 set_tarval_mode_output_option(mode, &mo_integer);
1597 const arch_isa_if_t ia32_isa_if;
1600 * The template that generates a new ISA object.
1601 * Note that this template can be changed by command line
1604 static ia32_isa_t ia32_isa_template = {
1606 &ia32_isa_if, /* isa interface implementation */
1607 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1608 &ia32_gp_regs[REG_EBP], /* base pointer register */
1609 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1610 -1, /* stack direction */
1611 2, /* power of two stack alignment, 2^2 == 4 */
1612 NULL, /* main environment */
1613 7, /* costs for a spill instruction */
1614 5, /* costs for a reload instruction */
1616 NULL, /* 16bit register names */
1617 NULL, /* 8bit register names */
1618 NULL, /* 8bit register names high */
1621 NULL, /* current code generator */
1622 NULL, /* abstract machine */
1624 NULL, /* name obstack */
1628 static void init_asm_constraints(void)
1630 be_init_default_asm_constraint_flags();
1632 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1633 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1634 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1635 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1636 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1637 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1638 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1639 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1640 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1641 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1642 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1643 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1644 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1645 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1646 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1647 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1648 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1649 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1650 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1651 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1653 /* no support for autodecrement/autoincrement */
1654 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1655 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1656 /* no float consts */
1657 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1658 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1659 /* makes no sense on x86 */
1660 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1661 /* no support for sse consts yet */
1662 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1663 /* no support for x87 consts yet */
1664 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1665 /* no support for mmx registers yet */
1666 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1667 /* not available in 32bit mode */
1668 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1669 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1671 /* no code yet to determine register class needed... */
1672 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1676 * Initializes the backend ISA.
1678 static arch_env_t *ia32_init(FILE *file_handle) {
1679 static int inited = 0;
1687 set_tarval_output_modes();
1689 isa = XMALLOC(ia32_isa_t);
1690 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1692 if(mode_fpcw == NULL) {
1693 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1696 ia32_register_init();
1697 ia32_create_opcodes(&ia32_irn_ops);
1699 be_emit_init(file_handle);
1700 isa->regs_16bit = pmap_create();
1701 isa->regs_8bit = pmap_create();
1702 isa->regs_8bit_high = pmap_create();
1703 isa->types = pmap_create();
1704 isa->tv_ent = pmap_create();
1705 isa->cpu = ia32_init_machine_description();
1707 ia32_build_16bit_reg_map(isa->regs_16bit);
1708 ia32_build_8bit_reg_map(isa->regs_8bit);
1709 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1712 isa->name_obst = XMALLOC(struct obstack);
1713 obstack_init(isa->name_obst);
1716 /* enter the ISA object into the intrinsic environment */
1717 intrinsic_env.isa = isa;
1719 /* emit asm includes */
1720 n = get_irp_n_asms();
1721 for (i = 0; i < n; ++i) {
1722 be_emit_cstring("#APP\n");
1723 be_emit_ident(get_irp_asm(i));
1724 be_emit_cstring("\n#NO_APP\n");
1727 /* needed for the debug support */
1728 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1729 be_emit_cstring(".Ltext0:\n");
1730 be_emit_write_line();
1732 /* we mark referenced global entities, so we can only emit those which
1733 * are actually referenced. (Note: you mustn't use the type visited flag
1734 * elsewhere in the backend)
1736 inc_master_type_visited();
1738 return &isa->arch_env;
1744 * Closes the output file and frees the ISA structure.
1746 static void ia32_done(void *self) {
1747 ia32_isa_t *isa = self;
1749 /* emit now all global declarations */
1750 be_gas_emit_decls(isa->arch_env.main_env, 1);
1752 pmap_destroy(isa->regs_16bit);
1753 pmap_destroy(isa->regs_8bit);
1754 pmap_destroy(isa->regs_8bit_high);
1755 pmap_destroy(isa->tv_ent);
1756 pmap_destroy(isa->types);
1759 obstack_free(isa->name_obst, NULL);
1769 * Return the number of register classes for this architecture.
1770 * We report always these:
1771 * - the general purpose registers
1772 * - the SSE floating point register set
1773 * - the virtual floating point registers
1774 * - the SSE vector register set
1776 static unsigned ia32_get_n_reg_class(const void *self) {
1782 * Return the register class for index i.
1784 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1788 assert(i < N_CLASSES);
1789 return &ia32_reg_classes[i];
1793 * Get the register class which shall be used to store a value of a given mode.
1794 * @param self The this pointer.
1795 * @param mode The mode in question.
1796 * @return A register class which can hold values of the given mode.
1798 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1799 const ir_mode *mode)
1803 if (mode_is_float(mode)) {
1804 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1807 return &ia32_reg_classes[CLASS_ia32_gp];
1811 * Get the ABI restrictions for procedure calls.
1812 * @param self The this pointer.
1813 * @param method_type The type of the method (procedure) in question.
1814 * @param abi The abi object to be modified
1816 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1824 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1828 /* set abi flags for calls */
1829 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1830 call_flags.bits.store_args_sequential = 0;
1831 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1832 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1833 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1835 /* set parameter passing style */
1836 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1838 cc = get_method_calling_convention(method_type);
1839 if (get_method_variadicity(method_type) == variadicity_variadic) {
1840 /* pass all parameters of a variadic function on the stack */
1841 cc = cc_cdecl_set | (cc & cc_this_call);
1843 if (get_method_additional_properties(method_type) & mtp_property_private &&
1844 ia32_cg_config.optimize_cc) {
1845 /* set the fast calling conventions (allowing up to 3) */
1846 cc = SET_FASTCALL(cc) | 3;
1850 /* we have to pop the shadow parameter ourself for compound calls */
1851 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1852 && !(cc & cc_reg_param)) {
1853 pop_amount += get_mode_size_bytes(mode_P_data);
1856 n = get_method_n_params(method_type);
1857 for (i = regnum = 0; i < n; i++) {
1859 const arch_register_t *reg = NULL;
1861 tp = get_method_param_type(method_type, i);
1862 mode = get_type_mode(tp);
1864 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1867 be_abi_call_param_reg(abi, i, reg);
1870 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1871 * movl has a shorter opcode than mov[sz][bw]l */
1872 ir_mode *load_mode = mode;
1875 unsigned size = get_mode_size_bytes(mode);
1877 if (cc & cc_callee_clear_stk) {
1878 pop_amount += (size + 3U) & ~3U;
1881 if (size < 4) load_mode = mode_Iu;
1884 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1888 be_abi_call_set_pop(abi, pop_amount);
1890 /* set return registers */
1891 n = get_method_n_ress(method_type);
1893 assert(n <= 2 && "more than two results not supported");
1895 /* In case of 64bit returns, we will have two 32bit values */
1897 tp = get_method_res_type(method_type, 0);
1898 mode = get_type_mode(tp);
1900 assert(!mode_is_float(mode) && "two FP results not supported");
1902 tp = get_method_res_type(method_type, 1);
1903 mode = get_type_mode(tp);
1905 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1907 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1908 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1911 const arch_register_t *reg;
1913 tp = get_method_res_type(method_type, 0);
1914 assert(is_atomic_type(tp));
1915 mode = get_type_mode(tp);
1917 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1919 be_abi_call_res_reg(abi, 0, reg);
1923 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1927 if(!is_ia32_irn(irn)) {
1931 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1932 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1933 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1934 || is_ia32_Immediate(irn))
1941 * Initializes the code generator interface.
1943 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1946 return &ia32_code_gen_if;
1950 * Returns the estimated execution time of an ia32 irn.
1952 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1954 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1957 list_sched_selector_t ia32_sched_selector;
1960 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1962 static const list_sched_selector_t *ia32_get_list_sched_selector(
1963 const void *self, list_sched_selector_t *selector)
1966 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1967 ia32_sched_selector.exectime = ia32_sched_exectime;
1968 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1969 return &ia32_sched_selector;
1972 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1979 * Returns the necessary byte alignment for storing a register of given class.
1981 static int ia32_get_reg_class_alignment(const void *self,
1982 const arch_register_class_t *cls)
1984 ir_mode *mode = arch_register_class_mode(cls);
1985 int bytes = get_mode_size_bytes(mode);
1988 if (mode_is_float(mode) && bytes > 8)
1993 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1994 const void *self, const ir_node *irn)
1996 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1997 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1998 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2001 static const be_execution_unit_t *_allowed_units_GP[] = {
2002 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2003 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2004 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2005 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2006 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2007 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2008 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2011 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2012 &be_machine_execution_units_DUMMY[0],
2015 static const be_execution_unit_t **_units_callret[] = {
2016 _allowed_units_BRANCH,
2019 static const be_execution_unit_t **_units_other[] = {
2023 static const be_execution_unit_t **_units_dummy[] = {
2024 _allowed_units_DUMMY,
2027 const be_execution_unit_t ***ret;
2030 if (is_ia32_irn(irn)) {
2031 ret = get_ia32_exec_units(irn);
2032 } else if (is_be_node(irn)) {
2033 if (be_is_Return(irn)) {
2034 ret = _units_callret;
2035 } else if (be_is_Barrier(irn)) {
2049 * Return the abstract ia32 machine.
2051 static const be_machine_t *ia32_get_machine(const void *self) {
2052 const ia32_isa_t *isa = self;
2057 * Return irp irgs in the desired order.
2059 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2066 static void ia32_mark_remat(const void *self, ir_node *node) {
2068 if (is_ia32_irn(node)) {
2069 set_ia32_is_remat(node);
2074 * Check for Abs or -Abs.
2076 static int psi_is_Abs_or_Nabs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) {
2083 /* must be <, <=, >=, > */
2084 pnc = get_Proj_proj(sel);
2085 if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
2086 pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
2089 l = get_Cmp_left(cmp);
2090 r = get_Cmp_right(cmp);
2092 /* must be x cmp 0 */
2093 if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
2096 if ((!is_Minus(t) || get_Minus_op(t) != f) &&
2097 (!is_Minus(f) || get_Minus_op(f) != t))
2103 * Check for Abs only
2105 static int psi_is_Abs(ir_node *cmp, ir_node *sel, ir_node *t, ir_node *f) {
2112 /* must be <, <=, >=, > */
2113 pnc = get_Proj_proj(sel);
2114 if (pnc != pn_Cmp_Ge && pnc != pn_Cmp_Gt &&
2115 pnc != pn_Cmp_Le && pnc != pn_Cmp_Lt)
2118 l = get_Cmp_left(cmp);
2119 r = get_Cmp_right(cmp);
2121 /* must be x cmp 0 */
2122 if ((l != t && l != f) || !is_Const(r) || !is_Const_null(r))
2125 if ((!is_Minus(t) || get_Minus_op(t) != f) &&
2126 (!is_Minus(f) || get_Minus_op(f) != t))
2129 if (pnc & pn_Cmp_Gt) {
2130 /* x >= 0 ? -x : x is NABS */
2134 /* x < 0 ? x : -x is NABS */
2143 * Allows or disallows the creation of Mux nodes for the given Phi nodes.
2145 * @param sel A selector of a Cond.
2146 * @param phi_list List of Phi nodes about to be converted (linked via get_Phi_next() field)
2147 * @param i First data predecessor involved in if conversion
2148 * @param j Second data predecessor involved in if conversion
2150 * @return 1 if allowed, 0 otherwise
2152 static int ia32_is_mux_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2159 /* we can't handle Muxs with 64bit compares yet */
2161 cmp = get_Proj_pred(sel);
2163 ir_node *left = get_Cmp_left(cmp);
2164 ir_mode *cmp_mode = get_irn_mode(left);
2165 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32) {
2166 /* 64bit Abs IS supported */
2167 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2168 ir_node *t = get_Phi_pred(phi, i);
2169 ir_node *f = get_Phi_pred(phi, j);
2171 if (! psi_is_Abs(cmp, sel, t, f))
2177 /* we do not support nodes without Cmp yet */
2181 /* we do not support nodes without Cmp yet */
2185 pn = get_Proj_proj(sel);
2186 cl = get_Cmp_left(cmp);
2187 cr = get_Cmp_right(cmp);
2189 if (ia32_cg_config.use_cmov) {
2190 if (ia32_cg_config.use_sse2) {
2191 /* check the Phi nodes: no 64bit and no floating point cmov */
2192 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2193 ir_mode *mode = get_irn_mode(phi);
2195 if (mode_is_float(mode)) {
2196 /* check for Min, Max */
2197 ir_node *t = get_Phi_pred(phi, i);
2198 ir_node *f = get_Phi_pred(phi, j);
2200 /* SSE2 supports Min & Max */
2201 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2202 if (cl == t && cr == f) {
2203 /* Mux(a <=/>= b, a, b) => MIN, MAX */
2205 } else if (cl == f && cr == t) {
2206 /* Mux(a <=/>= b, b, a) => MAX, MIN */
2211 } else if (get_mode_size_bits(mode) > 32) {
2217 /* check the Phi nodes: no 64bit and no floating point cmov */
2218 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2219 ir_mode *mode = get_irn_mode(phi);
2221 if (mode_is_float(mode)) {
2222 ir_node *t = get_Phi_pred(phi, i);
2223 ir_node *f = get_Phi_pred(phi, j);
2225 /* always support Mux(!float, C1, C2) */
2226 if (is_Const(t) && is_Const(f) && !mode_is_float(get_irn_mode(cl))) {
2227 switch (be_transformer) {
2228 case TRANSFORMER_DEFAULT:
2229 /* always support Mux(!float, C1, C2) */
2231 #ifdef FIRM_GRGEN_BE
2232 case TRANSFORMER_PBQP:
2233 case TRANSFORMER_RAND:
2234 /* no support for Mux(*, C1, C2) */
2238 panic("invalid transformer");
2241 /* only abs or nabs supported */
2242 if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
2244 } else if (get_mode_size_bits(mode) > 32)
2250 } else { /* No Cmov, only some special cases */
2252 /* Now some supported cases here */
2253 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2254 ir_mode *mode = get_irn_mode(phi);
2257 t = get_Phi_pred(phi, i);
2258 f = get_Phi_pred(phi, j);
2260 if (mode_is_float(mode)) {
2261 /* always support Mux(!float, C1, C2) */
2262 if (is_Const(t) && is_Const(f) &&
2263 !mode_is_float(get_irn_mode(cl))) {
2264 switch (be_transformer) {
2265 case TRANSFORMER_DEFAULT:
2266 /* always support Mux(!float, C1, C2) */
2268 #ifdef FIRM_GRGEN_BE
2269 case TRANSFORMER_PBQP:
2270 case TRANSFORMER_RAND:
2271 /* no support for Mux(*, C1, C2) */
2275 panic("invalid transformer");
2278 /* only abs or nabs supported */
2279 if (! psi_is_Abs_or_Nabs(cmp, sel, t, f))
2281 } else if (get_mode_size_bits(mode) > 32) {
2286 if (is_Const(t) && is_Const(f)) {
2287 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2288 /* always support Mux(x, C1, C2) */
2291 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2293 if (cl == t && cr == f) {
2294 /* Mux(a <=/>= b, a, b) => Min, Max */
2297 if (cl == f && cr == t) {
2298 /* Mux(a <=/>= b, b, a) => Max, Min */
2302 if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2303 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2304 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2305 /* Mux(a >=u b, a - b, 0) unsigned Doz */
2308 if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2309 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2310 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2311 /* Mux(a <=u b, 0, a - b) unsigned Doz */
2314 if (is_Const(cr) && is_Const_null(cr)) {
2315 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2316 /* Mux(a <=/>= 0 ? a : -a) Nabs/Abs */
2318 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2319 /* Mux(a <=/>= 0 ? -a : a) Abs/Nabs */
2326 /* all checks passed */
2332 static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
2337 /* we already added all our simple flags to the flags modifier list in
2338 * init, so this flag we don't know. */
2339 return ASM_CONSTRAINT_FLAG_INVALID;
2342 static int ia32_is_valid_clobber(const void *self, const char *clobber)
2346 return ia32_get_clobber_register(clobber) != NULL;
2350 * Create the trampoline code.
2352 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2354 ir_node *st, *p = trampoline;
2355 ir_mode *mode = get_irn_mode(p);
2358 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
2359 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2360 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2361 st = new_r_Store(block, mem, p, env, 0);
2362 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2363 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2365 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
2366 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2367 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2368 st = new_r_Store(block, mem, p, callee, 0);
2369 mem = new_r_Proj(block, st, mode_M, pn_Store_M);
2370 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2376 * Returns the libFirm configuration parameter for this backend.
2378 static const backend_params *ia32_get_libfirm_params(void) {
2379 static const ir_settings_if_conv_t ifconv = {
2380 4, /* maxdepth, doesn't matter for Mux-conversion */
2381 ia32_is_mux_allowed /* allows or disallows Mux creation for given selector */
2383 static const ir_settings_arch_dep_t ad = {
2384 1, /* also use subs */
2385 4, /* maximum shifts */
2386 31, /* maximum shift amount */
2387 ia32_evaluate_insn, /* evaluate the instruction sequence */
2389 1, /* allow Mulhs */
2390 1, /* allow Mulus */
2391 32, /* Mulh allowed up to 32 bit */
2393 static backend_params p = {
2394 1, /* need dword lowering */
2395 1, /* support inline assembly */
2396 NULL, /* will be set later */
2397 ia32_create_intrinsic_fkt,
2398 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2399 NULL, /* ifconv info will be set below */
2400 NULL, /* float arithmetic mode, will be set below */
2401 12, /* size of trampoline code */
2402 4, /* alignment of trampoline code */
2403 ia32_create_trampoline_fkt,
2404 4 /* alignment of stack parameter */
2407 ia32_setup_cg_config();
2409 /* doesn't really belong here, but this is the earliest place the backend
2411 init_asm_constraints();
2414 p.if_conv_info = &ifconv;
2415 if (! ia32_cg_config.use_sse2)
2416 p.mode_float_arithmetic = mode_E;
2420 static const lc_opt_enum_int_items_t gas_items[] = {
2421 { "elf", GAS_FLAVOUR_ELF },
2422 { "mingw", GAS_FLAVOUR_MINGW },
2423 { "yasm", GAS_FLAVOUR_YASM },
2424 { "macho", GAS_FLAVOUR_MACH_O },
2428 static lc_opt_enum_int_var_t gas_var = {
2429 (int*) &be_gas_flavour, gas_items
2432 #ifdef FIRM_GRGEN_BE
2433 static const lc_opt_enum_int_items_t transformer_items[] = {
2434 { "default", TRANSFORMER_DEFAULT },
2435 { "pbqp", TRANSFORMER_PBQP },
2436 { "random", TRANSFORMER_RAND },
2440 static lc_opt_enum_int_var_t transformer_var = {
2441 (int*)&be_transformer, transformer_items
2445 static const lc_opt_table_entry_t ia32_options[] = {
2446 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2447 #ifdef FIRM_GRGEN_BE
2448 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2450 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2451 &ia32_isa_template.arch_env.stack_alignment),
2455 const arch_isa_if_t ia32_isa_if = {
2458 ia32_handle_intrinsics,
2459 ia32_get_n_reg_class,
2461 ia32_get_reg_class_for_mode,
2463 ia32_get_code_generator_if,
2464 ia32_get_list_sched_selector,
2465 ia32_get_ilp_sched_selector,
2466 ia32_get_reg_class_alignment,
2467 ia32_get_libfirm_params,
2468 ia32_get_allowed_execution_units,
2472 ia32_parse_asm_constraint,
2473 ia32_is_valid_clobber
2476 void be_init_arch_ia32(void)
2478 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2479 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2481 lc_opt_add_table(ia32_grp, ia32_options);
2482 be_register_isa_if("ia32", &ia32_isa_if);
2484 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2486 ia32_init_emitter();
2488 ia32_init_optimize();
2489 ia32_init_transform();
2491 ia32_init_architecture();
2494 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);