2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
31 #include "lc_opts_enum.h"
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
46 #include "irdump_grgen.h"
53 #include "iroptimize.h"
54 #include "instrument.h"
57 #include "../beirg_t.h"
58 #include "../benode_t.h"
59 #include "../belower.h"
60 #include "../besched_t.h"
63 #include "../beirgmod.h"
64 #include "../be_dbgout.h"
65 #include "../beblocksched.h"
66 #include "../bemachine.h"
67 #include "../beilpsched.h"
68 #include "../bespillslots.h"
69 #include "../bemodule.h"
70 #include "../begnuas.h"
71 #include "../bestate.h"
72 #include "../beflags.h"
74 #include "bearch_ia32_t.h"
76 #include "ia32_new_nodes.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "gen_ia32_machine.h"
79 #include "ia32_transform.h"
80 #include "ia32_emitter.h"
81 #include "ia32_map_regs.h"
82 #include "ia32_optimize.h"
84 #include "ia32_dbg_stat.h"
85 #include "ia32_finish.h"
86 #include "ia32_util.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
94 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
97 static set *cur_reg_set = NULL;
99 ir_mode *mode_fpcw = NULL;
100 ia32_code_gen_t *ia32_current_cg = NULL;
103 * The environment for the intrinsic mapping.
105 static ia32_intrinsic_env_t intrinsic_env = {
107 NULL, /* the irg, these entities belong to */
108 NULL, /* entity for first div operand (move into FPU) */
109 NULL, /* entity for second div operand (move into FPU) */
110 NULL, /* entity for converts ll -> d */
111 NULL, /* entity for converts d -> ll */
112 NULL, /* entity for __divdi3 library call */
113 NULL, /* entity for __moddi3 library call */
114 NULL, /* entity for __udivdi3 library call */
115 NULL, /* entity for __umoddi3 library call */
116 NULL, /* bias value for conversion from float to unsigned 64 */
120 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
122 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
123 create_const_node_func func,
124 const arch_register_t* reg)
126 ir_node *block, *res;
131 block = get_irg_start_block(cg->irg);
132 res = func(NULL, cg->irg, block);
133 arch_set_irn_register(cg->arch_env, res, reg);
136 add_irn_dep(get_irg_end(cg->irg), res);
137 /* add_irn_dep(get_irg_start(cg->irg), res); */
142 /* Creates the unique per irg GP NoReg node. */
143 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
144 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
145 &ia32_gp_regs[REG_GP_NOREG]);
148 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
149 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
150 &ia32_vfp_regs[REG_VFP_NOREG]);
153 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
154 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
155 &ia32_xmm_regs[REG_XMM_NOREG]);
158 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
159 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
160 &ia32_gp_regs[REG_GP_UKNWN]);
163 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
164 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
165 &ia32_vfp_regs[REG_VFP_UKNWN]);
168 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
169 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
170 &ia32_xmm_regs[REG_XMM_UKNWN]);
173 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
174 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
175 &ia32_fp_cw_regs[REG_FPCW]);
180 * Returns the admissible noreg register node for input register pos of node irn.
182 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
183 const arch_register_req_t *req;
185 req = arch_get_register_req(cg->arch_env, irn, pos);
186 assert(req != NULL && "Missing register requirements");
187 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
188 return ia32_new_NoReg_gp(cg);
190 if (ia32_cg_config.use_sse2) {
191 return ia32_new_NoReg_xmm(cg);
193 return ia32_new_NoReg_vfp(cg);
197 /**************************************************
200 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
201 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
202 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
203 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
206 **************************************************/
209 * Return register requirements for an ia32 node.
210 * If the node returns a tuple (mode_T) then the proj's
211 * will be asked for this information.
213 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
216 ir_mode *mode = get_irn_mode(node);
219 if (mode == mode_X || is_Block(node)) {
220 return arch_no_register_req;
223 if (mode == mode_T && pos < 0) {
224 return arch_no_register_req;
227 node_pos = pos == -1 ? 0 : pos;
229 if (mode == mode_M || pos >= 0) {
230 return arch_no_register_req;
233 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
234 node = skip_Proj_const(node);
237 if (is_ia32_irn(node)) {
238 const arch_register_req_t *req;
240 req = get_ia32_in_req(node, pos);
242 req = get_ia32_out_req(node, node_pos);
249 /* unknowns should be transformed already */
250 assert(!is_Unknown(node));
251 return arch_no_register_req;
254 static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
258 if (get_irn_mode(irn) == mode_X) {
263 pos = get_Proj_proj(irn);
264 irn = skip_Proj(irn);
267 if (is_ia32_irn(irn)) {
268 const arch_register_t **slots;
270 slots = get_ia32_slots(irn);
273 ia32_set_firm_reg(irn, reg, cur_reg_set);
277 static const arch_register_t *ia32_get_irn_reg(const ir_node *irn)
280 const arch_register_t *reg = NULL;
284 if (get_irn_mode(irn) == mode_X) {
288 pos = get_Proj_proj(irn);
289 irn = skip_Proj_const(irn);
292 if (is_ia32_irn(irn)) {
293 const arch_register_t **slots;
294 slots = get_ia32_slots(irn);
295 assert(pos < get_ia32_n_res(irn));
298 reg = ia32_get_firm_reg(irn, cur_reg_set);
304 static arch_irn_class_t ia32_classify(const ir_node *irn) {
305 arch_irn_class_t classification = arch_irn_class_normal;
307 irn = skip_Proj_const(irn);
310 classification |= arch_irn_class_branch;
312 if (! is_ia32_irn(irn))
313 return classification & ~arch_irn_class_normal;
316 classification |= arch_irn_class_load;
319 classification |= arch_irn_class_store;
321 if (is_ia32_need_stackent(irn))
322 classification |= arch_irn_class_reload;
324 return classification;
327 static arch_irn_flags_t ia32_get_flags(const ir_node *irn) {
328 arch_irn_flags_t flags = arch_irn_flags_none;
331 return arch_irn_flags_ignore;
333 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
334 ir_node *pred = get_Proj_pred(irn);
336 if(is_ia32_irn(pred)) {
337 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
343 if (is_ia32_irn(irn)) {
344 flags |= get_ia32_flags(irn);
351 * The IA32 ABI callback object.
354 be_abi_call_flags_bits_t flags; /**< The call flags. */
355 const arch_env_t *aenv; /**< The architecture environment. */
356 ir_graph *irg; /**< The associated graph. */
359 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
360 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
363 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
364 set_ia32_frame_ent(irn, ent);
367 static void ia32_set_frame_offset(ir_node *irn, int bias)
369 if (get_ia32_frame_ent(irn) == NULL)
372 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
373 ia32_code_gen_t *cg = ia32_current_cg;
374 int omit_fp = be_abi_omit_fp(cg->birg->abi);
376 /* Pop nodes modify the stack pointer before calculating the
377 * destination address, so fix this here
382 add_ia32_am_offs_int(irn, bias);
385 static int ia32_get_sp_bias(const ir_node *node)
387 if (is_ia32_Push(node))
390 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
397 * Put all registers which are saved by the prologue/epilogue in a set.
399 * @param self The callback object.
400 * @param s The result set.
402 static void ia32_abi_dont_save_regs(void *self, pset *s)
404 ia32_abi_env_t *env = self;
405 if(env->flags.try_omit_fp)
406 pset_insert_ptr(s, env->aenv->bp);
410 * Generate the routine prologue.
412 * @param self The callback object.
413 * @param mem A pointer to the mem node. Update this if you define new memory.
414 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
416 * @return The register which shall be used as a stack frame base.
418 * All nodes which define registers in @p reg_map must keep @p reg_map current.
420 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
422 ia32_abi_env_t *env = self;
423 ia32_code_gen_t *cg = ia32_current_cg;
424 const arch_env_t *arch_env = env->aenv;
426 if (! env->flags.try_omit_fp) {
427 ir_node *bl = get_irg_start_block(env->irg);
428 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
429 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
430 ir_node *noreg = ia32_new_NoReg_gp(cg);
433 /* ALL nodes representing bp must be set to ignore. */
434 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
437 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
438 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
439 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
441 /* the push must have SP out register */
442 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
443 set_ia32_flags(push, arch_irn_flags_ignore);
445 /* move esp to ebp */
446 curr_bp = be_new_Copy(arch_env->bp->reg_class, env->irg, bl, curr_sp);
447 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
448 arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
449 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
451 /* beware: the copy must be done before any other sp use */
452 curr_sp = be_new_CopyKeep_single(env->aenv->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
453 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp);
454 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
455 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
457 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
458 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
467 * Generate the routine epilogue.
468 * @param self The callback object.
469 * @param bl The block for the epilog
470 * @param mem A pointer to the mem node. Update this if you define new memory.
471 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
472 * @return The register which shall be used as a stack frame base.
474 * All nodes which define registers in @p reg_map must keep @p reg_map current.
476 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
478 ia32_abi_env_t *env = self;
479 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->aenv->sp);
480 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->aenv->bp);
481 const arch_env_t *arch_env = env->aenv;
483 if (env->flags.try_omit_fp) {
484 /* simply remove the stack frame here */
485 curr_sp = be_new_IncSP(env->aenv->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
486 add_irn_dep(curr_sp, *mem);
488 ir_mode *mode_bp = env->aenv->bp->reg_class->mode;
489 ir_graph *irg = current_ir_graph;
491 if (ia32_cg_config.use_leave) {
495 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
496 set_ia32_flags(leave, arch_irn_flags_ignore);
497 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
498 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
502 /* the old SP is not needed anymore (kill the proj) */
503 assert(is_Proj(curr_sp));
504 be_kill_node(curr_sp);
506 /* copy ebp to esp */
507 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
508 arch_set_irn_register(arch_env, curr_sp, env->aenv->sp);
509 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
512 pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
513 set_ia32_flags(pop, arch_irn_flags_ignore);
514 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
515 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
517 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
519 arch_set_irn_register(arch_env, curr_sp, env->aenv->sp);
520 arch_set_irn_register(arch_env, curr_bp, env->aenv->bp);
523 be_abi_reg_map_set(reg_map, env->aenv->sp, curr_sp);
524 be_abi_reg_map_set(reg_map, env->aenv->bp, curr_bp);
528 * Initialize the callback object.
529 * @param call The call object.
530 * @param aenv The architecture environment.
531 * @param irg The graph with the method.
532 * @return Some pointer. This pointer is passed to all other callback functions as self object.
534 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
536 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
537 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
538 env->flags = fl.bits;
545 * Destroy the callback object.
546 * @param self The callback object.
548 static void ia32_abi_done(void *self) {
553 * Produces the type which sits between the stack args and the locals on the stack.
554 * it will contain the return address and space to store the old base pointer.
555 * @return The Firm type modeling the ABI between type.
557 static ir_type *ia32_abi_get_between_type(void *self)
559 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
560 static ir_type *omit_fp_between_type = NULL;
561 static ir_type *between_type = NULL;
563 ia32_abi_env_t *env = self;
565 if (! between_type) {
566 ir_entity *old_bp_ent;
567 ir_entity *ret_addr_ent;
568 ir_entity *omit_fp_ret_addr_ent;
570 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
571 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
573 between_type = new_type_struct(IDENT("ia32_between_type"));
574 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
575 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
577 set_entity_offset(old_bp_ent, 0);
578 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
579 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
580 set_type_state(between_type, layout_fixed);
582 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
583 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
585 set_entity_offset(omit_fp_ret_addr_ent, 0);
586 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
587 set_type_state(omit_fp_between_type, layout_fixed);
590 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
595 * Get the estimated cycle count for @p irn.
597 * @param self The this pointer.
598 * @param irn The node.
600 * @return The estimated cycle count for this operation
602 static int ia32_get_op_estimated_cost(const ir_node *irn)
605 ia32_op_type_t op_tp;
609 if (!is_ia32_irn(irn))
612 assert(is_ia32_irn(irn));
614 cost = get_ia32_latency(irn);
615 op_tp = get_ia32_op_type(irn);
617 if (is_ia32_CopyB(irn)) {
620 else if (is_ia32_CopyB_i(irn)) {
621 int size = get_ia32_copyb_size(irn);
622 cost = 20 + (int)ceil((4/3) * size);
624 /* in case of address mode operations add additional cycles */
625 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
627 In case of stack access and access to fixed addresses add 5 cycles
628 (we assume they are in cache), other memory operations cost 20
631 if(is_ia32_use_frame(irn) ||
632 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
633 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
644 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
646 * @param irn The original operation
647 * @param i Index of the argument we want the inverse operation to yield
648 * @param inverse struct to be filled with the resulting inverse op
649 * @param obstack The obstack to use for allocation of the returned nodes array
650 * @return The inverse operation or NULL if operation invertible
652 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
656 ir_node *block, *noreg, *nomem;
659 /* we cannot invert non-ia32 irns */
660 if (! is_ia32_irn(irn))
663 /* operand must always be a real operand (not base, index or mem) */
664 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
667 /* we don't invert address mode operations */
668 if (get_ia32_op_type(irn) != ia32_Normal)
671 /* TODO: adjust for new immediates... */
672 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
676 irg = get_irn_irg(irn);
677 block = get_nodes_block(irn);
678 mode = get_irn_mode(irn);
679 irn_mode = get_irn_mode(irn);
680 noreg = get_irn_n(irn, 0);
681 nomem = new_r_NoMem(irg);
682 dbg = get_irn_dbg_info(irn);
684 /* initialize structure */
685 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
689 switch (get_ia32_irn_opcode(irn)) {
692 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
693 /* we have an add with a const here */
694 /* invers == add with negated const */
695 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
697 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
698 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
699 set_ia32_commutative(inverse->nodes[0]);
701 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
702 /* we have an add with a symconst here */
703 /* invers == sub with const */
704 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
706 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
709 /* normal add: inverse == sub */
710 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
717 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
718 /* we have a sub with a const/symconst here */
719 /* invers == add with this const */
720 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
721 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
722 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
726 if (i == n_ia32_binary_left) {
727 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
730 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
738 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
739 /* xor with const: inverse = xor */
740 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
741 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
742 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
746 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
752 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
757 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
762 /* inverse operation not supported */
769 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
771 if(mode_is_float(mode))
778 * Get the mode that should be used for spilling value node
780 static ir_mode *get_spill_mode(const ir_node *node)
782 ir_mode *mode = get_irn_mode(node);
783 return get_spill_mode_mode(mode);
787 * Checks whether an addressmode reload for a node with mode mode is compatible
788 * with a spillslot of mode spill_mode
790 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
792 if(mode_is_float(mode)) {
793 return mode == spillmode;
800 * Check if irn can load its operand at position i from memory (source addressmode).
801 * @param self Pointer to irn ops itself
802 * @param irn The irn to be checked
803 * @param i The operands position
804 * @return Non-Zero if operand can be loaded
806 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) {
807 ir_node *op = get_irn_n(irn, i);
808 const ir_mode *mode = get_irn_mode(op);
809 const ir_mode *spillmode = get_spill_mode(op);
812 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
813 ! is_ia32_irn(irn) || /* must be an ia32 irn */
814 get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
815 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
816 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
817 ! ia32_is_spillmode_compatible(mode, spillmode) ||
818 is_ia32_use_frame(irn)) /* must not already use frame */
821 if (i == n_ia32_binary_left) {
822 const arch_register_req_t *req;
823 if(!is_ia32_commutative(irn))
825 /* we can't swap left/right for limited registers
826 * (As this (currently) breaks constraint handling copies)
828 req = get_ia32_in_req(irn, n_ia32_binary_left);
829 if (req->type & arch_register_req_type_limited) {
837 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
840 ia32_code_gen_t *cg = ia32_current_cg;
842 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
844 if (i == n_ia32_binary_left) {
845 ia32_swap_left_right(irn);
848 set_ia32_op_type(irn, ia32_AddrModeS);
849 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
850 set_ia32_use_frame(irn);
851 set_ia32_need_stackent(irn);
853 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
854 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
855 set_irn_n(irn, n_ia32_mem, spill);
857 /* immediates are only allowed on the right side */
858 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
859 ia32_swap_left_right(irn);
863 static const be_abi_callbacks_t ia32_abi_callbacks = {
866 ia32_abi_get_between_type,
867 ia32_abi_dont_save_regs,
872 /* fill register allocator interface */
874 static const arch_irn_ops_t ia32_irn_ops = {
875 ia32_get_irn_reg_req,
880 ia32_get_frame_entity,
881 ia32_set_frame_entity,
882 ia32_set_frame_offset,
885 ia32_get_op_estimated_cost,
886 ia32_possible_memory_operand,
887 ia32_perform_memory_operand,
890 /**************************************************
893 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
894 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
895 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
896 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
899 **************************************************/
901 static ir_entity *mcount = NULL;
903 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
905 static void ia32_before_abi(void *self) {
906 lower_mode_b_config_t lower_mode_b_config = {
907 mode_Iu, /* lowered mode */
908 mode_Bu, /* prefered mode for set */
909 0, /* don't lower direct compares */
911 ia32_code_gen_t *cg = self;
913 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
915 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
917 if (mcount == NULL) {
918 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
919 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
920 /* FIXME: enter the right ld_ident here */
921 set_entity_ld_ident(mcount, get_entity_ident(mcount));
922 set_entity_visibility(mcount, visibility_external_allocated);
924 instrument_initcall(cg->irg, mcount);
929 * Transforms the standard firm graph into
932 static void ia32_prepare_graph(void *self) {
933 ia32_code_gen_t *cg = self;
935 /* do local optimisations */
936 optimize_graph_df(cg->irg);
938 /* TODO: we often have dead code reachable through out-edges here. So for
939 * now we rebuild edges (as we need correct user count for code selection)
942 edges_deactivate(cg->irg);
943 edges_activate(cg->irg);
947 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
950 /* transform nodes into assembler instructions by PBQP magic */
951 ia32_transform_graph_by_pbqp(cg);
955 be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched);
957 /* transform remaining nodes into assembler instructions */
958 ia32_transform_graph(cg);
960 /* do local optimisations (mainly CSE) */
961 optimize_graph_df(cg->irg);
964 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
966 /* optimize address mode */
967 ia32_optimize_graph(cg);
970 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
972 /* do code placement, to optimize the position of constants */
976 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
980 * Dummy functions for hooks we don't need but which must be filled.
982 static void ia32_before_sched(void *self) {
986 static void turn_back_am(ir_node *node)
988 ir_graph *irg = current_ir_graph;
989 dbg_info *dbgi = get_irn_dbg_info(node);
990 ir_node *block = get_nodes_block(node);
991 ir_node *base = get_irn_n(node, n_ia32_base);
992 ir_node *index = get_irn_n(node, n_ia32_index);
993 ir_node *mem = get_irn_n(node, n_ia32_mem);
994 ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
998 const ir_edge_t *edge;
1000 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1001 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1003 ia32_copy_am_attrs(load, node);
1004 set_irn_n(node, n_ia32_mem, new_NoMem());
1006 switch (get_ia32_am_arity(node)) {
1008 set_irn_n(node, n_ia32_unary_op, load_res);
1011 case ia32_am_binary:
1012 if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
1013 assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
1014 is_ia32_Test(node) || is_ia32_Test8Bit(node));
1015 set_irn_n(node, n_ia32_binary_left, load_res);
1017 set_irn_n(node, n_ia32_binary_right, load_res);
1021 case ia32_am_ternary:
1022 set_irn_n(node, n_ia32_binary_right, load_res);
1027 set_irn_n(node, n_ia32_base, noreg);
1028 set_irn_n(node, n_ia32_index, noreg);
1029 set_ia32_am_offs_int(node, 0);
1030 set_ia32_am_sc(node, NULL);
1031 set_ia32_am_scale(node, 0);
1032 clear_ia32_am_sc_sign(node);
1034 /* rewire mem-proj */
1035 if (get_irn_mode(node) == mode_T) {
1037 foreach_out_edge(node, edge) {
1038 ir_node *out = get_edge_src_irn(edge);
1039 if(get_Proj_proj(out) == pn_ia32_mem) {
1045 if(mem_proj != NULL) {
1046 set_Proj_pred(mem_proj, load);
1047 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1051 set_ia32_op_type(node, ia32_Normal);
1052 if (sched_is_scheduled(node))
1053 sched_add_before(node, load);
1056 static ir_node *flags_remat(ir_node *node, ir_node *after)
1058 /* we should turn back source address mode when rematerializing nodes */
1059 ia32_op_type_t type;
1063 if (is_Block(after)) {
1066 block = get_nodes_block(after);
1069 type = get_ia32_op_type(node);
1071 case ia32_AddrModeS: turn_back_am(node); break;
1073 case ia32_AddrModeD:
1074 /* TODO implement this later... */
1075 panic("found DestAM with flag user %+F this should not happen", node);
1078 default: assert(type == ia32_Normal); break;
1081 copy = exact_copy(node);
1082 set_nodes_block(copy, block);
1083 sched_add_after(after, copy);
1089 * Called before the register allocator.
1090 * Calculate a block schedule here. We need it for the x87
1091 * simulator and the emitter.
1093 static void ia32_before_ra(void *self) {
1094 ia32_code_gen_t *cg = self;
1096 /* setup fpu rounding modes */
1097 ia32_setup_fpu_mode(cg);
1100 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1103 ia32_add_missing_keeps(cg);
1108 * Transforms a be_Reload into a ia32 Load.
1110 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1111 ir_graph *irg = get_irn_irg(node);
1112 dbg_info *dbg = get_irn_dbg_info(node);
1113 ir_node *block = get_nodes_block(node);
1114 ir_entity *ent = be_get_frame_entity(node);
1115 ir_mode *mode = get_irn_mode(node);
1116 ir_mode *spillmode = get_spill_mode(node);
1117 ir_node *noreg = ia32_new_NoReg_gp(cg);
1118 ir_node *sched_point = NULL;
1119 ir_node *ptr = get_irg_frame(irg);
1120 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1121 ir_node *new_op, *proj;
1122 const arch_register_t *reg;
1124 if (sched_is_scheduled(node)) {
1125 sched_point = sched_prev(node);
1128 if (mode_is_float(spillmode)) {
1129 if (ia32_cg_config.use_sse2)
1130 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1132 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1134 else if (get_mode_size_bits(spillmode) == 128) {
1135 /* Reload 128 bit SSE registers */
1136 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1139 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1141 set_ia32_op_type(new_op, ia32_AddrModeS);
1142 set_ia32_ls_mode(new_op, spillmode);
1143 set_ia32_frame_ent(new_op, ent);
1144 set_ia32_use_frame(new_op);
1146 DBG_OPT_RELOAD2LD(node, new_op);
1148 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1151 sched_add_after(sched_point, new_op);
1155 /* copy the register from the old node to the new Load */
1156 reg = arch_get_irn_register(cg->arch_env, node);
1157 arch_set_irn_register(cg->arch_env, new_op, reg);
1159 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1161 exchange(node, proj);
1165 * Transforms a be_Spill node into a ia32 Store.
1167 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1168 ir_graph *irg = get_irn_irg(node);
1169 dbg_info *dbg = get_irn_dbg_info(node);
1170 ir_node *block = get_nodes_block(node);
1171 ir_entity *ent = be_get_frame_entity(node);
1172 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1173 ir_mode *mode = get_spill_mode(spillval);
1174 ir_node *noreg = ia32_new_NoReg_gp(cg);
1175 ir_node *nomem = new_rd_NoMem(irg);
1176 ir_node *ptr = get_irg_frame(irg);
1177 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1179 ir_node *sched_point = NULL;
1181 if (sched_is_scheduled(node)) {
1182 sched_point = sched_prev(node);
1185 /* No need to spill unknown values... */
1186 if(is_ia32_Unknown_GP(val) ||
1187 is_ia32_Unknown_VFP(val) ||
1188 is_ia32_Unknown_XMM(val)) {
1193 exchange(node, store);
1197 if (mode_is_float(mode)) {
1198 if (ia32_cg_config.use_sse2)
1199 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1201 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1202 } else if (get_mode_size_bits(mode) == 128) {
1203 /* Spill 128 bit SSE registers */
1204 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1205 } else if (get_mode_size_bits(mode) == 8) {
1206 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1208 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1211 set_ia32_op_type(store, ia32_AddrModeD);
1212 set_ia32_ls_mode(store, mode);
1213 set_ia32_frame_ent(store, ent);
1214 set_ia32_use_frame(store);
1215 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1216 DBG_OPT_SPILL2ST(node, store);
1219 sched_add_after(sched_point, store);
1223 exchange(node, store);
1226 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1227 ir_graph *irg = get_irn_irg(node);
1228 dbg_info *dbg = get_irn_dbg_info(node);
1229 ir_node *block = get_nodes_block(node);
1230 ir_node *noreg = ia32_new_NoReg_gp(cg);
1231 ir_node *frame = get_irg_frame(irg);
1233 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
1235 set_ia32_frame_ent(push, ent);
1236 set_ia32_use_frame(push);
1237 set_ia32_op_type(push, ia32_AddrModeS);
1238 set_ia32_ls_mode(push, mode_Is);
1240 sched_add_before(schedpoint, push);
1244 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1245 ir_graph *irg = get_irn_irg(node);
1246 dbg_info *dbg = get_irn_dbg_info(node);
1247 ir_node *block = get_nodes_block(node);
1248 ir_node *noreg = ia32_new_NoReg_gp(cg);
1249 ir_node *frame = get_irg_frame(irg);
1251 ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1253 set_ia32_frame_ent(pop, ent);
1254 set_ia32_use_frame(pop);
1255 set_ia32_op_type(pop, ia32_AddrModeD);
1256 set_ia32_ls_mode(pop, mode_Is);
1258 sched_add_before(schedpoint, pop);
1263 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1264 ir_graph *irg = get_irn_irg(node);
1265 dbg_info *dbg = get_irn_dbg_info(node);
1266 ir_node *block = get_nodes_block(node);
1267 ir_mode *spmode = mode_Iu;
1268 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1271 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1272 arch_set_irn_register(cg->arch_env, sp, spreg);
1278 * Transform MemPerm, currently we do this the ugly way and produce
1279 * push/pop into/from memory cascades. This is possible without using
1282 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1283 ir_graph *irg = get_irn_irg(node);
1284 ir_node *block = get_nodes_block(node);
1288 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1289 const ir_edge_t *edge;
1290 const ir_edge_t *next;
1293 arity = be_get_MemPerm_entity_arity(node);
1294 pops = alloca(arity * sizeof(pops[0]));
1297 for(i = 0; i < arity; ++i) {
1298 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1299 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1300 ir_type *enttype = get_entity_type(inent);
1301 unsigned entsize = get_type_size_bytes(enttype);
1302 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1303 ir_node *mem = get_irn_n(node, i + 1);
1306 /* work around cases where entities have different sizes */
1307 if(entsize2 < entsize)
1309 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1311 push = create_push(cg, node, node, sp, mem, inent);
1312 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1314 /* add another push after the first one */
1315 push = create_push(cg, node, node, sp, mem, inent);
1316 add_ia32_am_offs_int(push, 4);
1317 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1320 set_irn_n(node, i, new_Bad());
1324 for(i = arity - 1; i >= 0; --i) {
1325 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1326 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1327 ir_type *enttype = get_entity_type(outent);
1328 unsigned entsize = get_type_size_bytes(enttype);
1329 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1332 /* work around cases where entities have different sizes */
1333 if(entsize2 < entsize)
1335 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1337 pop = create_pop(cg, node, node, sp, outent);
1338 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1340 add_ia32_am_offs_int(pop, 4);
1342 /* add another pop after the first one */
1343 pop = create_pop(cg, node, node, sp, outent);
1344 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1351 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1352 sched_add_before(node, keep);
1354 /* exchange memprojs */
1355 foreach_out_edge_safe(node, edge, next) {
1356 ir_node *proj = get_edge_src_irn(edge);
1357 int p = get_Proj_proj(proj);
1361 set_Proj_pred(proj, pops[p]);
1362 set_Proj_proj(proj, pn_ia32_Pop_M);
1365 /* remove memperm */
1366 arity = get_irn_arity(node);
1367 for(i = 0; i < arity; ++i) {
1368 set_irn_n(node, i, new_Bad());
1374 * Block-Walker: Calls the transform functions Spill and Reload.
1376 static void ia32_after_ra_walker(ir_node *block, void *env) {
1377 ir_node *node, *prev;
1378 ia32_code_gen_t *cg = env;
1380 /* beware: the schedule is changed here */
1381 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1382 prev = sched_prev(node);
1384 if (be_is_Reload(node)) {
1385 transform_to_Load(cg, node);
1386 } else if (be_is_Spill(node)) {
1387 transform_to_Store(cg, node);
1388 } else if (be_is_MemPerm(node)) {
1389 transform_MemPerm(cg, node);
1395 * Collects nodes that need frame entities assigned.
1397 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1399 be_fec_env_t *env = data;
1401 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1402 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1403 int align = get_mode_size_bytes(mode);
1404 be_node_needs_frame_entity(env, node, mode, align);
1405 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1406 && is_ia32_use_frame(node)) {
1407 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1408 const ir_mode *mode = get_ia32_ls_mode(node);
1409 const ia32_attr_t *attr = get_ia32_attr_const(node);
1410 int align = get_mode_size_bytes(mode);
1412 if(attr->data.need_64bit_stackent) {
1415 if(attr->data.need_32bit_stackent) {
1418 be_node_needs_frame_entity(env, node, mode, align);
1419 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1420 || is_ia32_vfld(node)) {
1421 const ir_mode *mode = get_ia32_ls_mode(node);
1423 be_node_needs_frame_entity(env, node, mode, align);
1424 } else if(is_ia32_FldCW(node)) {
1425 /* although 2 byte would be enough 4 byte performs best */
1426 const ir_mode *mode = mode_Iu;
1428 be_node_needs_frame_entity(env, node, mode, align);
1431 assert(is_ia32_St(node) ||
1432 is_ia32_xStoreSimple(node) ||
1433 is_ia32_vfst(node) ||
1434 is_ia32_vfist(node) ||
1435 is_ia32_vfisttp(node) ||
1436 is_ia32_FnstCW(node));
1443 * We transform Spill and Reload here. This needs to be done before
1444 * stack biasing otherwise we would miss the corrected offset for these nodes.
1446 static void ia32_after_ra(void *self) {
1447 ia32_code_gen_t *cg = self;
1448 ir_graph *irg = cg->irg;
1449 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1451 /* create and coalesce frame entities */
1452 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1453 be_assign_entities(fec_env);
1454 be_free_frame_entity_coalescer(fec_env);
1456 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1460 * Last touchups for the graph before emit: x87 simulation to replace the
1461 * virtual with real x87 instructions, creating a block schedule and peephole
1464 static void ia32_finish(void *self) {
1465 ia32_code_gen_t *cg = self;
1466 ir_graph *irg = cg->irg;
1468 ia32_finish_irg(irg, cg);
1470 /* we might have to rewrite x87 virtual registers */
1471 if (cg->do_x87_sim) {
1472 x87_simulate_graph(cg->arch_env, cg->birg);
1475 /* do peephole optimisations */
1476 ia32_peephole_optimization(cg);
1478 /* create block schedule, this also removes empty blocks which might
1479 * produce critical edges */
1480 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1484 * Emits the code, closes the output file and frees
1485 * the code generator interface.
1487 static void ia32_codegen(void *self) {
1488 ia32_code_gen_t *cg = self;
1489 ir_graph *irg = cg->irg;
1491 ia32_gen_routine(cg, irg);
1495 /* remove it from the isa */
1498 assert(ia32_current_cg == cg);
1499 ia32_current_cg = NULL;
1501 /* de-allocate code generator */
1502 del_set(cg->reg_set);
1507 * Returns the node representing the PIC base.
1509 static ir_node *ia32_get_pic_base(void *self) {
1511 ia32_code_gen_t *cg = self;
1512 ir_node *get_eip = cg->get_eip;
1513 if (get_eip != NULL)
1516 block = get_irg_start_block(cg->irg);
1517 get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
1518 cg->get_eip = get_eip;
1520 add_irn_dep(get_eip, get_irg_frame(cg->irg));
1525 static void *ia32_cg_init(be_irg_t *birg);
1527 static const arch_code_generator_if_t ia32_code_gen_if = {
1529 ia32_get_pic_base, /* return node used as base in pic code addresses */
1530 ia32_before_abi, /* before abi introduce hook */
1533 ia32_before_sched, /* before scheduling hook */
1534 ia32_before_ra, /* before register allocation hook */
1535 ia32_after_ra, /* after register allocation hook */
1536 ia32_finish, /* called before codegen */
1537 ia32_codegen /* emit && done */
1541 * Initializes a IA32 code generator.
1543 static void *ia32_cg_init(be_irg_t *birg) {
1544 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1545 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1547 cg->impl = &ia32_code_gen_if;
1548 cg->irg = birg->irg;
1549 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1551 cg->arch_env = birg->main_env->arch_env;
1553 cg->blk_sched = NULL;
1554 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1555 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1558 /* Linux gprof implementation needs base pointer */
1559 birg->main_env->options->omit_fp = 0;
1566 if (isa->name_obst) {
1567 obstack_free(isa->name_obst, NULL);
1568 obstack_init(isa->name_obst);
1572 cur_reg_set = cg->reg_set;
1574 assert(ia32_current_cg == NULL);
1575 ia32_current_cg = cg;
1577 return (arch_code_generator_t *)cg;
1582 /*****************************************************************
1583 * ____ _ _ _____ _____
1584 * | _ \ | | | | |_ _|/ ____| /\
1585 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1586 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1587 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1588 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1590 *****************************************************************/
1593 * Set output modes for GCC
1595 static const tarval_mode_info mo_integer = {
1602 * set the tarval output mode of all integer modes to decimal
1604 static void set_tarval_output_modes(void)
1608 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1609 ir_mode *mode = get_irp_mode(i);
1611 if (mode_is_int(mode))
1612 set_tarval_mode_output_option(mode, &mo_integer);
1616 const arch_isa_if_t ia32_isa_if;
1619 * The template that generates a new ISA object.
1620 * Note that this template can be changed by command line
1623 static ia32_isa_t ia32_isa_template = {
1625 &ia32_isa_if, /* isa interface implementation */
1626 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1627 &ia32_gp_regs[REG_EBP], /* base pointer register */
1628 -1, /* stack direction */
1629 16, /* stack alignment */
1630 NULL, /* main environment */
1631 7, /* costs for a spill instruction */
1632 5, /* costs for a reload instruction */
1634 NULL, /* 16bit register names */
1635 NULL, /* 8bit register names */
1636 NULL, /* 8bit register names high */
1639 NULL, /* current code generator */
1640 NULL, /* abstract machine */
1642 NULL, /* name obstack */
1647 * Initializes the backend ISA.
1649 static arch_env_t *ia32_init(FILE *file_handle) {
1650 static int inited = 0;
1657 set_tarval_output_modes();
1659 isa = xmalloc(sizeof(*isa));
1660 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1662 if(mode_fpcw == NULL) {
1663 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1666 ia32_register_init();
1667 ia32_create_opcodes(&ia32_irn_ops);
1669 be_emit_init(file_handle);
1670 isa->regs_16bit = pmap_create();
1671 isa->regs_8bit = pmap_create();
1672 isa->regs_8bit_high = pmap_create();
1673 isa->types = pmap_create();
1674 isa->tv_ent = pmap_create();
1675 isa->cpu = ia32_init_machine_description();
1677 ia32_build_16bit_reg_map(isa->regs_16bit);
1678 ia32_build_8bit_reg_map(isa->regs_8bit);
1679 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1682 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1683 obstack_init(isa->name_obst);
1686 /* enter the ISA object into the intrinsic environment */
1687 intrinsic_env.isa = isa;
1688 ia32_handle_intrinsics();
1690 /* needed for the debug support */
1691 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1692 be_emit_cstring(".Ltext0:\n");
1693 be_emit_write_line();
1695 /* we mark referenced global entities, so we can only emit those which
1696 * are actually referenced. (Note: you mustn't use the type visited flag
1697 * elsewhere in the backend)
1699 inc_master_type_visited();
1701 return &isa->arch_env;
1707 * Closes the output file and frees the ISA structure.
1709 static void ia32_done(void *self) {
1710 ia32_isa_t *isa = self;
1712 /* emit now all global declarations */
1713 be_gas_emit_decls(isa->arch_env.main_env, 1);
1715 pmap_destroy(isa->regs_16bit);
1716 pmap_destroy(isa->regs_8bit);
1717 pmap_destroy(isa->regs_8bit_high);
1718 pmap_destroy(isa->tv_ent);
1719 pmap_destroy(isa->types);
1722 obstack_free(isa->name_obst, NULL);
1732 * Return the number of register classes for this architecture.
1733 * We report always these:
1734 * - the general purpose registers
1735 * - the SSE floating point register set
1736 * - the virtual floating point registers
1737 * - the SSE vector register set
1739 static unsigned ia32_get_n_reg_class(const void *self) {
1745 * Return the register class for index i.
1747 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1751 assert(i < N_CLASSES);
1752 return &ia32_reg_classes[i];
1756 * Get the register class which shall be used to store a value of a given mode.
1757 * @param self The this pointer.
1758 * @param mode The mode in question.
1759 * @return A register class which can hold values of the given mode.
1761 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1762 const ir_mode *mode)
1766 if (mode_is_float(mode)) {
1767 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1770 return &ia32_reg_classes[CLASS_ia32_gp];
1774 * Get the ABI restrictions for procedure calls.
1775 * @param self The this pointer.
1776 * @param method_type The type of the method (procedure) in question.
1777 * @param abi The abi object to be modified
1779 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1786 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1789 /* set abi flags for calls */
1790 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1791 call_flags.bits.store_args_sequential = 0;
1792 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1793 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1794 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1796 /* set parameter passing style */
1797 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1799 if (get_method_variadicity(method_type) == variadicity_variadic) {
1800 /* pass all parameters of a variadic function on the stack */
1803 cc = get_method_calling_convention(method_type);
1804 if (get_method_additional_properties(method_type) & mtp_property_private
1805 && (ia32_cg_config.optimize_cc)) {
1806 /* set the calling conventions to register parameter */
1807 cc = (cc & ~cc_bits) | cc_reg_param;
1811 /* we have to pop the shadow parameter ourself for compound calls */
1812 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1813 && !(cc & cc_reg_param)) {
1814 be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
1817 n = get_method_n_params(method_type);
1818 for (i = regnum = 0; i < n; i++) {
1820 const arch_register_t *reg = NULL;
1822 tp = get_method_param_type(method_type, i);
1823 mode = get_type_mode(tp);
1825 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1828 be_abi_call_param_reg(abi, i, reg);
1831 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1832 * movl has a shorter opcode than mov[sz][bw]l */
1833 ir_mode *load_mode = mode;
1834 if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
1835 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1839 /* set return registers */
1840 n = get_method_n_ress(method_type);
1842 assert(n <= 2 && "more than two results not supported");
1844 /* In case of 64bit returns, we will have two 32bit values */
1846 tp = get_method_res_type(method_type, 0);
1847 mode = get_type_mode(tp);
1849 assert(!mode_is_float(mode) && "two FP results not supported");
1851 tp = get_method_res_type(method_type, 1);
1852 mode = get_type_mode(tp);
1854 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1856 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1857 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1860 const arch_register_t *reg;
1862 tp = get_method_res_type(method_type, 0);
1863 assert(is_atomic_type(tp));
1864 mode = get_type_mode(tp);
1866 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1868 be_abi_call_res_reg(abi, 0, reg);
1872 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1876 if(!is_ia32_irn(irn)) {
1880 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1881 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1882 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1883 || is_ia32_Immediate(irn))
1890 * Initializes the code generator interface.
1892 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1895 return &ia32_code_gen_if;
1899 * Returns the estimated execution time of an ia32 irn.
1901 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1903 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1906 list_sched_selector_t ia32_sched_selector;
1909 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1911 static const list_sched_selector_t *ia32_get_list_sched_selector(
1912 const void *self, list_sched_selector_t *selector)
1915 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1916 ia32_sched_selector.exectime = ia32_sched_exectime;
1917 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1918 return &ia32_sched_selector;
1921 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1928 * Returns the necessary byte alignment for storing a register of given class.
1930 static int ia32_get_reg_class_alignment(const void *self,
1931 const arch_register_class_t *cls)
1933 ir_mode *mode = arch_register_class_mode(cls);
1934 int bytes = get_mode_size_bytes(mode);
1937 if (mode_is_float(mode) && bytes > 8)
1942 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1943 const void *self, const ir_node *irn)
1945 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1946 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1947 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1950 static const be_execution_unit_t *_allowed_units_GP[] = {
1951 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1952 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1953 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1954 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1955 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1956 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1957 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1960 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1961 &be_machine_execution_units_DUMMY[0],
1964 static const be_execution_unit_t **_units_callret[] = {
1965 _allowed_units_BRANCH,
1968 static const be_execution_unit_t **_units_other[] = {
1972 static const be_execution_unit_t **_units_dummy[] = {
1973 _allowed_units_DUMMY,
1976 const be_execution_unit_t ***ret;
1979 if (is_ia32_irn(irn)) {
1980 ret = get_ia32_exec_units(irn);
1982 else if (is_be_node(irn)) {
1983 if (be_is_Call(irn) || be_is_Return(irn)) {
1984 ret = _units_callret;
1986 else if (be_is_Barrier(irn)) {
2001 * Return the abstract ia32 machine.
2003 static const be_machine_t *ia32_get_machine(const void *self) {
2004 const ia32_isa_t *isa = self;
2009 * Return irp irgs in the desired order.
2011 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2019 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2020 * @return 1 if allowed, 0 otherwise
2022 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2024 ir_node *phi, *left;
2025 ir_node *cmp = NULL;
2028 if (ia32_cg_config.use_cmov) {
2029 /* we can't handle psis with 64bit compares yet */
2031 cmp = get_Proj_pred(sel);
2033 left = get_Cmp_left(cmp);
2034 cmp_mode = get_irn_mode(left);
2035 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2042 if (ia32_cg_config.use_sse2 && cmp != NULL) {
2043 pn_Cmp pn = get_Proj_proj(sel);
2044 ir_node *cl = get_Cmp_left(cmp);
2045 ir_node *cr = get_Cmp_right(cmp);
2047 /* check the Phi nodes: no 64bit and no floating point cmov */
2048 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2049 ir_mode *mode = get_irn_mode(phi);
2051 if (mode_is_float(mode)) {
2052 /* check for Min, Max */
2053 ir_node *t = get_Phi_pred(phi, i);
2054 ir_node *f = get_Phi_pred(phi, j);
2057 /* SSE2 supports Min & Max */
2058 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2059 if (cl == t && cr == f) {
2060 /* Psi(a <=/>= b, a, b) => MIN, MAX */
2062 } else if (cl == f && cr == t) {
2063 /* Psi(a <=/>= b, b, a) => MAX, MIN */
2070 } else if (get_mode_size_bits(mode) > 32)
2074 /* check the Phi nodes: no 64bit and no floating point cmov */
2075 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2076 ir_mode *mode = get_irn_mode(phi);
2078 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2088 /* No cmov, only some special cases */
2091 cmp = get_Proj_pred(sel);
2095 left = get_Cmp_left(cmp);
2096 cmp_mode = get_irn_mode(left);
2098 /* Now some supported cases here */
2099 pn = get_Proj_proj(sel);
2100 cl = get_Cmp_left(cmp);
2101 cr = get_Cmp_right(cmp);
2103 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2104 ir_mode *mode = get_irn_mode(phi);
2108 t = get_Phi_pred(phi, i);
2109 f = get_Phi_pred(phi, j);
2111 /* no floating point and no 64bit yet */
2112 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2115 if (is_Const(t) && is_Const(f)) {
2116 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2117 /* always support Psi(x, C1, C2) */
2120 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2123 } else if (cl == t && cr == f) {
2124 /* Psi(a <=/>= b, a, b) => Min, Max */
2126 } else if (cl == f && cr == t) {
2127 /* Psi(a <=/>= b, b, a) => Max, Min */
2130 } else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2131 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2132 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2133 /* Psi(a >=u b, a - b, 0) unsigned Doz */
2135 } else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2136 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2137 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2138 /* Psi(a <=u b, 0, a - b) unsigned Doz */
2140 } else if (is_Const(cr) && is_Const_null(cr)) {
2141 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2142 /* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
2144 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2145 /* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
2153 /* all checks passed */
2160 * Returns the libFirm configuration parameter for this backend.
2162 static const backend_params *ia32_get_libfirm_params(void) {
2163 static const ir_settings_if_conv_t ifconv = {
2164 4, /* maxdepth, doesn't matter for Psi-conversion */
2165 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2167 static const ir_settings_arch_dep_t ad = {
2168 1, /* also use subs */
2169 4, /* maximum shifts */
2170 31, /* maximum shift amount */
2171 ia32_evaluate_insn, /* evaluate the instruction sequence */
2173 1, /* allow Mulhs */
2174 1, /* allow Mulus */
2175 32 /* Mulh allowed up to 32 bit */
2177 static backend_params p = {
2178 1, /* need dword lowering */
2179 1, /* support inline assembly */
2180 NULL, /* no additional opcodes */
2181 NULL, /* will be set later */
2182 ia32_create_intrinsic_fkt,
2183 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2184 NULL, /* will be set below */
2187 ia32_setup_cg_config();
2190 p.if_conv_info = &ifconv;
2194 static const lc_opt_enum_int_items_t gas_items[] = {
2195 { "elf", GAS_FLAVOUR_ELF },
2196 { "mingw", GAS_FLAVOUR_MINGW },
2197 { "yasm", GAS_FLAVOUR_YASM },
2198 { "macho", GAS_FLAVOUR_MACH_O },
2202 static lc_opt_enum_int_var_t gas_var = {
2203 (int*) &be_gas_flavour, gas_items
2206 static const lc_opt_table_entry_t ia32_options[] = {
2207 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2208 LC_OPT_ENT_INT("stackalign", "set stack alignment for calls",
2209 &ia32_isa_template.arch_env.stack_alignment),
2213 const arch_isa_if_t ia32_isa_if = {
2216 ia32_get_n_reg_class,
2218 ia32_get_reg_class_for_mode,
2220 ia32_get_code_generator_if,
2221 ia32_get_list_sched_selector,
2222 ia32_get_ilp_sched_selector,
2223 ia32_get_reg_class_alignment,
2224 ia32_get_libfirm_params,
2225 ia32_get_allowed_execution_units,
2230 void ia32_init_emitter(void);
2231 void ia32_init_finish(void);
2232 void ia32_init_optimize(void);
2233 void ia32_init_transform(void);
2234 void ia32_init_x87(void);
2236 void be_init_arch_ia32(void)
2238 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2239 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2241 lc_opt_add_table(ia32_grp, ia32_options);
2242 be_register_isa_if("ia32", &ia32_isa_if);
2244 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2246 ia32_init_emitter();
2248 ia32_init_optimize();
2249 ia32_init_transform();
2251 ia32_init_architecture();
2254 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);