2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
26 #include "pseudo_irg.h"
30 #include "iredges_t.h"
39 #include "../beabi.h" /* the general register allocator interface */
40 #include "../benode_t.h"
41 #include "../belower.h"
42 #include "../besched_t.h"
45 #include "../beirgmod.h"
46 #include "../be_dbgout.h"
47 #include "../beblocksched.h"
48 #include "../bemachine.h"
49 #include "../beilpsched.h"
50 #include "../bespillslots.h"
51 #include "../bemodule.h"
53 #include "bearch_ia32_t.h"
55 #include "ia32_new_nodes.h" /* ia32 nodes interface */
56 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
57 #include "gen_ia32_machine.h"
58 #include "ia32_gen_decls.h" /* interface declaration emitter */
59 #include "ia32_transform.h"
60 #include "ia32_emitter.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_optimize.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_finish.h"
66 #include "ia32_util.h"
68 #define DEBUG_MODULE "firm.be.ia32.isa"
71 static set *cur_reg_set = NULL;
73 /* Creates the unique per irg GP NoReg node. */
74 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
75 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
78 /* Creates the unique per irg FP NoReg node. */
79 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
80 return be_abi_get_callee_save_irn(cg->birg->abi,
81 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
85 * Returns gp_noreg or fp_noreg, depending in input requirements.
87 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
88 arch_register_req_t req;
89 const arch_register_req_t *p_req;
91 p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
92 assert(p_req && "Missing register requirements");
93 if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
94 return ia32_new_NoReg_gp(cg);
96 return ia32_new_NoReg_fp(cg);
99 /**************************************************
102 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
103 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
104 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
105 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
108 **************************************************/
111 * Return register requirements for an ia32 node.
112 * If the node returns a tuple (mode_T) then the proj's
113 * will be asked for this information.
115 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
116 const ia32_irn_ops_t *ops = self;
117 const ia32_register_req_t *irn_req;
118 long node_pos = pos == -1 ? 0 : pos;
119 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
120 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
122 if (is_Block(irn) || mode == mode_X) {
123 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
127 if (mode == mode_T && pos < 0) {
128 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
132 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
139 DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
143 node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
144 irn = skip_Proj_const(irn);
146 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
149 if (is_ia32_irn(irn)) {
150 irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
151 if (irn_req == NULL) {
152 /* no requirements */
156 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
158 memcpy(req, &(irn_req->req), sizeof(*req));
160 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
161 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
162 req->other_same = get_irn_n(irn, irn_req->same_pos);
165 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
166 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
167 req->other_different = get_irn_n(irn, irn_req->different_pos);
171 /* treat Unknowns like Const with default requirements */
172 if (is_Unknown(irn)) {
173 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
174 if (mode_is_float(mode)) {
175 if (USE_SSE2(ops->cg))
176 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
178 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
180 else if (mode_is_int(mode) || mode_is_reference(mode))
181 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
182 else if (mode == mode_T || mode == mode_M) {
183 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
187 assert(0 && "unsupported Unknown-Mode");
190 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
198 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
200 const ia32_irn_ops_t *ops = self;
202 if (get_irn_mode(irn) == mode_X) {
206 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
209 pos = get_Proj_proj(irn);
210 irn = skip_Proj(irn);
213 if (is_ia32_irn(irn)) {
214 const arch_register_t **slots;
216 slots = get_ia32_slots(irn);
220 ia32_set_firm_reg(irn, reg, cur_reg_set);
224 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
226 const arch_register_t *reg = NULL;
230 if (get_irn_mode(irn) == mode_X) {
234 pos = get_Proj_proj(irn);
235 irn = skip_Proj_const(irn);
238 if (is_ia32_irn(irn)) {
239 const arch_register_t **slots;
240 slots = get_ia32_slots(irn);
244 reg = ia32_get_firm_reg(irn, cur_reg_set);
250 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
251 arch_irn_class_t classification = arch_irn_class_normal;
253 irn = skip_Proj_const(irn);
256 classification |= arch_irn_class_branch;
258 if (! is_ia32_irn(irn))
259 return classification & ~arch_irn_class_normal;
261 if (is_ia32_Cnst(irn))
262 classification |= arch_irn_class_const;
265 classification |= arch_irn_class_load;
267 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
268 classification |= arch_irn_class_store;
270 if (is_ia32_got_reload(irn))
271 classification |= arch_irn_class_reload;
273 return classification;
276 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
277 arch_irn_flags_t flags;
278 ir_node *pred = is_Proj(irn) && mode_is_datab(get_irn_mode(irn)) ? get_Proj_pred(irn) : NULL;
281 flags = arch_irn_flags_ignore;
283 /* pred is only set, if we have a Proj */
284 flags = pred && is_ia32_irn(pred) ? get_ia32_out_flags(pred, get_Proj_proj(irn)) : arch_irn_flags_none;
286 irn = skip_Proj_const(irn);
287 if (is_ia32_irn(irn))
288 flags |= get_ia32_flags(irn);
295 * The IA32 ABI callback object.
298 be_abi_call_flags_bits_t flags; /**< The call flags. */
299 const arch_isa_t *isa; /**< The ISA handle. */
300 const arch_env_t *aenv; /**< The architecture environment. */
301 ir_graph *irg; /**< The associated graph. */
304 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
305 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
308 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
309 set_ia32_frame_ent(irn, ent);
312 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
313 const ia32_irn_ops_t *ops = self;
315 if (get_ia32_frame_ent(irn)) {
316 if(is_ia32_Pop(irn)) {
317 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
319 /* Pop nodes modify the stack pointer before calculating the destination
320 * address, so fix this here
326 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
328 if (get_ia32_op_type(irn) == ia32_Normal) {
329 // Matze: When does this case happen?
331 snprintf(buf, sizeof(buf), "%d", bias);
332 set_ia32_cnst(irn, buf);
334 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
336 set_ia32_am_flavour(irn, am_flav);
338 add_ia32_am_offs_int(irn, bias);
343 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
345 long proj = get_Proj_proj(irn);
346 ir_node *pred = get_Proj_pred(irn);
348 if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack)
350 if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack)
358 * Put all registers which are saved by the prologue/epilogue in a set.
360 * @param self The callback object.
361 * @param s The result set.
363 static void ia32_abi_dont_save_regs(void *self, pset *s)
365 ia32_abi_env_t *env = self;
366 if(env->flags.try_omit_fp)
367 pset_insert_ptr(s, env->isa->bp);
371 * Generate the routine prologue.
373 * @param self The callback object.
374 * @param mem A pointer to the mem node. Update this if you define new memory.
375 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
377 * @return The register which shall be used as a stack frame base.
379 * All nodes which define registers in @p reg_map must keep @p reg_map current.
381 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
383 ia32_abi_env_t *env = self;
385 if (! env->flags.try_omit_fp) {
386 ir_node *bl = get_irg_start_block(env->irg);
387 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
388 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
389 ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
393 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
394 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
395 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
397 /* the push must have SP out register */
398 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
399 set_ia32_flags(push, arch_irn_flags_ignore);
401 /* move esp to ebp */
402 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
403 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
404 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
405 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
407 /* beware: the copy must be done before any other sp use */
408 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
409 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
410 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
411 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
413 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
414 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
423 * Generate the routine epilogue.
424 * @param self The callback object.
425 * @param bl The block for the epilog
426 * @param mem A pointer to the mem node. Update this if you define new memory.
427 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
428 * @return The register which shall be used as a stack frame base.
430 * All nodes which define registers in @p reg_map must keep @p reg_map current.
432 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
434 ia32_abi_env_t *env = self;
435 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
436 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
438 if (env->flags.try_omit_fp) {
439 /* simply remove the stack frame here */
440 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
441 add_irn_dep(curr_sp, *mem);
444 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
445 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
447 /* gcc always emits a leave at the end of a routine */
448 if (1 || ARCH_AMD(isa->opt_arch)) {
452 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
453 set_ia32_flags(leave, arch_irn_flags_ignore);
454 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
455 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
456 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
459 ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
462 /* copy ebp to esp */
463 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
466 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
467 set_ia32_flags(pop, arch_irn_flags_ignore);
468 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
469 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
470 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
472 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
473 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
476 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
477 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
481 * Initialize the callback object.
482 * @param call The call object.
483 * @param aenv The architecture environment.
484 * @param irg The graph with the method.
485 * @return Some pointer. This pointer is passed to all other callback functions as self object.
487 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
489 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
490 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
491 env->flags = fl.bits;
494 env->isa = aenv->isa;
499 * Destroy the callback object.
500 * @param self The callback object.
502 static void ia32_abi_done(void *self) {
507 * Produces the type which sits between the stack args and the locals on the stack.
508 * it will contain the return address and space to store the old base pointer.
509 * @return The Firm type modeling the ABI between type.
511 static ir_type *ia32_abi_get_between_type(void *self)
513 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
514 static ir_type *omit_fp_between_type = NULL;
515 static ir_type *between_type = NULL;
517 ia32_abi_env_t *env = self;
519 if (! between_type) {
520 ir_entity *old_bp_ent;
521 ir_entity *ret_addr_ent;
522 ir_entity *omit_fp_ret_addr_ent;
524 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_P);
525 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_P);
527 between_type = new_type_struct(IDENT("ia32_between_type"));
528 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
529 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
531 set_entity_offset(old_bp_ent, 0);
532 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
533 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
534 set_type_state(between_type, layout_fixed);
536 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
537 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
539 set_entity_offset(omit_fp_ret_addr_ent, 0);
540 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
541 set_type_state(omit_fp_between_type, layout_fixed);
544 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
549 * Get the estimated cycle count for @p irn.
551 * @param self The this pointer.
552 * @param irn The node.
554 * @return The estimated cycle count for this operation
556 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
559 ia32_op_type_t op_tp;
560 const ia32_irn_ops_t *ops = self;
564 if (!is_ia32_irn(irn))
567 assert(is_ia32_irn(irn));
569 cost = get_ia32_latency(irn);
570 op_tp = get_ia32_op_type(irn);
572 if (is_ia32_CopyB(irn)) {
574 if (ARCH_INTEL(ops->cg->arch))
577 else if (is_ia32_CopyB_i(irn)) {
578 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
579 cost = 20 + (int)ceil((4/3) * size);
580 if (ARCH_INTEL(ops->cg->arch))
583 /* in case of address mode operations add additional cycles */
584 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
586 In case of stack access add 5 cycles (we assume stack is in cache),
587 other memory operations cost 20 cycles.
589 cost += is_ia32_use_frame(irn) ? 5 : 20;
596 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
598 * @param irn The original operation
599 * @param i Index of the argument we want the inverse operation to yield
600 * @param inverse struct to be filled with the resulting inverse op
601 * @param obstack The obstack to use for allocation of the returned nodes array
602 * @return The inverse operation or NULL if operation invertible
604 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
608 ir_node *block, *noreg, *nomem;
611 /* we cannot invert non-ia32 irns */
612 if (! is_ia32_irn(irn))
615 /* operand must always be a real operand (not base, index or mem) */
616 if (i != 2 && i != 3)
619 /* we don't invert address mode operations */
620 if (get_ia32_op_type(irn) != ia32_Normal)
623 irg = get_irn_irg(irn);
624 block = get_nodes_block(irn);
625 mode = get_ia32_res_mode(irn);
626 irn_mode = get_irn_mode(irn);
627 noreg = get_irn_n(irn, 0);
628 nomem = new_r_NoMem(irg);
629 dbg = get_irn_dbg_info(irn);
631 /* initialize structure */
632 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
636 switch (get_ia32_irn_opcode(irn)) {
638 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
639 /* we have an add with a const here */
640 /* invers == add with negated const */
641 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem, irn_mode);
643 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
644 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
645 set_ia32_commutative(inverse->nodes[0]);
647 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
648 /* we have an add with a symconst here */
649 /* invers == sub with const */
650 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem, irn_mode);
652 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
655 /* normal add: inverse == sub */
656 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem, irn_mode);
661 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
662 /* we have a sub with a const/symconst here */
663 /* invers == add with this const */
664 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem, irn_mode);
665 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
666 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
671 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem, irn_mode);
674 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem, irn_mode);
680 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
681 /* xor with const: inverse = xor */
682 inverse->nodes[0] = new_rd_ia32_Eor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem, irn_mode);
683 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
684 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
688 inverse->nodes[0] = new_rd_ia32_Eor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem, irn_mode);
693 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem, irn_mode);
697 case iro_ia32_Minus: {
698 inverse->nodes[0] = new_rd_ia32_Minus(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem, irn_mode);
703 /* inverse operation not supported */
707 set_ia32_res_mode(inverse->nodes[0], mode);
713 * Get the mode that should be used for spilling value node
715 static ir_mode *get_spill_mode(ia32_code_gen_t *cg, const ir_node *node)
717 ir_mode *mode = get_irn_mode(node);
718 if (mode_is_float(mode)) {
720 // super exact spilling...
737 * Checks wether an addressmode reload for a node with mode mode is compatible
738 * with a spillslot of mode spill_mode
740 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
742 if(mode_is_float(mode)) {
743 return mode == spillmode;
750 * Check if irn can load it's operand at position i from memory (source addressmode).
751 * @param self Pointer to irn ops itself
752 * @param irn The irn to be checked
753 * @param i The operands position
754 * @return Non-Zero if operand can be loaded
756 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
757 const ia32_irn_ops_t *ops = self;
758 ia32_code_gen_t *cg = ops->cg;
759 ir_node *op = get_irn_n(irn, i);
760 const ir_mode *mode = get_irn_mode(op);
761 const ir_mode *spillmode = get_spill_mode(cg, op);
763 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
764 get_irn_arity(irn) != 5 || /* must be a binary operation */
765 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
766 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
767 ! ia32_is_spillmode_compatible(mode, spillmode) ||
768 (i != 2 && i != 3) || /* a "real" operand position must be requested */
769 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
770 is_ia32_use_frame(irn)) /* must not already use frame */
776 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
777 const ia32_irn_ops_t *ops = self;
778 ia32_code_gen_t *cg = ops->cg;
780 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
783 ir_node *tmp = get_irn_n(irn, 3);
784 set_irn_n(irn, 3, get_irn_n(irn, 2));
785 set_irn_n(irn, 2, tmp);
788 set_ia32_am_support(irn, ia32_am_Source);
789 set_ia32_op_type(irn, ia32_AddrModeS);
790 set_ia32_am_flavour(irn, ia32_B);
791 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
792 set_ia32_use_frame(irn);
793 set_ia32_got_reload(irn);
795 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
796 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
797 set_irn_n(irn, 4, spill);
799 //FIXME DBG_OPT_AM_S(reload, irn);
802 static const be_abi_callbacks_t ia32_abi_callbacks = {
805 ia32_abi_get_between_type,
806 ia32_abi_dont_save_regs,
811 /* fill register allocator interface */
813 static const arch_irn_ops_if_t ia32_irn_ops_if = {
814 ia32_get_irn_reg_req,
819 ia32_get_frame_entity,
820 ia32_set_frame_entity,
821 ia32_set_frame_offset,
824 ia32_get_op_estimated_cost,
825 ia32_possible_memory_operand,
826 ia32_perform_memory_operand,
829 ia32_irn_ops_t ia32_irn_ops = {
836 /**************************************************
839 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
840 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
841 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
842 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
845 **************************************************/
847 static void ia32_kill_convs(ia32_code_gen_t *cg) {
850 foreach_nodeset(cg->kill_conv, irn) {
851 ir_node *in = get_irn_n(irn, 2);
852 edges_reroute(irn, in, cg->birg->irg);
857 * Transform the Thread Local Store base.
859 static void transform_tls(ir_graph *irg) {
860 ir_node *irn = get_irg_tls(irg);
863 dbg_info *dbg = get_irn_dbg_info(irn);
864 ir_node *blk = get_nodes_block(irn);
866 newn = new_rd_ia32_LdTls(dbg, irg, blk, get_irn_mode(irn));
869 set_irg_tls(irg, newn);
874 * Transforms the standard firm graph into
877 static void ia32_prepare_graph(void *self) {
878 ia32_code_gen_t *cg = self;
879 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
881 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
883 /* 1st: transform constants and psi condition trees */
884 ia32_pre_transform_phase(cg);
886 /* 2nd: transform all remaining nodes */
887 ia32_register_transformers();
889 cg->kill_conv = new_nodeset(5);
890 transform_tls(cg->irg);
891 edges_deactivate(cg->irg);
892 edges_activate(cg->irg);
893 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
895 del_nodeset(cg->kill_conv);
898 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
900 /* 3rd: optimize address mode */
901 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
902 ia32_optimize_addressmode(cg);
905 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
907 DEBUG_ONLY(cg->mod = old_mod;)
911 * Dummy functions for hooks we don't need but which must be filled.
913 static void ia32_before_sched(void *self) {
916 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
919 ir_node *mem_proj = NULL;
924 mode = get_irn_mode(irn);
926 /* check if we already saw this node or the node has more than one user */
927 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
931 /* mark irn visited */
932 bitset_add_irn(already_visited, irn);
934 /* non-Tuple nodes with one user: ok, return */
935 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
939 /* tuple node has one user which is not the mem proj-> ok */
940 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
941 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
942 if (mem_proj == NULL) {
947 arity = get_irn_arity(irn);
948 for (i = 0; i < arity; ++i) {
949 ir_node *pred = get_irn_n(irn, i);
951 /* do not follow memory edges or we will accidentally remove stores */
952 if (get_irn_mode(pred) == mode_M) {
953 if(mem_proj != NULL) {
954 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
960 set_irn_n(irn, i, new_Bad());
963 The current node is about to be removed: if the predecessor
964 has only this node as user, it need to be removed as well.
966 if (get_irn_n_edges(pred) <= 1)
967 remove_unused_nodes(pred, already_visited);
970 // we need to set the presd to Bad again to also get the memory edges
971 arity = get_irn_arity(irn);
972 for (i = 0; i < arity; ++i) {
973 set_irn_n(irn, i, new_Bad());
976 if (sched_is_scheduled(irn)) {
981 static void remove_unused_loads_walker(ir_node *irn, void *env) {
982 bitset_t *already_visited = env;
983 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
984 remove_unused_nodes(irn, env);
988 * Called before the register allocator.
989 * Calculate a block schedule here. We need it for the x87
990 * simulator and the emitter.
992 static void ia32_before_ra(void *self) {
993 ia32_code_gen_t *cg = self;
994 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
998 There are sometimes unused loads, only pinned by memory.
999 We need to remove those Loads and all other nodes which won't be used
1000 after removing the Load from schedule.
1002 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
1007 * Transforms a be_Reload into a ia32 Load.
1009 static void transform_to_Load(ia32_transform_env_t *env) {
1010 ir_node *irn = env->irn;
1011 ir_entity *ent = be_get_frame_entity(irn);
1012 ir_mode *mode = get_irn_mode(irn);
1013 ir_mode *spillmode = get_spill_mode(env->cg, irn);
1014 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1015 ir_node *sched_point = NULL;
1016 ir_node *ptr = get_irg_frame(env->irg);
1017 ir_node *mem = get_irn_n(irn, be_pos_Reload_mem);
1018 ir_node *new_op, *proj;
1019 const arch_register_t *reg;
1021 if (sched_is_scheduled(irn)) {
1022 sched_point = sched_prev(irn);
1025 if (mode_is_float(spillmode)) {
1026 if (USE_SSE2(env->cg))
1027 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1029 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1032 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1034 set_ia32_am_support(new_op, ia32_am_Source);
1035 set_ia32_op_type(new_op, ia32_AddrModeS);
1036 set_ia32_am_flavour(new_op, ia32_B);
1037 set_ia32_ls_mode(new_op, spillmode);
1038 set_ia32_frame_ent(new_op, ent);
1039 set_ia32_use_frame(new_op);
1041 DBG_OPT_RELOAD2LD(irn, new_op);
1043 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1046 sched_add_after(sched_point, new_op);
1047 sched_add_after(new_op, proj);
1052 /* copy the register from the old node to the new Load */
1053 reg = arch_get_irn_register(env->cg->arch_env, irn);
1054 arch_set_irn_register(env->cg->arch_env, new_op, reg);
1056 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
1058 exchange(irn, proj);
1062 * Transforms a be_Spill node into a ia32 Store.
1064 static void transform_to_Store(ia32_transform_env_t *env) {
1065 ir_node *irn = env->irn;
1066 ir_entity *ent = be_get_frame_entity(irn);
1067 const ir_node *spillval = get_irn_n(irn, be_pos_Spill_val);
1068 ir_mode *mode = get_spill_mode(env->cg, spillval);
1069 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1070 ir_node *nomem = new_rd_NoMem(env->irg);
1071 ir_node *ptr = get_irg_frame(env->irg);
1072 ir_node *val = get_irn_n(irn, be_pos_Spill_val);
1074 ir_node *sched_point = NULL;
1076 if (sched_is_scheduled(irn)) {
1077 sched_point = sched_prev(irn);
1080 if (mode_is_float(mode)) {
1081 if (USE_SSE2(env->cg))
1082 store = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1084 store = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1086 else if (get_mode_size_bits(mode) == 8) {
1087 store = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1090 store = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1093 set_ia32_am_support(store, ia32_am_Dest);
1094 set_ia32_op_type(store, ia32_AddrModeD);
1095 set_ia32_am_flavour(store, ia32_B);
1096 set_ia32_ls_mode(store, mode);
1097 set_ia32_frame_ent(store, ent);
1098 set_ia32_use_frame(store);
1100 DBG_OPT_SPILL2ST(irn, store);
1101 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env->cg, irn));
1104 sched_add_after(sched_point, store);
1108 exchange(irn, store);
1111 static ir_node *create_push(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1112 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1113 ir_node *frame = get_irg_frame(env->irg);
1115 ir_node *push = new_rd_ia32_Push(env->dbg, env->irg, env->block, frame, noreg, noreg, sp, mem);
1117 set_ia32_frame_ent(push, ent);
1118 set_ia32_use_frame(push);
1119 set_ia32_op_type(push, ia32_AddrModeS);
1120 set_ia32_am_flavour(push, ia32_B);
1121 set_ia32_ls_mode(push, mode_Is);
1123 sched_add_before(schedpoint, push);
1127 static ir_node *create_pop(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1128 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1129 ir_node *frame = get_irg_frame(env->irg);
1131 ir_node *pop = new_rd_ia32_Pop(env->dbg, env->irg, env->block, frame, noreg, sp, new_NoMem());
1133 set_ia32_frame_ent(pop, ent);
1134 set_ia32_use_frame(pop);
1135 set_ia32_op_type(pop, ia32_AddrModeD);
1136 set_ia32_am_flavour(pop, ia32_am_OB);
1137 set_ia32_ls_mode(pop, mode_Is);
1139 sched_add_before(schedpoint, pop);
1144 static ir_node* create_spproj(ia32_transform_env_t *env, ir_node *pred, int pos, ir_node *schedpoint) {
1145 ir_mode *spmode = mode_Iu;
1146 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1149 sp = new_rd_Proj(env->dbg, env->irg, env->block, pred, spmode, pos);
1150 arch_set_irn_register(env->cg->arch_env, sp, spreg);
1151 sched_add_before(schedpoint, sp);
1157 * Transform memperm, currently we do this the ugly way and produce
1158 * push/pop into/from memory cascades. This is possible without using
1161 static void transform_MemPerm(ia32_transform_env_t *env) {
1162 ir_node *node = env->irn;
1164 ir_node *sp = be_abi_get_ignore_irn(env->cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1165 const ir_edge_t *edge;
1166 const ir_edge_t *next;
1169 arity = be_get_MemPerm_entity_arity(node);
1170 pops = alloca(arity * sizeof(pops[0]));
1173 for(i = 0; i < arity; ++i) {
1174 ir_entity *ent = be_get_MemPerm_in_entity(node, i);
1175 ir_type *enttype = get_entity_type(ent);
1176 int entbits = get_type_size_bits(enttype);
1177 ir_node *mem = get_irn_n(node, i + 1);
1180 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1182 push = create_push(env, node, sp, mem, ent);
1183 sp = create_spproj(env, push, 0, node);
1185 // add another push after the first one
1186 push = create_push(env, node, sp, mem, ent);
1187 add_ia32_am_offs_int(push, 4);
1188 sp = create_spproj(env, push, 0, node);
1191 set_irn_n(node, i, new_Bad());
1195 for(i = arity - 1; i >= 0; --i) {
1196 ir_entity *ent = be_get_MemPerm_out_entity(node, i);
1197 ir_type *enttype = get_entity_type(ent);
1198 int entbits = get_type_size_bits(enttype);
1202 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1204 pop = create_pop(env, node, sp, ent);
1206 // add another pop after the first one
1207 sp = create_spproj(env, pop, 1, node);
1208 pop = create_pop(env, node, sp, ent);
1209 add_ia32_am_offs_int(pop, 4);
1211 sp = create_spproj(env, pop, 1, node);
1216 // exchange memprojs
1217 foreach_out_edge_safe(node, edge, next) {
1218 ir_node *proj = get_edge_src_irn(edge);
1219 int p = get_Proj_proj(proj);
1223 set_Proj_pred(proj, pops[p]);
1224 set_Proj_proj(proj, 3);
1228 arity = get_irn_arity(node);
1229 for(i = 0; i < arity; ++i) {
1230 set_irn_n(node, i, new_Bad());
1236 * Block-Walker: Calls the transform functions Spill and Reload.
1238 static void ia32_after_ra_walker(ir_node *block, void *env) {
1239 ir_node *node, *prev;
1240 ia32_code_gen_t *cg = env;
1241 ia32_transform_env_t tenv;
1244 tenv.irg = current_ir_graph;
1246 DEBUG_ONLY(tenv.mod = cg->mod;)
1248 /* beware: the schedule is changed here */
1249 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1250 prev = sched_prev(node);
1251 tenv.dbg = get_irn_dbg_info(node);
1253 tenv.mode = get_irn_mode(node);
1255 if (be_is_Reload(node)) {
1256 transform_to_Load(&tenv);
1257 } else if (be_is_Spill(node)) {
1258 transform_to_Store(&tenv);
1259 } else if(be_is_MemPerm(node)) {
1260 transform_MemPerm(&tenv);
1266 * Collects nodes that need frame entities assigned.
1268 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1270 be_fec_env_t *env = data;
1272 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1273 const ir_mode *mode = get_irn_mode(node);
1274 int align = get_mode_size_bytes(mode);
1275 be_node_needs_frame_entity(env, node, mode, align);
1276 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1277 && is_ia32_use_frame(node)) {
1278 if (is_ia32_Load(node)) {
1279 const ir_mode *mode = get_ia32_ls_mode(node);
1280 int align = get_mode_size_bytes(mode);
1281 be_node_needs_frame_entity(env, node, mode, align);
1282 } else if (is_ia32_vfild(node)) {
1283 const ir_mode *mode = get_ia32_ls_mode(node);
1285 be_node_needs_frame_entity(env, node, mode, align);
1291 * We transform Spill and Reload here. This needs to be done before
1292 * stack biasing otherwise we would miss the corrected offset for these nodes.
1294 static void ia32_after_ra(void *self) {
1295 ia32_code_gen_t *cg = self;
1296 ir_graph *irg = cg->irg;
1297 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1299 /* create and coalesce frame entities */
1300 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1301 be_assign_entities(fec_env);
1302 be_free_frame_entity_coalescer(fec_env);
1304 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1306 ia32_finish_irg(irg, cg);
1310 * Last touchups for the graph before emit: x87 simulation to replace the
1311 * virtual with real x87 instructions, creating a block schedule and peephole
1314 static void ia32_finish(void *self) {
1315 ia32_code_gen_t *cg = self;
1316 ir_graph *irg = cg->irg;
1318 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1319 if (cg->used_fp == fp_x87 || cg->force_sim) {
1320 x87_simulate_graph(cg->arch_env, cg->birg);
1323 /* create block schedule, this also removes empty blocks which might
1324 * produce critical edges */
1325 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1327 /* do peephole optimisations */
1328 ia32_peephole_optimization(irg, cg);
1332 * Emits the code, closes the output file and frees
1333 * the code generator interface.
1335 static void ia32_codegen(void *self) {
1336 ia32_code_gen_t *cg = self;
1337 ir_graph *irg = cg->irg;
1339 ia32_gen_routine(cg->isa->out, irg, cg);
1343 /* remove it from the isa */
1346 /* de-allocate code generator */
1347 del_set(cg->reg_set);
1351 static void *ia32_cg_init(be_irg_t *birg);
1353 static const arch_code_generator_if_t ia32_code_gen_if = {
1355 NULL, /* before abi introduce hook */
1358 ia32_before_sched, /* before scheduling hook */
1359 ia32_before_ra, /* before register allocation hook */
1360 ia32_after_ra, /* after register allocation hook */
1361 ia32_finish, /* called before codegen */
1362 ia32_codegen /* emit && done */
1366 * Initializes a IA32 code generator.
1368 static void *ia32_cg_init(be_irg_t *birg) {
1369 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1370 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1372 cg->impl = &ia32_code_gen_if;
1373 cg->irg = birg->irg;
1374 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1375 cg->arch_env = birg->main_env->arch_env;
1378 cg->blk_sched = NULL;
1379 cg->fp_kind = isa->fp_kind;
1380 cg->used_fp = fp_none;
1381 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1383 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1385 /* copy optimizations from isa for easier access */
1387 cg->arch = isa->arch;
1388 cg->opt_arch = isa->opt_arch;
1394 if (isa->name_obst) {
1395 obstack_free(isa->name_obst, NULL);
1396 obstack_init(isa->name_obst);
1400 cur_reg_set = cg->reg_set;
1402 ia32_irn_ops.cg = cg;
1404 return (arch_code_generator_t *)cg;
1409 /*****************************************************************
1410 * ____ _ _ _____ _____
1411 * | _ \ | | | | |_ _|/ ____| /\
1412 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1413 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1414 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1415 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1417 *****************************************************************/
1420 * Set output modes for GCC
1422 static const tarval_mode_info mo_integer = {
1429 * set the tarval output mode of all integer modes to decimal
1431 static void set_tarval_output_modes(void)
1435 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1436 ir_mode *mode = get_irp_mode(i);
1438 if (mode_is_int(mode))
1439 set_tarval_mode_output_option(mode, &mo_integer);
1443 const arch_isa_if_t ia32_isa_if;
1446 * The template that generates a new ISA object.
1447 * Note that this template can be changed by command line
1450 static ia32_isa_t ia32_isa_template = {
1452 &ia32_isa_if, /* isa interface implementation */
1453 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1454 &ia32_gp_regs[REG_EBP], /* base pointer register */
1455 -1, /* stack direction */
1456 NULL, /* main environment */
1458 NULL, /* 16bit register names */
1459 NULL, /* 8bit register names */
1463 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1464 IA32_OPT_DOAM | /* optimize address mode default: on */
1465 IA32_OPT_LEA | /* optimize for LEAs default: on */
1466 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1467 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1468 IA32_OPT_EXTBB | /* use extended basic block scheduling, default: on */
1469 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1470 arch_pentium_4, /* instruction architecture */
1471 arch_pentium_4, /* optimize for architecture */
1472 fp_sse2, /* use sse2 unit */
1473 NULL, /* current code generator */
1474 NULL, /* output file */
1476 NULL, /* name obstack */
1477 0 /* name obst size */
1482 * Initializes the backend ISA.
1484 static void *ia32_init(FILE *file_handle) {
1485 static int inited = 0;
1491 set_tarval_output_modes();
1493 isa = xmalloc(sizeof(*isa));
1494 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1496 ia32_register_init(isa);
1497 ia32_create_opcodes();
1498 ia32_register_copy_attr_func();
1500 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1501 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1502 /* no SSE2 for these cpu's */
1503 isa->fp_kind = fp_x87;
1505 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1506 /* Pentium 4 don't like inc and dec instructions */
1507 isa->opt &= ~IA32_OPT_INCDEC;
1510 isa->regs_16bit = pmap_create();
1511 isa->regs_8bit = pmap_create();
1512 isa->types = pmap_create();
1513 isa->tv_ent = pmap_create();
1514 isa->out = file_handle;
1515 isa->cpu = ia32_init_machine_description();
1517 ia32_build_16bit_reg_map(isa->regs_16bit);
1518 ia32_build_8bit_reg_map(isa->regs_8bit);
1520 /* patch register names of x87 registers */
1521 ia32_st_regs[0].name = "st";
1522 ia32_st_regs[1].name = "st(1)";
1523 ia32_st_regs[2].name = "st(2)";
1524 ia32_st_regs[3].name = "st(3)";
1525 ia32_st_regs[4].name = "st(4)";
1526 ia32_st_regs[5].name = "st(5)";
1527 ia32_st_regs[6].name = "st(6)";
1528 ia32_st_regs[7].name = "st(7)";
1531 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1532 obstack_init(isa->name_obst);
1535 ia32_handle_intrinsics();
1536 ia32_switch_section(isa->out, NO_SECTION);
1537 fprintf(isa->out, "\t.intel_syntax\n");
1539 /* needed for the debug support */
1540 ia32_switch_section(isa->out, SECTION_TEXT);
1541 fprintf(isa->out, ".Ltext0:\n");
1551 * Closes the output file and frees the ISA structure.
1553 static void ia32_done(void *self) {
1554 ia32_isa_t *isa = self;
1556 /* emit now all global declarations */
1557 ia32_gen_decls(isa->out, isa->arch_isa.main_env);
1559 pmap_destroy(isa->regs_16bit);
1560 pmap_destroy(isa->regs_8bit);
1561 pmap_destroy(isa->tv_ent);
1562 pmap_destroy(isa->types);
1565 obstack_free(isa->name_obst, NULL);
1573 * Return the number of register classes for this architecture.
1574 * We report always these:
1575 * - the general purpose registers
1576 * - the SSE floating point register set
1577 * - the virtual floating point registers
1579 static int ia32_get_n_reg_class(const void *self) {
1584 * Return the register class for index i.
1586 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1587 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1589 return &ia32_reg_classes[CLASS_ia32_gp];
1591 return &ia32_reg_classes[CLASS_ia32_xmm];
1593 return &ia32_reg_classes[CLASS_ia32_vfp];
1597 * Get the register class which shall be used to store a value of a given mode.
1598 * @param self The this pointer.
1599 * @param mode The mode in question.
1600 * @return A register class which can hold values of the given mode.
1602 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1603 const ia32_isa_t *isa = self;
1604 if (mode_is_float(mode)) {
1605 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1608 return &ia32_reg_classes[CLASS_ia32_gp];
1612 * Get the ABI restrictions for procedure calls.
1613 * @param self The this pointer.
1614 * @param method_type The type of the method (procedure) in question.
1615 * @param abi The abi object to be modified
1617 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1618 const ia32_isa_t *isa = self;
1621 unsigned cc = get_method_calling_convention(method_type);
1622 int n = get_method_n_params(method_type);
1625 int i, ignore_1, ignore_2;
1627 const arch_register_t *reg;
1628 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1630 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1632 /* set abi flags for calls */
1633 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1634 call_flags.bits.store_args_sequential = use_push;
1635 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1636 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1637 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1639 /* set stack parameter passing style */
1640 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1642 /* collect the mode for each type */
1643 modes = alloca(n * sizeof(modes[0]));
1645 for (i = 0; i < n; i++) {
1646 tp = get_method_param_type(method_type, i);
1647 modes[i] = get_type_mode(tp);
1650 /* set register parameters */
1651 if (cc & cc_reg_param) {
1652 /* determine the number of parameters passed via registers */
1653 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1655 /* loop over all parameters and set the register requirements */
1656 for (i = 0; i <= biggest_n; i++) {
1657 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1658 assert(reg && "kaputt");
1659 be_abi_call_param_reg(abi, i, reg);
1666 /* set stack parameters */
1667 for (i = stack_idx; i < n; i++) {
1668 /* parameters on the stack are 32 bit aligned */
1669 be_abi_call_param_stack(abi, i, 4, 0, 0);
1673 /* set return registers */
1674 n = get_method_n_ress(method_type);
1676 assert(n <= 2 && "more than two results not supported");
1678 /* In case of 64bit returns, we will have two 32bit values */
1680 tp = get_method_res_type(method_type, 0);
1681 mode = get_type_mode(tp);
1683 assert(!mode_is_float(mode) && "two FP results not supported");
1685 tp = get_method_res_type(method_type, 1);
1686 mode = get_type_mode(tp);
1688 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1690 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1691 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1694 const arch_register_t *reg;
1696 tp = get_method_res_type(method_type, 0);
1697 assert(is_atomic_type(tp));
1698 mode = get_type_mode(tp);
1700 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1702 be_abi_call_res_reg(abi, 0, reg);
1707 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1708 return &ia32_irn_ops;
1711 const arch_irn_handler_t ia32_irn_handler = {
1715 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1716 return &ia32_irn_handler;
1719 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1720 return is_ia32_irn(irn) ? 1 : -1;
1724 * Initializes the code generator interface.
1726 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1727 return &ia32_code_gen_if;
1731 * Returns the estimated execution time of an ia32 irn.
1733 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1734 const arch_env_t *arch_env = env;
1735 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1738 list_sched_selector_t ia32_sched_selector;
1741 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1743 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1744 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1745 ia32_sched_selector.exectime = ia32_sched_exectime;
1746 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1747 return &ia32_sched_selector;
1750 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
1755 * Returns the necessary byte alignment for storing a register of given class.
1757 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1758 ir_mode *mode = arch_register_class_mode(cls);
1759 int bytes = get_mode_size_bytes(mode);
1761 if (mode_is_float(mode) && bytes > 8)
1766 static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
1767 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1768 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1769 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1772 static const be_execution_unit_t *_allowed_units_ALU[] = {
1773 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU1],
1774 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU2],
1775 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU3],
1776 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU4],
1779 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1780 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY1],
1781 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY2],
1782 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY3],
1783 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY4],
1786 static const be_execution_unit_t **_units_callret[] = {
1787 _allowed_units_BRANCH,
1790 static const be_execution_unit_t **_units_other[] = {
1794 static const be_execution_unit_t **_units_dummy[] = {
1795 _allowed_units_DUMMY,
1798 const be_execution_unit_t ***ret;
1800 if (is_ia32_irn(irn)) {
1801 ret = get_ia32_exec_units(irn);
1803 else if (is_be_node(irn)) {
1804 if (be_is_Call(irn) || be_is_Return(irn)) {
1805 ret = _units_callret;
1807 else if (be_is_Barrier(irn)) {
1822 * Return the abstract ia32 machine.
1824 static const be_machine_t *ia32_get_machine(const void *self) {
1825 const ia32_isa_t *isa = self;
1830 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1831 * @return 1 if allowed, 0 otherwise
1833 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1835 ir_node *cmp, *cmp_a, *phi;
1838 /* we don't want long long an floating point Psi */
1839 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
1841 if (get_irn_mode(sel) != mode_b)
1844 cmp = get_Proj_pred(sel);
1845 cmp_a = get_Cmp_left(cmp);
1846 mode = get_irn_mode(cmp_a);
1848 if (IS_BAD_PSI_MODE(mode))
1851 /* check the Phi nodes */
1852 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1853 ir_node *pred_i = get_irn_n(phi, i);
1854 ir_node *pred_j = get_irn_n(phi, j);
1855 ir_mode *mode_i = get_irn_mode(pred_i);
1856 ir_mode *mode_j = get_irn_mode(pred_j);
1858 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1862 #undef IS_BAD_PSI_MODE
1867 static ia32_intrinsic_env_t intrinsic_env = {
1868 NULL, /**< the irg, these entities belong to */
1869 NULL, /**< entity for first div operand (move into FPU) */
1870 NULL, /**< entity for second div operand (move into FPU) */
1871 NULL, /**< entity for converts ll -> d */
1872 NULL, /**< entity for converts d -> ll */
1876 * Returns the libFirm configuration parameter for this backend.
1878 static const backend_params *ia32_get_libfirm_params(void) {
1879 static const opt_if_conv_info_t ifconv = {
1880 4, /* maxdepth, doesn't matter for Psi-conversion */
1881 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
1883 static const arch_dep_params_t ad = {
1884 1, /* also use subs */
1885 4, /* maximum shifts */
1886 31, /* maximum shift amount */
1888 1, /* allow Mulhs */
1889 1, /* allow Mulus */
1890 32 /* Mulh allowed up to 32 bit */
1892 static backend_params p = {
1893 NULL, /* no additional opcodes */
1894 NULL, /* will be set later */
1895 1, /* need dword lowering */
1896 ia32_create_intrinsic_fkt,
1897 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1898 NULL, /* will be set later */
1902 p.if_conv_info = &ifconv;
1907 /* instruction set architectures. */
1908 static const lc_opt_enum_int_items_t arch_items[] = {
1909 { "386", arch_i386, },
1910 { "486", arch_i486, },
1911 { "pentium", arch_pentium, },
1912 { "586", arch_pentium, },
1913 { "pentiumpro", arch_pentium_pro, },
1914 { "686", arch_pentium_pro, },
1915 { "pentiummmx", arch_pentium_mmx, },
1916 { "pentium2", arch_pentium_2, },
1917 { "p2", arch_pentium_2, },
1918 { "pentium3", arch_pentium_3, },
1919 { "p3", arch_pentium_3, },
1920 { "pentium4", arch_pentium_4, },
1921 { "p4", arch_pentium_4, },
1922 { "pentiumm", arch_pentium_m, },
1923 { "pm", arch_pentium_m, },
1924 { "core", arch_core, },
1926 { "athlon", arch_athlon, },
1927 { "athlon64", arch_athlon_64, },
1928 { "opteron", arch_opteron, },
1932 static lc_opt_enum_int_var_t arch_var = {
1933 &ia32_isa_template.arch, arch_items
1936 static lc_opt_enum_int_var_t opt_arch_var = {
1937 &ia32_isa_template.opt_arch, arch_items
1940 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1942 { "sse2", fp_sse2 },
1946 static lc_opt_enum_int_var_t fp_unit_var = {
1947 &ia32_isa_template.fp_kind, fp_unit_items
1950 static const lc_opt_enum_int_items_t gas_items[] = {
1951 { "linux", ASM_LINUX_GAS },
1952 { "mingw", ASM_MINGW_GAS },
1956 static lc_opt_enum_int_var_t gas_var = {
1957 (int *)&asm_flavour, gas_items
1960 static const lc_opt_table_entry_t ia32_options[] = {
1961 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1962 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1963 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1964 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1965 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1966 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1967 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1968 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1969 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
1970 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1973 #endif /* WITH_LIBCORE */
1975 const arch_isa_if_t ia32_isa_if = {
1978 ia32_get_n_reg_class,
1980 ia32_get_reg_class_for_mode,
1982 ia32_get_irn_handler,
1983 ia32_get_code_generator_if,
1984 ia32_get_list_sched_selector,
1985 ia32_get_ilp_sched_selector,
1986 ia32_get_reg_class_alignment,
1987 ia32_get_libfirm_params,
1988 ia32_get_allowed_execution_units,
1992 void be_init_arch_ia32(void)
1994 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
1995 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
1997 lc_opt_add_table(ia32_grp, ia32_options);
1998 be_register_isa_if("ia32", &ia32_isa_if);
2001 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);