2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
26 #include "pseudo_irg.h"
30 #include "iredges_t.h"
38 #include "../beabi.h" /* the general register allocator interface */
39 #include "../benode_t.h"
40 #include "../belower.h"
41 #include "../besched_t.h"
44 #include "../beirgmod.h"
45 #include "../be_dbgout.h"
46 #include "../beblocksched.h"
47 #include "bearch_ia32_t.h"
49 #include "ia32_new_nodes.h" /* ia32 nodes interface */
50 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
51 #include "ia32_gen_decls.h" /* interface declaration emitter */
52 #include "ia32_transform.h"
53 #include "ia32_emitter.h"
54 #include "ia32_map_regs.h"
55 #include "ia32_optimize.h"
57 #include "ia32_dbg_stat.h"
58 #include "ia32_finish.h"
59 #include "ia32_util.h"
61 #define DEBUG_MODULE "firm.be.ia32.isa"
64 static set *cur_reg_set = NULL;
66 /* Creates the unique per irg GP NoReg node. */
67 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
68 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
71 /* Creates the unique per irg FP NoReg node. */
72 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
73 return be_abi_get_callee_save_irn(cg->birg->abi,
74 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
78 * Returns gp_noreg or fp_noreg, depending in input requirements.
80 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
81 arch_register_req_t req;
82 const arch_register_req_t *p_req;
84 p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
85 assert(p_req && "Missing register requirements");
86 if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
87 return ia32_new_NoReg_gp(cg);
89 return ia32_new_NoReg_fp(cg);
92 /**************************************************
95 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
96 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
97 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
98 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
101 **************************************************/
104 * Return register requirements for an ia32 node.
105 * If the node returns a tuple (mode_T) then the proj's
106 * will be asked for this information.
108 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
109 const ia32_irn_ops_t *ops = self;
110 const ia32_register_req_t *irn_req;
111 long node_pos = pos == -1 ? 0 : pos;
112 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
113 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
115 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
116 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
120 if (mode == mode_T && pos < 0) {
121 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
125 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
129 DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
133 node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
134 irn = skip_Proj(irn);
136 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
139 if (is_ia32_irn(irn)) {
140 irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
142 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
144 memcpy(req, &(irn_req->req), sizeof(*req));
146 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
147 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
148 req->other_same = get_irn_n(irn, irn_req->same_pos);
151 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
152 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
153 req->other_different = get_irn_n(irn, irn_req->different_pos);
157 /* treat Unknowns like Const with default requirements */
158 if (is_Unknown(irn)) {
159 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
160 if (mode_is_float(mode)) {
161 if (USE_SSE2(ops->cg))
162 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
164 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
166 else if (mode_is_int(mode) || mode_is_reference(mode))
167 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
168 else if (mode == mode_T || mode == mode_M) {
169 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
173 assert(0 && "unsupported Unknown-Mode");
176 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
184 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
186 const ia32_irn_ops_t *ops = self;
188 if (get_irn_mode(irn) == mode_X) {
192 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
195 pos = get_Proj_proj(irn);
196 irn = skip_Proj(irn);
199 if (is_ia32_irn(irn)) {
200 const arch_register_t **slots;
202 slots = get_ia32_slots(irn);
206 ia32_set_firm_reg(irn, reg, cur_reg_set);
210 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
212 const arch_register_t *reg = NULL;
216 if (get_irn_mode(irn) == mode_X) {
220 pos = get_Proj_proj(irn);
221 irn = skip_Proj(irn);
224 if (is_ia32_irn(irn)) {
225 /* retrieve "real" x87 register */
226 if (ia32_has_x87_register(irn))
227 reg = get_ia32_attr(irn)->x87[pos + 2];
229 const arch_register_t **slots;
230 slots = get_ia32_slots(irn);
235 reg = ia32_get_firm_reg(irn, cur_reg_set);
241 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
242 arch_irn_class_t classification = arch_irn_class_normal;
244 irn = skip_Proj(irn);
247 classification |= arch_irn_class_branch;
249 if (! is_ia32_irn(irn))
250 return classification & ~arch_irn_class_normal;
252 if (is_ia32_Cnst(irn))
253 classification |= arch_irn_class_const;
256 classification |= arch_irn_class_load;
258 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
259 classification |= arch_irn_class_store;
261 if (is_ia32_got_reload(irn))
262 classification |= arch_irn_class_reload;
264 return classification;
267 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
268 arch_irn_flags_t flags;
269 ir_node *pred = is_Proj(irn) ? get_Proj_pred(irn) : NULL;
272 flags = arch_irn_flags_ignore;
274 /* pred is only set, if we have a Proj */
275 flags = pred && is_ia32_irn(pred) ? get_ia32_out_flags(pred, get_Proj_proj(irn)) : arch_irn_flags_none;
277 irn = skip_Proj(irn);
278 if (is_ia32_irn(irn))
279 flags |= get_ia32_flags(irn);
286 * The IA32 ABI callback object.
289 be_abi_call_flags_bits_t flags; /**< The call flags. */
290 const arch_isa_t *isa; /**< The ISA handle. */
291 const arch_env_t *aenv; /**< The architecture environment. */
292 ir_graph *irg; /**< The associated graph. */
295 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
296 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
299 static void ia32_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
300 set_ia32_frame_ent(irn, ent);
303 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
305 const ia32_irn_ops_t *ops = self;
307 if (get_ia32_frame_ent(irn)) {
308 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
310 if(is_ia32_Pop(irn)) {
311 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
313 /* Pop nodes modify the stack pointer before calculating the destination
314 * address, so fix this here
320 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
322 snprintf(buf, sizeof(buf), "%d", bias);
324 if (get_ia32_op_type(irn) == ia32_Normal) {
325 set_ia32_cnst(irn, buf);
327 add_ia32_am_offs(irn, buf);
329 set_ia32_am_flavour(irn, am_flav);
334 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
336 long proj = get_Proj_proj(irn);
337 ir_node *pred = get_Proj_pred(irn);
339 if (proj == pn_ia32_Push_stack && is_ia32_Push(pred))
341 if (proj == pn_ia32_Pop_stack && is_ia32_Pop(pred))
349 * Put all registers which are saved by the prologue/epilogue in a set.
351 * @param self The callback object.
352 * @param s The result set.
354 static void ia32_abi_dont_save_regs(void *self, pset *s)
356 ia32_abi_env_t *env = self;
357 if(env->flags.try_omit_fp)
358 pset_insert_ptr(s, env->isa->bp);
362 * Generate the routine prologue.
364 * @param self The callback object.
365 * @param mem A pointer to the mem node. Update this if you define new memory.
366 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
368 * @return The register which shall be used as a stack frame base.
370 * All nodes which define registers in @p reg_map must keep @p reg_map current.
372 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
374 ia32_abi_env_t *env = self;
376 if (! env->flags.try_omit_fp) {
377 ir_node *bl = get_irg_start_block(env->irg);
378 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
379 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
380 ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
384 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
385 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
386 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
388 /* the push must have SP out register */
389 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
390 set_ia32_flags(push, arch_irn_flags_ignore);
392 /* move esp to ebp */
393 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
394 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
395 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
396 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
398 /* beware: the copy must be done before any other sp use */
399 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
400 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
401 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
402 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
404 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
405 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
414 * Generate the routine epilogue.
415 * @param self The callback object.
416 * @param bl The block for the epilog
417 * @param mem A pointer to the mem node. Update this if you define new memory.
418 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
419 * @return The register which shall be used as a stack frame base.
421 * All nodes which define registers in @p reg_map must keep @p reg_map current.
423 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
425 ia32_abi_env_t *env = self;
426 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
427 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
429 if (env->flags.try_omit_fp) {
430 /* simply remove the stack frame here */
431 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
432 add_irn_dep(curr_sp, *mem);
435 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
436 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
438 /* gcc always emits a leave at the end of a routine */
439 if (1 || ARCH_AMD(isa->opt_arch)) {
443 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
444 set_ia32_flags(leave, arch_irn_flags_ignore);
445 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
446 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
447 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
450 ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
453 /* copy ebp to esp */
454 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
457 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
458 set_ia32_flags(pop, arch_irn_flags_ignore);
459 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
460 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
461 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
463 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
464 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
467 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
468 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
472 * Initialize the callback object.
473 * @param call The call object.
474 * @param aenv The architecture environment.
475 * @param irg The graph with the method.
476 * @return Some pointer. This pointer is passed to all other callback functions as self object.
478 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
480 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
481 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
482 env->flags = fl.bits;
485 env->isa = aenv->isa;
490 * Destroy the callback object.
491 * @param self The callback object.
493 static void ia32_abi_done(void *self) {
498 * Produces the type which sits between the stack args and the locals on the stack.
499 * it will contain the return address and space to store the old base pointer.
500 * @return The Firm type modeling the ABI between type.
502 static ir_type *ia32_abi_get_between_type(void *self)
504 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
505 static ir_type *omit_fp_between_type = NULL;
506 static ir_type *between_type = NULL;
508 ia32_abi_env_t *env = self;
510 if ( !between_type) {
512 entity *ret_addr_ent;
513 entity *omit_fp_ret_addr_ent;
515 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_P);
516 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_P);
518 between_type = new_type_struct(IDENT("ia32_between_type"));
519 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
520 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
522 set_entity_offset_bytes(old_bp_ent, 0);
523 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
524 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
525 set_type_state(between_type, layout_fixed);
527 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
528 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
530 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
531 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
532 set_type_state(omit_fp_between_type, layout_fixed);
535 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
540 * Get the estimated cycle count for @p irn.
542 * @param self The this pointer.
543 * @param irn The node.
545 * @return The estimated cycle count for this operation
547 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
550 ia32_op_type_t op_tp;
551 const ia32_irn_ops_t *ops = self;
556 assert(is_ia32_irn(irn));
558 cost = get_ia32_latency(irn);
559 op_tp = get_ia32_op_type(irn);
561 if (is_ia32_CopyB(irn)) {
563 if (ARCH_INTEL(ops->cg->arch))
566 else if (is_ia32_CopyB_i(irn)) {
567 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
568 cost = 20 + (int)ceil((4/3) * size);
569 if (ARCH_INTEL(ops->cg->arch))
572 /* in case of address mode operations add additional cycles */
573 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
575 In case of stack access add 5 cycles (we assume stack is in cache),
576 other memory operations cost 20 cycles.
578 cost += is_ia32_use_frame(irn) ? 5 : 20;
585 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
587 * @param irn The original operation
588 * @param i Index of the argument we want the inverse operation to yield
589 * @param inverse struct to be filled with the resulting inverse op
590 * @param obstack The obstack to use for allocation of the returned nodes array
591 * @return The inverse operation or NULL if operation invertible
593 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
596 ir_node *block, *noreg, *nomem;
599 /* we cannot invert non-ia32 irns */
600 if (! is_ia32_irn(irn))
603 /* operand must always be a real operand (not base, index or mem) */
604 if (i != 2 && i != 3)
607 /* we don't invert address mode operations */
608 if (get_ia32_op_type(irn) != ia32_Normal)
611 irg = get_irn_irg(irn);
612 block = get_nodes_block(irn);
613 mode = get_ia32_res_mode(irn);
614 noreg = get_irn_n(irn, 0);
615 nomem = new_r_NoMem(irg);
617 /* initialize structure */
618 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
622 switch (get_ia32_irn_opcode(irn)) {
624 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
625 /* we have an add with a const here */
626 /* invers == add with negated const */
627 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
628 pnc = pn_ia32_Add_res;
630 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
631 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
632 set_ia32_commutative(inverse->nodes[0]);
634 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
635 /* we have an add with a symconst here */
636 /* invers == sub with const */
637 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
638 pnc = pn_ia32_Sub_res;
640 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
643 /* normal add: inverse == sub */
644 ir_node *proj = ia32_get_res_proj(irn);
647 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
648 pnc = pn_ia32_Sub_res;
653 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
654 /* we have a sub with a const/symconst here */
655 /* invers == add with this const */
656 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
657 pnc = pn_ia32_Add_res;
658 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
659 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
663 ir_node *proj = ia32_get_res_proj(irn);
667 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
670 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
672 pnc = pn_ia32_Sub_res;
677 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
678 /* xor with const: inverse = xor */
679 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
680 pnc = pn_ia32_Eor_res;
681 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
682 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
686 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
687 pnc = pn_ia32_Eor_res;
692 ir_node *proj = ia32_get_res_proj(irn);
695 inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, proj, nomem);
696 pnc = pn_ia32_Not_res;
700 case iro_ia32_Minus: {
701 ir_node *proj = ia32_get_res_proj(irn);
704 inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, proj, nomem);
705 pnc = pn_ia32_Minus_res;
710 /* inverse operation not supported */
714 set_ia32_res_mode(inverse->nodes[0], mode);
715 inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
721 * Check if irn can load it's operand at position i from memory (source addressmode).
722 * @param self Pointer to irn ops itself
723 * @param irn The irn to be checked
724 * @param i The operands position
725 * @return Non-Zero if operand can be loaded
727 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
728 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
729 get_irn_arity(irn) != 5 || /* must be a binary operation */
730 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
731 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
732 (i != 2 && i != 3) || /* a "real" operand position must be requested */
733 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
734 is_ia32_use_frame(irn)) /* must not already use frame */
740 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
741 const ia32_irn_ops_t *ops = self;
742 ia32_code_gen_t *cg = ops->cg;
744 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
747 ir_node *tmp = get_irn_n(irn, 3);
748 set_irn_n(irn, 3, get_irn_n(irn, 2));
749 set_irn_n(irn, 2, tmp);
752 set_ia32_am_support(irn, ia32_am_Source);
753 set_ia32_op_type(irn, ia32_AddrModeS);
754 set_ia32_am_flavour(irn, ia32_B);
755 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
756 set_ia32_use_frame(irn);
757 set_ia32_got_reload(irn);
759 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
760 set_irn_n(irn, 4, spill);
763 Input at position one is index register, which is NoReg.
764 We would need cg object to get a real noreg, but we cannot
767 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
769 //FIXME DBG_OPT_AM_S(reload, irn);
772 static const be_abi_callbacks_t ia32_abi_callbacks = {
775 ia32_abi_get_between_type,
776 ia32_abi_dont_save_regs,
781 /* fill register allocator interface */
783 static const arch_irn_ops_if_t ia32_irn_ops_if = {
784 ia32_get_irn_reg_req,
789 ia32_get_frame_entity,
790 ia32_set_frame_entity,
791 ia32_set_frame_offset,
794 ia32_get_op_estimated_cost,
795 ia32_possible_memory_operand,
796 ia32_perform_memory_operand,
799 ia32_irn_ops_t ia32_irn_ops = {
806 /**************************************************
809 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
810 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
811 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
812 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
815 **************************************************/
817 static void ia32_kill_convs(ia32_code_gen_t *cg) {
820 /* BEWARE: the Projs are inserted in the set */
821 foreach_nodeset(cg->kill_conv, irn) {
822 ir_node *in = get_irn_n(get_Proj_pred(irn), 2);
823 edges_reroute(irn, in, cg->birg->irg);
828 * Transform the Thread Local Store base.
830 static void transform_tls(ir_graph *irg) {
831 ir_node *irn = get_irg_tls(irg);
834 dbg_info *dbg = get_irn_dbg_info(irn);
835 ir_node *blk = get_nodes_block(irn);
837 newn = new_rd_ia32_LdTls(dbg, irg, blk, get_irn_mode(irn));
844 * Transforms the standard firm graph into
847 static void ia32_prepare_graph(void *self) {
848 ia32_code_gen_t *cg = self;
849 dom_front_info_t *dom;
850 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
852 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
854 /* 1st: transform constants and psi condition trees */
855 ia32_pre_transform_phase(cg);
857 /* 2nd: transform all remaining nodes */
858 ia32_register_transformers();
859 dom = be_compute_dominance_frontiers(cg->irg);
861 cg->kill_conv = new_nodeset(5);
862 transform_tls(cg->irg);
863 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
865 del_nodeset(cg->kill_conv);
867 be_free_dominance_frontiers(dom);
870 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
872 /* 3rd: optimize address mode */
873 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
874 ia32_optimize_addressmode(cg);
877 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
879 DEBUG_ONLY(cg->mod = old_mod;)
883 * Dummy functions for hooks we don't need but which must be filled.
885 static void ia32_before_sched(void *self) {
888 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
891 ir_node *mem_proj = NULL;
896 mode = get_irn_mode(irn);
898 /* check if we already saw this node or the node has more than one user */
899 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
903 /* mark irn visited */
904 bitset_add_irn(already_visited, irn);
906 /* non-Tuple nodes with one user: ok, return */
907 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
911 /* tuple node has one user which is not the mem proj-> ok */
912 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
913 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
914 if (mem_proj == NULL) {
919 arity = get_irn_arity(irn);
920 for (i = 0; i < arity; ++i) {
921 ir_node *pred = get_irn_n(irn, i);
923 /* do not follow memory edges or we will accidentally remove stores */
924 if (get_irn_mode(pred) == mode_M) {
925 if(mem_proj != NULL) {
926 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
932 set_irn_n(irn, i, new_Bad());
935 The current node is about to be removed: if the predecessor
936 has only this node as user, it need to be removed as well.
938 if (get_irn_n_edges(pred) <= 1)
939 remove_unused_nodes(pred, already_visited);
942 // we need to set the presd to Bad again to also get the memory edges
943 arity = get_irn_arity(irn);
944 for (i = 0; i < arity; ++i) {
945 set_irn_n(irn, i, new_Bad());
948 if (sched_is_scheduled(irn)) {
953 static void remove_unused_loads_walker(ir_node *irn, void *env) {
954 bitset_t *already_visited = env;
955 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
956 remove_unused_nodes(irn, env);
960 * Called before the register allocator.
961 * Calculate a block schedule here. We need it for the x87
962 * simulator and the emitter.
964 static void ia32_before_ra(void *self) {
965 ia32_code_gen_t *cg = self;
966 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
970 There are sometimes unused loads, only pinned by memory.
971 We need to remove those Loads and all other nodes which won't be used
972 after removing the Load from schedule.
974 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
979 * Transforms a be node into a Load.
981 static void transform_to_Load(ia32_transform_env_t *env) {
982 ir_node *irn = env->irn;
983 entity *ent = be_get_frame_entity(irn);
984 ir_mode *mode = env->mode;
985 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
986 ir_node *nomem = new_rd_NoMem(env->irg);
987 ir_node *sched_point = NULL;
988 ir_node *ptr = get_irn_n(irn, 0);
989 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
990 ir_node *new_op, *proj;
991 const arch_register_t *reg;
993 if (sched_is_scheduled(irn)) {
994 sched_point = sched_prev(irn);
997 if (mode_is_float(mode)) {
998 if (USE_SSE2(env->cg))
999 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1001 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1004 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1006 set_ia32_am_support(new_op, ia32_am_Source);
1007 set_ia32_op_type(new_op, ia32_AddrModeS);
1008 set_ia32_am_flavour(new_op, ia32_B);
1009 set_ia32_ls_mode(new_op, mode);
1010 set_ia32_frame_ent(new_op, ent);
1011 set_ia32_use_frame(new_op);
1013 DBG_OPT_RELOAD2LD(irn, new_op);
1015 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1018 sched_add_after(sched_point, new_op);
1019 sched_add_after(new_op, proj);
1024 /* copy the register from the old node to the new Load */
1025 reg = arch_get_irn_register(env->cg->arch_env, irn);
1026 arch_set_irn_register(env->cg->arch_env, new_op, reg);
1028 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
1030 exchange(irn, proj);
1034 * Transforms a be node into a Store.
1036 static void transform_to_Store(ia32_transform_env_t *env) {
1037 ir_node *irn = env->irn;
1038 entity *ent = be_get_frame_entity(irn);
1039 ir_mode *mode = env->mode;
1040 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1041 ir_node *nomem = new_rd_NoMem(env->irg);
1042 ir_node *ptr = get_irn_n(irn, 0);
1043 ir_node *val = get_irn_n(irn, 1);
1044 ir_node *new_op, *proj;
1045 ir_node *sched_point = NULL;
1047 if (sched_is_scheduled(irn)) {
1048 sched_point = sched_prev(irn);
1051 if (mode_is_float(mode)) {
1052 if (USE_SSE2(env->cg))
1053 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1055 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1057 else if (get_mode_size_bits(mode) == 8) {
1058 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1061 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1064 set_ia32_am_support(new_op, ia32_am_Dest);
1065 set_ia32_op_type(new_op, ia32_AddrModeD);
1066 set_ia32_am_flavour(new_op, ia32_B);
1067 set_ia32_ls_mode(new_op, mode);
1068 set_ia32_frame_ent(new_op, ent);
1069 set_ia32_use_frame(new_op);
1071 DBG_OPT_SPILL2ST(irn, new_op);
1073 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
1076 sched_add_after(sched_point, new_op);
1080 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
1082 exchange(irn, proj);
1085 static ir_node *create_push(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, ir_node *mem, entity *ent) {
1086 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1087 ir_node *frame = get_irg_frame(env->irg);
1089 ir_node *push = new_rd_ia32_Push(env->dbg, env->irg, env->block, frame, noreg, noreg, sp, mem);
1091 set_ia32_frame_ent(push, ent);
1092 set_ia32_use_frame(push);
1093 set_ia32_op_type(push, ia32_AddrModeS);
1094 set_ia32_am_flavour(push, ia32_B);
1095 set_ia32_ls_mode(push, mode_Is);
1097 sched_add_before(schedpoint, push);
1101 static ir_node *create_pop(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, entity *ent) {
1102 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1103 ir_node *frame = get_irg_frame(env->irg);
1105 ir_node *pop = new_rd_ia32_Pop(env->dbg, env->irg, env->block, frame, noreg, sp, new_NoMem());
1107 set_ia32_frame_ent(pop, ent);
1108 set_ia32_use_frame(pop);
1109 set_ia32_op_type(pop, ia32_AddrModeD);
1110 set_ia32_am_flavour(pop, ia32_B);
1111 set_ia32_ls_mode(pop, mode_Is);
1113 sched_add_before(schedpoint, pop);
1118 static ir_node* create_spproj(ia32_transform_env_t *env, ir_node *pred, int pos, ir_node *schedpoint) {
1119 ir_mode *spmode = mode_Iu;
1120 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1123 sp = new_rd_Proj(env->dbg, env->irg, env->block, pred, spmode, pos);
1124 arch_set_irn_register(env->cg->arch_env, sp, spreg);
1125 sched_add_before(schedpoint, sp);
1131 * Transform memperm, currently we do this the ugly way and produce
1132 * push/pop into/from memory cascades. This is possible without using
1135 static void transform_MemPerm(ia32_transform_env_t *env) {
1136 ir_node *node = env->irn;
1138 ir_node *sp = be_abi_get_ignore_irn(env->cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1139 const ir_edge_t *edge;
1140 const ir_edge_t *next;
1143 arity = be_get_MemPerm_entity_arity(node);
1144 pops = alloca(arity * sizeof(pops[0]));
1147 for(i = 0; i < arity; ++i) {
1148 entity *ent = be_get_MemPerm_in_entity(node, i);
1149 ir_type *enttype = get_entity_type(ent);
1150 int entbits = get_type_size_bits(enttype);
1151 ir_node *mem = get_irn_n(node, i + 1);
1154 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1156 push = create_push(env, node, sp, mem, ent);
1157 sp = create_spproj(env, push, 0, node);
1159 // add another push after the first one
1160 push = create_push(env, node, sp, mem, ent);
1161 add_ia32_am_offs_int(push, 4);
1162 sp = create_spproj(env, push, 0, node);
1165 set_irn_n(node, i, new_Bad());
1169 for(i = arity - 1; i >= 0; --i) {
1170 entity *ent = be_get_MemPerm_out_entity(node, i);
1171 ir_type *enttype = get_entity_type(ent);
1172 int entbits = get_type_size_bits(enttype);
1176 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1178 pop = create_pop(env, node, sp, ent);
1180 // add another pop after the first one
1181 sp = create_spproj(env, pop, 1, node);
1182 pop = create_pop(env, node, sp, ent);
1183 add_ia32_am_offs_int(pop, 4);
1185 sp = create_spproj(env, pop, 1, node);
1190 // exchange memprojs
1191 foreach_out_edge_safe(node, edge, next) {
1192 ir_node *proj = get_edge_src_irn(edge);
1193 int p = get_Proj_proj(proj);
1197 set_Proj_pred(proj, pops[p]);
1198 set_Proj_proj(proj, 3);
1202 arity = get_irn_arity(node);
1203 for(i = 0; i < arity; ++i) {
1204 set_irn_n(node, i, new_Bad());
1210 * Fix the mode of Spill/Reload
1212 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
1214 if (mode_is_float(mode)) {
1226 * Block-Walker: Calls the transform functions Spill and Reload.
1228 static void ia32_after_ra_walker(ir_node *block, void *env) {
1229 ir_node *node, *prev;
1230 ia32_code_gen_t *cg = env;
1231 ia32_transform_env_t tenv;
1234 tenv.irg = current_ir_graph;
1236 DEBUG_ONLY(tenv.mod = cg->mod;)
1238 /* beware: the schedule is changed here */
1239 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1240 prev = sched_prev(node);
1241 if (be_is_Reload(node)) {
1242 /* we always reload the whole register */
1243 tenv.dbg = get_irn_dbg_info(node);
1245 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
1246 transform_to_Load(&tenv);
1248 else if (be_is_Spill(node)) {
1249 ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1250 /* we always spill the whole register */
1251 tenv.dbg = get_irn_dbg_info(node);
1253 tenv.mode = fix_spill_mode(cg, get_irn_mode(spillval));
1254 transform_to_Store(&tenv);
1256 else if(be_is_MemPerm(node)) {
1257 tenv.dbg = get_irn_dbg_info(node);
1259 transform_MemPerm(&tenv);
1265 * We transform Spill and Reload here. This needs to be done before
1266 * stack biasing otherwise we would miss the corrected offset for these nodes.
1268 * If x87 instruction should be emitted, run the x87 simulator and patch
1269 * the virtual instructions. This must obviously be done after register allocation.
1271 static void ia32_after_ra(void *self) {
1272 ia32_code_gen_t *cg = self;
1273 ir_graph *irg = cg->irg;
1275 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1277 ia32_finish_irg(irg, cg);
1281 * Last touchups for the graph before emit
1283 static void ia32_finish(void *self) {
1284 ia32_code_gen_t *cg = self;
1285 ir_graph *irg = cg->irg;
1287 //be_remove_empty_blocks(irg);
1288 cg->blk_sched = be_create_block_schedule(irg, cg->birg->execfreqs);
1290 //cg->blk_sched = sched_create_block_schedule(cg->irg, cg->birg->execfreqs);
1292 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1293 if (cg->used_fp == fp_x87 || cg->force_sim) {
1294 x87_simulate_graph(cg->arch_env, irg, cg->blk_sched);
1297 ia32_peephole_optimization(irg, cg);
1301 * Emits the code, closes the output file and frees
1302 * the code generator interface.
1304 static void ia32_codegen(void *self) {
1305 ia32_code_gen_t *cg = self;
1306 ir_graph *irg = cg->irg;
1308 ia32_gen_routine(cg->isa->out, irg, cg);
1312 /* remove it from the isa */
1315 /* de-allocate code generator */
1316 del_set(cg->reg_set);
1320 static void *ia32_cg_init(const be_irg_t *birg);
1322 static const arch_code_generator_if_t ia32_code_gen_if = {
1324 NULL, /* before abi introduce hook */
1326 ia32_before_sched, /* before scheduling hook */
1327 ia32_before_ra, /* before register allocation hook */
1328 ia32_after_ra, /* after register allocation hook */
1329 ia32_finish, /* called before codegen */
1330 ia32_codegen /* emit && done */
1334 * Initializes a IA32 code generator.
1336 static void *ia32_cg_init(const be_irg_t *birg) {
1337 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1338 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1340 cg->impl = &ia32_code_gen_if;
1341 cg->irg = birg->irg;
1342 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1343 cg->arch_env = birg->main_env->arch_env;
1346 cg->blk_sched = NULL;
1347 cg->fp_to_gp = NULL;
1348 cg->gp_to_fp = NULL;
1349 cg->fp_kind = isa->fp_kind;
1350 cg->used_fp = fp_none;
1351 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1353 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1355 /* copy optimizations from isa for easier access */
1357 cg->arch = isa->arch;
1358 cg->opt_arch = isa->opt_arch;
1364 if (isa->name_obst_size) {
1365 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
1366 isa->name_obst_size = 0;
1367 obstack_free(isa->name_obst, NULL);
1368 obstack_init(isa->name_obst);
1372 cur_reg_set = cg->reg_set;
1374 ia32_irn_ops.cg = cg;
1376 return (arch_code_generator_t *)cg;
1381 /*****************************************************************
1382 * ____ _ _ _____ _____
1383 * | _ \ | | | | |_ _|/ ____| /\
1384 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1385 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1386 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1387 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1389 *****************************************************************/
1392 * Set output modes for GCC
1394 static const tarval_mode_info mo_integer = {
1401 * set the tarval output mode of all integer modes to decimal
1403 static void set_tarval_output_modes(void)
1407 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1408 ir_mode *mode = get_irp_mode(i);
1410 if (mode_is_int(mode))
1411 set_tarval_mode_output_option(mode, &mo_integer);
1417 * The template that generates a new ISA object.
1418 * Note that this template can be changed by command line
1421 static ia32_isa_t ia32_isa_template = {
1423 &ia32_isa_if, /* isa interface implementation */
1424 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1425 &ia32_gp_regs[REG_EBP], /* base pointer register */
1426 -1, /* stack direction */
1427 NULL, /* main environment */
1429 NULL, /* 16bit register names */
1430 NULL, /* 8bit register names */
1434 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1435 IA32_OPT_DOAM | /* optimize address mode default: on */
1436 IA32_OPT_LEA | /* optimize for LEAs default: on */
1437 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1438 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1439 IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
1440 arch_pentium_4, /* instruction architecture */
1441 arch_pentium_4, /* optimize for architecture */
1442 fp_sse2, /* use sse2 unit */
1443 NULL, /* current code generator */
1444 NULL, /* output file */
1446 NULL, /* name obstack */
1447 0 /* name obst size */
1452 * Initializes the backend ISA.
1454 static void *ia32_init(FILE *file_handle) {
1455 static int inited = 0;
1461 set_tarval_output_modes();
1463 isa = xmalloc(sizeof(*isa));
1464 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1466 ia32_register_init(isa);
1467 ia32_create_opcodes();
1469 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1470 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1471 /* no SSE2 for these cpu's */
1472 isa->fp_kind = fp_x87;
1474 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1475 /* Pentium 4 don't like inc and dec instructions */
1476 isa->opt &= ~IA32_OPT_INCDEC;
1479 isa->regs_16bit = pmap_create();
1480 isa->regs_8bit = pmap_create();
1481 isa->types = pmap_create();
1482 isa->tv_ent = pmap_create();
1483 isa->out = file_handle;
1485 ia32_build_16bit_reg_map(isa->regs_16bit);
1486 ia32_build_8bit_reg_map(isa->regs_8bit);
1488 /* patch register names of x87 registers */
1490 ia32_st_regs[0].name = "st";
1491 ia32_st_regs[1].name = "st(1)";
1492 ia32_st_regs[2].name = "st(2)";
1493 ia32_st_regs[3].name = "st(3)";
1494 ia32_st_regs[4].name = "st(4)";
1495 ia32_st_regs[5].name = "st(5)";
1496 ia32_st_regs[6].name = "st(6)";
1497 ia32_st_regs[7].name = "st(7)";
1501 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1502 obstack_init(isa->name_obst);
1503 isa->name_obst_size = 0;
1506 ia32_handle_intrinsics();
1507 ia32_switch_section(isa->out, NO_SECTION);
1508 fprintf(isa->out, "\t.intel_syntax\n");
1510 /* needed for the debug support */
1511 ia32_switch_section(isa->out, SECTION_TEXT);
1512 fprintf(isa->out, ".Ltext0:\n");
1522 * Closes the output file and frees the ISA structure.
1524 static void ia32_done(void *self) {
1525 ia32_isa_t *isa = self;
1527 /* emit now all global declarations */
1528 ia32_gen_decls(isa->out, isa->arch_isa.main_env);
1530 pmap_destroy(isa->regs_16bit);
1531 pmap_destroy(isa->regs_8bit);
1532 pmap_destroy(isa->tv_ent);
1533 pmap_destroy(isa->types);
1536 //printf("name obst size = %d bytes\n", isa->name_obst_size);
1537 obstack_free(isa->name_obst, NULL);
1545 * Return the number of register classes for this architecture.
1546 * We report always these:
1547 * - the general purpose registers
1548 * - the SSE floating point register set
1549 * - the virtual floating point registers
1551 static int ia32_get_n_reg_class(const void *self) {
1556 * Return the register class for index i.
1558 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1559 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1561 return &ia32_reg_classes[CLASS_ia32_gp];
1563 return &ia32_reg_classes[CLASS_ia32_xmm];
1565 return &ia32_reg_classes[CLASS_ia32_vfp];
1569 * Get the register class which shall be used to store a value of a given mode.
1570 * @param self The this pointer.
1571 * @param mode The mode in question.
1572 * @return A register class which can hold values of the given mode.
1574 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1575 const ia32_isa_t *isa = self;
1576 if (mode_is_float(mode)) {
1577 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1580 return &ia32_reg_classes[CLASS_ia32_gp];
1584 * Get the ABI restrictions for procedure calls.
1585 * @param self The this pointer.
1586 * @param method_type The type of the method (procedure) in question.
1587 * @param abi The abi object to be modified
1589 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1590 const ia32_isa_t *isa = self;
1593 unsigned cc = get_method_calling_convention(method_type);
1594 int n = get_method_n_params(method_type);
1597 int i, ignore_1, ignore_2;
1599 const arch_register_t *reg;
1600 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1602 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1604 /* set abi flags for calls */
1605 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1606 call_flags.bits.store_args_sequential = use_push;
1607 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1608 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1609 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1611 /* set stack parameter passing style */
1612 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1614 /* collect the mode for each type */
1615 modes = alloca(n * sizeof(modes[0]));
1617 for (i = 0; i < n; i++) {
1618 tp = get_method_param_type(method_type, i);
1619 modes[i] = get_type_mode(tp);
1622 /* set register parameters */
1623 if (cc & cc_reg_param) {
1624 /* determine the number of parameters passed via registers */
1625 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1627 /* loop over all parameters and set the register requirements */
1628 for (i = 0; i <= biggest_n; i++) {
1629 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1630 assert(reg && "kaputt");
1631 be_abi_call_param_reg(abi, i, reg);
1638 /* set stack parameters */
1639 for (i = stack_idx; i < n; i++) {
1640 /* parameters on the stack are 32 bit aligned */
1641 be_abi_call_param_stack(abi, i, 4, 0, 0);
1645 /* set return registers */
1646 n = get_method_n_ress(method_type);
1648 assert(n <= 2 && "more than two results not supported");
1650 /* In case of 64bit returns, we will have two 32bit values */
1652 tp = get_method_res_type(method_type, 0);
1653 mode = get_type_mode(tp);
1655 assert(!mode_is_float(mode) && "two FP results not supported");
1657 tp = get_method_res_type(method_type, 1);
1658 mode = get_type_mode(tp);
1660 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1662 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1663 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1666 const arch_register_t *reg;
1668 tp = get_method_res_type(method_type, 0);
1669 assert(is_atomic_type(tp));
1670 mode = get_type_mode(tp);
1672 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1674 be_abi_call_res_reg(abi, 0, reg);
1679 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1680 return &ia32_irn_ops;
1683 const arch_irn_handler_t ia32_irn_handler = {
1687 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1688 return &ia32_irn_handler;
1691 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1692 return is_ia32_irn(irn) ? 1 : -1;
1696 * Initializes the code generator interface.
1698 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1699 return &ia32_code_gen_if;
1703 * Returns the estimated execution time of an ia32 irn.
1705 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1706 const arch_env_t *arch_env = env;
1707 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1710 list_sched_selector_t ia32_sched_selector;
1713 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1715 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1716 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1717 ia32_sched_selector.exectime = ia32_sched_exectime;
1718 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1719 return &ia32_sched_selector;
1723 * Returns the necessary byte alignment for storing a register of given class.
1725 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1726 ir_mode *mode = arch_register_class_mode(cls);
1727 int bytes = get_mode_size_bytes(mode);
1729 if (mode_is_float(mode) && bytes > 8)
1734 static ia32_intrinsic_env_t intrinsic_env = { NULL, NULL };
1737 * Returns the libFirm configuration parameter for this backend.
1739 static const backend_params *ia32_get_libfirm_params(void) {
1740 static const arch_dep_params_t ad = {
1741 1, /* also use subs */
1742 4, /* maximum shifts */
1743 31, /* maximum shift amount */
1745 1, /* allow Mulhs */
1746 1, /* allow Mulus */
1747 32 /* Mulh allowed up to 32 bit */
1749 static backend_params p = {
1750 NULL, /* no additional opcodes */
1751 NULL, /* will be set later */
1752 1, /* need dword lowering */
1753 ia32_create_intrinsic_fkt,
1754 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1762 /* instruction set architectures. */
1763 static const lc_opt_enum_int_items_t arch_items[] = {
1764 { "386", arch_i386, },
1765 { "486", arch_i486, },
1766 { "pentium", arch_pentium, },
1767 { "586", arch_pentium, },
1768 { "pentiumpro", arch_pentium_pro, },
1769 { "686", arch_pentium_pro, },
1770 { "pentiummmx", arch_pentium_mmx, },
1771 { "pentium2", arch_pentium_2, },
1772 { "p2", arch_pentium_2, },
1773 { "pentium3", arch_pentium_3, },
1774 { "p3", arch_pentium_3, },
1775 { "pentium4", arch_pentium_4, },
1776 { "p4", arch_pentium_4, },
1777 { "pentiumm", arch_pentium_m, },
1778 { "pm", arch_pentium_m, },
1779 { "core", arch_core, },
1781 { "athlon", arch_athlon, },
1782 { "athlon64", arch_athlon_64, },
1783 { "opteron", arch_opteron, },
1787 static lc_opt_enum_int_var_t arch_var = {
1788 &ia32_isa_template.arch, arch_items
1791 static lc_opt_enum_int_var_t opt_arch_var = {
1792 &ia32_isa_template.opt_arch, arch_items
1795 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1797 { "sse2", fp_sse2 },
1801 static lc_opt_enum_int_var_t fp_unit_var = {
1802 &ia32_isa_template.fp_kind, fp_unit_items
1805 static const lc_opt_enum_int_items_t gas_items[] = {
1806 { "linux", ASM_LINUX_GAS },
1807 { "mingw", ASM_MINGW_GAS },
1811 static lc_opt_enum_int_var_t gas_var = {
1812 (int *)&asm_flavour, gas_items
1815 static const lc_opt_table_entry_t ia32_options[] = {
1816 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1817 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1818 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1819 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1820 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1821 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1822 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1823 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1824 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1829 * Register command line options for the ia32 backend.
1833 * ia32-arch=arch create instruction for arch
1834 * ia32-opt=arch optimize for run on arch
1835 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1836 * ia32-incdec optimize for inc/dec
1837 * ia32-noaddrmode do not use address mode
1838 * ia32-nolea do not optimize for LEAs
1839 * ia32-noplacecnst do not place constants,
1840 * ia32-noimmop no operations with immediates
1841 * ia32-noextbb do not use extended basic block scheduling
1842 * ia32-gasmode set the GAS compatibility mode
1844 static void ia32_register_options(lc_opt_entry_t *ent)
1846 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1847 lc_opt_add_table(be_grp_ia32, ia32_options);
1849 #endif /* WITH_LIBCORE */
1851 const arch_isa_if_t ia32_isa_if = {
1854 ia32_get_n_reg_class,
1856 ia32_get_reg_class_for_mode,
1858 ia32_get_irn_handler,
1859 ia32_get_code_generator_if,
1860 ia32_get_list_sched_selector,
1861 ia32_get_reg_class_alignment,
1862 ia32_get_libfirm_params,
1864 ia32_register_options