2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
31 #include "lc_opts_enum.h"
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
46 #include "irdump_grgen.h"
53 #include "iroptimize.h"
54 #include "instrument.h"
57 #include "../beirg_t.h"
58 #include "../benode_t.h"
59 #include "../belower.h"
60 #include "../besched_t.h"
63 #include "../beirgmod.h"
64 #include "../be_dbgout.h"
65 #include "../beblocksched.h"
66 #include "../bemachine.h"
67 #include "../beilpsched.h"
68 #include "../bespillslots.h"
69 #include "../bemodule.h"
70 #include "../begnuas.h"
71 #include "../bestate.h"
72 #include "../beflags.h"
74 #include "bearch_ia32_t.h"
76 #include "ia32_new_nodes.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "gen_ia32_machine.h"
79 #include "ia32_transform.h"
80 #include "ia32_emitter.h"
81 #include "ia32_map_regs.h"
82 #include "ia32_optimize.h"
84 #include "ia32_dbg_stat.h"
85 #include "ia32_finish.h"
86 #include "ia32_util.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
94 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
97 static set *cur_reg_set = NULL;
99 ir_mode *mode_fpcw = NULL;
100 ia32_code_gen_t *ia32_current_cg = NULL;
103 * The environment for the intrinsic mapping.
105 static ia32_intrinsic_env_t intrinsic_env = {
107 NULL, /* the irg, these entities belong to */
108 NULL, /* entity for first div operand (move into FPU) */
109 NULL, /* entity for second div operand (move into FPU) */
110 NULL, /* entity for converts ll -> d */
111 NULL, /* entity for converts d -> ll */
112 NULL, /* entity for __divdi3 library call */
113 NULL, /* entity for __moddi3 library call */
114 NULL, /* entity for __udivdi3 library call */
115 NULL, /* entity for __umoddi3 library call */
116 NULL, /* bias value for conversion from float to unsigned 64 */
120 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
122 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
123 create_const_node_func func,
124 const arch_register_t* reg)
126 ir_node *block, *res;
131 block = get_irg_start_block(cg->irg);
132 res = func(NULL, cg->irg, block);
133 arch_set_irn_register(cg->arch_env, res, reg);
136 add_irn_dep(get_irg_end(cg->irg), res);
137 /* add_irn_dep(get_irg_start(cg->irg), res); */
142 /* Creates the unique per irg GP NoReg node. */
143 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
144 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
145 &ia32_gp_regs[REG_GP_NOREG]);
148 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
149 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
150 &ia32_vfp_regs[REG_VFP_NOREG]);
153 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
154 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
155 &ia32_xmm_regs[REG_XMM_NOREG]);
158 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
159 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
160 &ia32_gp_regs[REG_GP_UKNWN]);
163 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
164 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
165 &ia32_vfp_regs[REG_VFP_UKNWN]);
168 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
169 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
170 &ia32_xmm_regs[REG_XMM_UKNWN]);
173 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
174 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
175 &ia32_fp_cw_regs[REG_FPCW]);
180 * Returns the admissible noreg register node for input register pos of node irn.
182 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
183 const arch_register_req_t *req;
185 req = arch_get_register_req(cg->arch_env, irn, pos);
186 assert(req != NULL && "Missing register requirements");
187 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
188 return ia32_new_NoReg_gp(cg);
190 if (ia32_cg_config.use_sse2) {
191 return ia32_new_NoReg_xmm(cg);
193 return ia32_new_NoReg_vfp(cg);
197 /**************************************************
200 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
201 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
202 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
203 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
206 **************************************************/
209 * Return register requirements for an ia32 node.
210 * If the node returns a tuple (mode_T) then the proj's
211 * will be asked for this information.
213 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
217 ir_mode *mode = get_irn_mode(node);
221 if (mode == mode_X || is_Block(node)) {
222 return arch_no_register_req;
225 if (mode == mode_T && pos < 0) {
226 return arch_no_register_req;
229 node_pos = pos == -1 ? 0 : pos;
231 if (mode == mode_M || pos >= 0) {
232 return arch_no_register_req;
235 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
236 node = skip_Proj_const(node);
239 if (is_ia32_irn(node)) {
240 const arch_register_req_t *req;
242 req = get_ia32_in_req(node, pos);
244 req = get_ia32_out_req(node, node_pos);
251 /* unknowns should be transformed already */
252 assert(!is_Unknown(node));
253 return arch_no_register_req;
256 static void ia32_set_irn_reg(const void *self, ir_node *irn,
257 const arch_register_t *reg)
262 if (get_irn_mode(irn) == mode_X) {
267 pos = get_Proj_proj(irn);
268 irn = skip_Proj(irn);
271 if (is_ia32_irn(irn)) {
272 const arch_register_t **slots;
274 slots = get_ia32_slots(irn);
277 ia32_set_firm_reg(irn, reg, cur_reg_set);
281 static const arch_register_t *ia32_get_irn_reg(const void *self,
285 const arch_register_t *reg = NULL;
290 if (get_irn_mode(irn) == mode_X) {
294 pos = get_Proj_proj(irn);
295 irn = skip_Proj_const(irn);
298 if (is_ia32_irn(irn)) {
299 const arch_register_t **slots;
300 slots = get_ia32_slots(irn);
301 assert(pos < get_ia32_n_res(irn));
304 reg = ia32_get_firm_reg(irn, cur_reg_set);
310 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
311 arch_irn_class_t classification = arch_irn_class_normal;
314 irn = skip_Proj_const(irn);
317 classification |= arch_irn_class_branch;
319 if (! is_ia32_irn(irn))
320 return classification & ~arch_irn_class_normal;
323 classification |= arch_irn_class_load;
326 classification |= arch_irn_class_store;
328 if (is_ia32_need_stackent(irn))
329 classification |= arch_irn_class_reload;
331 return classification;
334 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
335 arch_irn_flags_t flags = arch_irn_flags_none;
339 return arch_irn_flags_ignore;
341 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
342 ir_node *pred = get_Proj_pred(irn);
344 if(is_ia32_irn(pred)) {
345 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
351 if (is_ia32_irn(irn)) {
352 flags |= get_ia32_flags(irn);
359 * The IA32 ABI callback object.
362 be_abi_call_flags_bits_t flags; /**< The call flags. */
363 const arch_isa_t *isa; /**< The ISA handle. */
364 const arch_env_t *aenv; /**< The architecture environment. */
365 ir_graph *irg; /**< The associated graph. */
368 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
370 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
373 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
375 set_ia32_frame_ent(irn, ent);
378 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias)
380 const ia32_irn_ops_t *ops = self;
382 if (get_ia32_frame_ent(irn) == NULL)
385 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
386 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
388 /* Pop nodes modify the stack pointer before calculating the
389 * destination address, so fix this here
394 add_ia32_am_offs_int(irn, bias);
397 static int ia32_get_sp_bias(const void *self, const ir_node *node)
401 if (is_ia32_Push(node))
404 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
411 * Put all registers which are saved by the prologue/epilogue in a set.
413 * @param self The callback object.
414 * @param s The result set.
416 static void ia32_abi_dont_save_regs(void *self, pset *s)
418 ia32_abi_env_t *env = self;
419 if(env->flags.try_omit_fp)
420 pset_insert_ptr(s, env->isa->bp);
424 * Generate the routine prologue.
426 * @param self The callback object.
427 * @param mem A pointer to the mem node. Update this if you define new memory.
428 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
430 * @return The register which shall be used as a stack frame base.
432 * All nodes which define registers in @p reg_map must keep @p reg_map current.
434 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
436 ia32_abi_env_t *env = self;
437 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
438 ia32_code_gen_t *cg = isa->cg;
440 if (! env->flags.try_omit_fp) {
441 ir_node *bl = get_irg_start_block(env->irg);
442 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
443 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
444 ir_node *noreg = ia32_new_NoReg_gp(cg);
447 /* ALL nodes representing bp must be set to ignore. */
448 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
451 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
452 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
453 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
455 /* the push must have SP out register */
456 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
457 set_ia32_flags(push, arch_irn_flags_ignore);
459 /* move esp to ebp */
460 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
461 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
462 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
463 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
465 /* beware: the copy must be done before any other sp use */
466 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
467 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
468 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
469 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
471 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
472 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
481 * Generate the routine epilogue.
482 * @param self The callback object.
483 * @param bl The block for the epilog
484 * @param mem A pointer to the mem node. Update this if you define new memory.
485 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
486 * @return The register which shall be used as a stack frame base.
488 * All nodes which define registers in @p reg_map must keep @p reg_map current.
490 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
492 ia32_abi_env_t *env = self;
493 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
494 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
496 if (env->flags.try_omit_fp) {
497 /* simply remove the stack frame here */
498 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
499 add_irn_dep(curr_sp, *mem);
501 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
502 ir_graph *irg = current_ir_graph;
504 if (ia32_cg_config.use_leave) {
508 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
509 set_ia32_flags(leave, arch_irn_flags_ignore);
510 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
511 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
515 /* the old SP is not needed anymore (kill the proj) */
516 assert(is_Proj(curr_sp));
517 be_kill_node(curr_sp);
519 /* copy ebp to esp */
520 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
521 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
522 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
525 pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
526 set_ia32_flags(pop, arch_irn_flags_ignore);
527 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
528 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
530 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
532 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
533 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
536 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
537 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
541 * Initialize the callback object.
542 * @param call The call object.
543 * @param aenv The architecture environment.
544 * @param irg The graph with the method.
545 * @return Some pointer. This pointer is passed to all other callback functions as self object.
547 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
549 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
550 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
551 env->flags = fl.bits;
554 env->isa = aenv->isa;
559 * Destroy the callback object.
560 * @param self The callback object.
562 static void ia32_abi_done(void *self) {
567 * Produces the type which sits between the stack args and the locals on the stack.
568 * it will contain the return address and space to store the old base pointer.
569 * @return The Firm type modeling the ABI between type.
571 static ir_type *ia32_abi_get_between_type(void *self)
573 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
574 static ir_type *omit_fp_between_type = NULL;
575 static ir_type *between_type = NULL;
577 ia32_abi_env_t *env = self;
579 if (! between_type) {
580 ir_entity *old_bp_ent;
581 ir_entity *ret_addr_ent;
582 ir_entity *omit_fp_ret_addr_ent;
584 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
585 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
587 between_type = new_type_struct(IDENT("ia32_between_type"));
588 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
589 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
591 set_entity_offset(old_bp_ent, 0);
592 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
593 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
594 set_type_state(between_type, layout_fixed);
596 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
597 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
599 set_entity_offset(omit_fp_ret_addr_ent, 0);
600 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
601 set_type_state(omit_fp_between_type, layout_fixed);
604 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
609 * Get the estimated cycle count for @p irn.
611 * @param self The this pointer.
612 * @param irn The node.
614 * @return The estimated cycle count for this operation
616 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
619 ia32_op_type_t op_tp;
624 if (!is_ia32_irn(irn))
627 assert(is_ia32_irn(irn));
629 cost = get_ia32_latency(irn);
630 op_tp = get_ia32_op_type(irn);
632 if (is_ia32_CopyB(irn)) {
635 else if (is_ia32_CopyB_i(irn)) {
636 int size = get_ia32_copyb_size(irn);
637 cost = 20 + (int)ceil((4/3) * size);
639 /* in case of address mode operations add additional cycles */
640 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
642 In case of stack access and access to fixed addresses add 5 cycles
643 (we assume they are in cache), other memory operations cost 20
646 if(is_ia32_use_frame(irn) ||
647 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
648 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
659 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
661 * @param irn The original operation
662 * @param i Index of the argument we want the inverse operation to yield
663 * @param inverse struct to be filled with the resulting inverse op
664 * @param obstack The obstack to use for allocation of the returned nodes array
665 * @return The inverse operation or NULL if operation invertible
667 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
671 ir_node *block, *noreg, *nomem;
675 /* we cannot invert non-ia32 irns */
676 if (! is_ia32_irn(irn))
679 /* operand must always be a real operand (not base, index or mem) */
680 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
683 /* we don't invert address mode operations */
684 if (get_ia32_op_type(irn) != ia32_Normal)
687 /* TODO: adjust for new immediates... */
688 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
692 irg = get_irn_irg(irn);
693 block = get_nodes_block(irn);
694 mode = get_irn_mode(irn);
695 irn_mode = get_irn_mode(irn);
696 noreg = get_irn_n(irn, 0);
697 nomem = new_r_NoMem(irg);
698 dbg = get_irn_dbg_info(irn);
700 /* initialize structure */
701 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
705 switch (get_ia32_irn_opcode(irn)) {
708 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
709 /* we have an add with a const here */
710 /* invers == add with negated const */
711 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
713 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
714 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
715 set_ia32_commutative(inverse->nodes[0]);
717 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
718 /* we have an add with a symconst here */
719 /* invers == sub with const */
720 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
722 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
725 /* normal add: inverse == sub */
726 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
733 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
734 /* we have a sub with a const/symconst here */
735 /* invers == add with this const */
736 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
737 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
738 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
742 if (i == n_ia32_binary_left) {
743 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
746 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
754 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
755 /* xor with const: inverse = xor */
756 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
757 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
758 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
762 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
768 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
773 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
778 /* inverse operation not supported */
785 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
787 if(mode_is_float(mode))
794 * Get the mode that should be used for spilling value node
796 static ir_mode *get_spill_mode(const ir_node *node)
798 ir_mode *mode = get_irn_mode(node);
799 return get_spill_mode_mode(mode);
803 * Checks whether an addressmode reload for a node with mode mode is compatible
804 * with a spillslot of mode spill_mode
806 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
808 if(mode_is_float(mode)) {
809 return mode == spillmode;
816 * Check if irn can load its operand at position i from memory (source addressmode).
817 * @param self Pointer to irn ops itself
818 * @param irn The irn to be checked
819 * @param i The operands position
820 * @return Non-Zero if operand can be loaded
822 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
823 ir_node *op = get_irn_n(irn, i);
824 const ir_mode *mode = get_irn_mode(op);
825 const ir_mode *spillmode = get_spill_mode(op);
829 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
830 ! is_ia32_irn(irn) || /* must be an ia32 irn */
831 get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
832 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
833 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
834 ! ia32_is_spillmode_compatible(mode, spillmode) ||
835 is_ia32_use_frame(irn)) /* must not already use frame */
838 if (i == n_ia32_binary_left) {
839 const arch_register_req_t *req;
840 if(!is_ia32_commutative(irn))
842 /* we can't swap left/right for limited registers
843 * (As this (currently) breaks constraint handling copies)
845 req = get_ia32_in_req(irn, n_ia32_binary_left);
846 if (req->type & arch_register_req_type_limited) {
854 static void ia32_perform_memory_operand(const void *self, ir_node *irn,
855 ir_node *spill, unsigned int i)
857 const ia32_irn_ops_t *ops = self;
859 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
861 if (i == n_ia32_binary_left) {
862 ia32_swap_left_right(irn);
865 set_ia32_op_type(irn, ia32_AddrModeS);
866 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
867 set_ia32_use_frame(irn);
868 set_ia32_need_stackent(irn);
870 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
871 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(ops->cg, irn, n_ia32_binary_right));
872 set_irn_n(irn, n_ia32_mem, spill);
874 /* immediates are only allowed on the right side */
875 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
876 ia32_swap_left_right(irn);
880 static const be_abi_callbacks_t ia32_abi_callbacks = {
883 ia32_abi_get_between_type,
884 ia32_abi_dont_save_regs,
889 /* fill register allocator interface */
891 static const arch_irn_ops_if_t ia32_irn_ops_if = {
892 ia32_get_irn_reg_req,
897 ia32_get_frame_entity,
898 ia32_set_frame_entity,
899 ia32_set_frame_offset,
902 ia32_get_op_estimated_cost,
903 ia32_possible_memory_operand,
904 ia32_perform_memory_operand,
907 static ia32_irn_ops_t ia32_irn_ops = {
914 /**************************************************
917 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
918 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
919 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
920 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
923 **************************************************/
925 static ir_entity *mcount = NULL;
927 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
929 static void ia32_before_abi(void *self) {
930 lower_mode_b_config_t lower_mode_b_config = {
931 mode_Iu, /* lowered mode */
932 mode_Bu, /* prefered mode for set */
933 0, /* don't lower direct compares */
935 ia32_code_gen_t *cg = self;
937 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
939 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
941 if (mcount == NULL) {
942 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
943 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
944 /* FIXME: enter the right ld_ident here */
945 set_entity_ld_ident(mcount, get_entity_ident(mcount));
946 set_entity_visibility(mcount, visibility_external_allocated);
948 instrument_initcall(cg->irg, mcount);
953 * Transforms the standard firm graph into
956 static void ia32_prepare_graph(void *self) {
957 ia32_code_gen_t *cg = self;
959 /* do local optimisations */
960 optimize_graph_df(cg->irg);
962 /* TODO: we often have dead code reachable through out-edges here. So for
963 * now we rebuild edges (as we need correct user count for code selection)
966 edges_deactivate(cg->irg);
967 edges_activate(cg->irg);
971 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
974 /* transform nodes into assembler instructions by PBQP magic */
975 ia32_transform_graph_by_pbqp(cg);
979 be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched);
981 /* transform remaining nodes into assembler instructions */
982 ia32_transform_graph(cg);
984 /* do local optimisations (mainly CSE) */
985 optimize_graph_df(cg->irg);
988 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
990 /* optimize address mode */
991 ia32_optimize_graph(cg);
994 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
996 /* do code placement, to optimize the position of constants */
1000 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
1004 * Dummy functions for hooks we don't need but which must be filled.
1006 static void ia32_before_sched(void *self) {
1010 static void turn_back_am(ir_node *node)
1012 ir_graph *irg = current_ir_graph;
1013 dbg_info *dbgi = get_irn_dbg_info(node);
1014 ir_node *block = get_nodes_block(node);
1015 ir_node *base = get_irn_n(node, n_ia32_base);
1016 ir_node *index = get_irn_n(node, n_ia32_index);
1017 ir_node *mem = get_irn_n(node, n_ia32_mem);
1018 ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
1022 const ir_edge_t *edge;
1024 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1025 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1027 ia32_copy_am_attrs(load, node);
1028 set_irn_n(node, n_ia32_mem, new_NoMem());
1030 switch (get_ia32_am_arity(node)) {
1032 set_irn_n(node, n_ia32_unary_op, load_res);
1035 case ia32_am_binary:
1036 if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
1037 assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
1038 is_ia32_Test(node) || is_ia32_Test8Bit(node));
1039 set_irn_n(node, n_ia32_binary_left, load_res);
1041 set_irn_n(node, n_ia32_binary_right, load_res);
1045 case ia32_am_ternary:
1046 set_irn_n(node, n_ia32_binary_right, load_res);
1051 set_irn_n(node, n_ia32_base, noreg);
1052 set_irn_n(node, n_ia32_index, noreg);
1053 set_ia32_am_offs_int(node, 0);
1054 set_ia32_am_sc(node, NULL);
1055 set_ia32_am_scale(node, 0);
1056 clear_ia32_am_sc_sign(node);
1058 /* rewire mem-proj */
1059 if (get_irn_mode(node) == mode_T) {
1061 foreach_out_edge(node, edge) {
1062 ir_node *out = get_edge_src_irn(edge);
1063 if(get_Proj_proj(out) == pn_ia32_mem) {
1069 if(mem_proj != NULL) {
1070 set_Proj_pred(mem_proj, load);
1071 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1075 set_ia32_op_type(node, ia32_Normal);
1076 if (sched_is_scheduled(node))
1077 sched_add_before(node, load);
1080 static ir_node *flags_remat(ir_node *node, ir_node *after)
1082 /* we should turn back source address mode when rematerializing nodes */
1083 ia32_op_type_t type;
1087 if (is_Block(after)) {
1090 block = get_nodes_block(after);
1093 type = get_ia32_op_type(node);
1095 case ia32_AddrModeS: turn_back_am(node); break;
1097 case ia32_AddrModeD:
1098 /* TODO implement this later... */
1099 panic("found DestAM with flag user %+F this should not happen", node);
1102 default: assert(type == ia32_Normal); break;
1105 copy = exact_copy(node);
1106 set_nodes_block(copy, block);
1107 sched_add_after(after, copy);
1113 * Called before the register allocator.
1114 * Calculate a block schedule here. We need it for the x87
1115 * simulator and the emitter.
1117 static void ia32_before_ra(void *self) {
1118 ia32_code_gen_t *cg = self;
1120 /* setup fpu rounding modes */
1121 ia32_setup_fpu_mode(cg);
1124 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1127 ia32_add_missing_keeps(cg);
1132 * Transforms a be_Reload into a ia32 Load.
1134 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1135 ir_graph *irg = get_irn_irg(node);
1136 dbg_info *dbg = get_irn_dbg_info(node);
1137 ir_node *block = get_nodes_block(node);
1138 ir_entity *ent = be_get_frame_entity(node);
1139 ir_mode *mode = get_irn_mode(node);
1140 ir_mode *spillmode = get_spill_mode(node);
1141 ir_node *noreg = ia32_new_NoReg_gp(cg);
1142 ir_node *sched_point = NULL;
1143 ir_node *ptr = get_irg_frame(irg);
1144 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1145 ir_node *new_op, *proj;
1146 const arch_register_t *reg;
1148 if (sched_is_scheduled(node)) {
1149 sched_point = sched_prev(node);
1152 if (mode_is_float(spillmode)) {
1153 if (ia32_cg_config.use_sse2)
1154 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1156 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1158 else if (get_mode_size_bits(spillmode) == 128) {
1159 /* Reload 128 bit SSE registers */
1160 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1163 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1165 set_ia32_op_type(new_op, ia32_AddrModeS);
1166 set_ia32_ls_mode(new_op, spillmode);
1167 set_ia32_frame_ent(new_op, ent);
1168 set_ia32_use_frame(new_op);
1170 DBG_OPT_RELOAD2LD(node, new_op);
1172 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1175 sched_add_after(sched_point, new_op);
1179 /* copy the register from the old node to the new Load */
1180 reg = arch_get_irn_register(cg->arch_env, node);
1181 arch_set_irn_register(cg->arch_env, new_op, reg);
1183 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1185 exchange(node, proj);
1189 * Transforms a be_Spill node into a ia32 Store.
1191 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1192 ir_graph *irg = get_irn_irg(node);
1193 dbg_info *dbg = get_irn_dbg_info(node);
1194 ir_node *block = get_nodes_block(node);
1195 ir_entity *ent = be_get_frame_entity(node);
1196 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1197 ir_mode *mode = get_spill_mode(spillval);
1198 ir_node *noreg = ia32_new_NoReg_gp(cg);
1199 ir_node *nomem = new_rd_NoMem(irg);
1200 ir_node *ptr = get_irg_frame(irg);
1201 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1203 ir_node *sched_point = NULL;
1205 if (sched_is_scheduled(node)) {
1206 sched_point = sched_prev(node);
1209 /* No need to spill unknown values... */
1210 if(is_ia32_Unknown_GP(val) ||
1211 is_ia32_Unknown_VFP(val) ||
1212 is_ia32_Unknown_XMM(val)) {
1217 exchange(node, store);
1221 if (mode_is_float(mode)) {
1222 if (ia32_cg_config.use_sse2)
1223 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1225 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1226 } else if (get_mode_size_bits(mode) == 128) {
1227 /* Spill 128 bit SSE registers */
1228 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1229 } else if (get_mode_size_bits(mode) == 8) {
1230 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1232 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1235 set_ia32_op_type(store, ia32_AddrModeD);
1236 set_ia32_ls_mode(store, mode);
1237 set_ia32_frame_ent(store, ent);
1238 set_ia32_use_frame(store);
1239 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1240 DBG_OPT_SPILL2ST(node, store);
1243 sched_add_after(sched_point, store);
1247 exchange(node, store);
1250 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1251 ir_graph *irg = get_irn_irg(node);
1252 dbg_info *dbg = get_irn_dbg_info(node);
1253 ir_node *block = get_nodes_block(node);
1254 ir_node *noreg = ia32_new_NoReg_gp(cg);
1255 ir_node *frame = get_irg_frame(irg);
1257 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
1259 set_ia32_frame_ent(push, ent);
1260 set_ia32_use_frame(push);
1261 set_ia32_op_type(push, ia32_AddrModeS);
1262 set_ia32_ls_mode(push, mode_Is);
1264 sched_add_before(schedpoint, push);
1268 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1269 ir_graph *irg = get_irn_irg(node);
1270 dbg_info *dbg = get_irn_dbg_info(node);
1271 ir_node *block = get_nodes_block(node);
1272 ir_node *noreg = ia32_new_NoReg_gp(cg);
1273 ir_node *frame = get_irg_frame(irg);
1275 ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1277 set_ia32_frame_ent(pop, ent);
1278 set_ia32_use_frame(pop);
1279 set_ia32_op_type(pop, ia32_AddrModeD);
1280 set_ia32_ls_mode(pop, mode_Is);
1282 sched_add_before(schedpoint, pop);
1287 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1288 ir_graph *irg = get_irn_irg(node);
1289 dbg_info *dbg = get_irn_dbg_info(node);
1290 ir_node *block = get_nodes_block(node);
1291 ir_mode *spmode = mode_Iu;
1292 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1295 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1296 arch_set_irn_register(cg->arch_env, sp, spreg);
1302 * Transform MemPerm, currently we do this the ugly way and produce
1303 * push/pop into/from memory cascades. This is possible without using
1306 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1307 ir_graph *irg = get_irn_irg(node);
1308 ir_node *block = get_nodes_block(node);
1312 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1313 const ir_edge_t *edge;
1314 const ir_edge_t *next;
1317 arity = be_get_MemPerm_entity_arity(node);
1318 pops = alloca(arity * sizeof(pops[0]));
1321 for(i = 0; i < arity; ++i) {
1322 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1323 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1324 ir_type *enttype = get_entity_type(inent);
1325 unsigned entsize = get_type_size_bytes(enttype);
1326 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1327 ir_node *mem = get_irn_n(node, i + 1);
1330 /* work around cases where entities have different sizes */
1331 if(entsize2 < entsize)
1333 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1335 push = create_push(cg, node, node, sp, mem, inent);
1336 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1338 /* add another push after the first one */
1339 push = create_push(cg, node, node, sp, mem, inent);
1340 add_ia32_am_offs_int(push, 4);
1341 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1344 set_irn_n(node, i, new_Bad());
1348 for(i = arity - 1; i >= 0; --i) {
1349 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1350 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1351 ir_type *enttype = get_entity_type(outent);
1352 unsigned entsize = get_type_size_bytes(enttype);
1353 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1356 /* work around cases where entities have different sizes */
1357 if(entsize2 < entsize)
1359 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1361 pop = create_pop(cg, node, node, sp, outent);
1362 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1364 add_ia32_am_offs_int(pop, 4);
1366 /* add another pop after the first one */
1367 pop = create_pop(cg, node, node, sp, outent);
1368 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1375 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1376 sched_add_before(node, keep);
1378 /* exchange memprojs */
1379 foreach_out_edge_safe(node, edge, next) {
1380 ir_node *proj = get_edge_src_irn(edge);
1381 int p = get_Proj_proj(proj);
1385 set_Proj_pred(proj, pops[p]);
1386 set_Proj_proj(proj, pn_ia32_Pop_M);
1389 /* remove memperm */
1390 arity = get_irn_arity(node);
1391 for(i = 0; i < arity; ++i) {
1392 set_irn_n(node, i, new_Bad());
1398 * Block-Walker: Calls the transform functions Spill and Reload.
1400 static void ia32_after_ra_walker(ir_node *block, void *env) {
1401 ir_node *node, *prev;
1402 ia32_code_gen_t *cg = env;
1404 /* beware: the schedule is changed here */
1405 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1406 prev = sched_prev(node);
1408 if (be_is_Reload(node)) {
1409 transform_to_Load(cg, node);
1410 } else if (be_is_Spill(node)) {
1411 transform_to_Store(cg, node);
1412 } else if (be_is_MemPerm(node)) {
1413 transform_MemPerm(cg, node);
1419 * Collects nodes that need frame entities assigned.
1421 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1423 be_fec_env_t *env = data;
1425 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1426 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1427 int align = get_mode_size_bytes(mode);
1428 be_node_needs_frame_entity(env, node, mode, align);
1429 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1430 && is_ia32_use_frame(node)) {
1431 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1432 const ir_mode *mode = get_ia32_ls_mode(node);
1433 const ia32_attr_t *attr = get_ia32_attr_const(node);
1434 int align = get_mode_size_bytes(mode);
1436 if(attr->data.need_64bit_stackent) {
1439 if(attr->data.need_32bit_stackent) {
1442 be_node_needs_frame_entity(env, node, mode, align);
1443 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1444 || is_ia32_vfld(node)) {
1445 const ir_mode *mode = get_ia32_ls_mode(node);
1447 be_node_needs_frame_entity(env, node, mode, align);
1448 } else if(is_ia32_FldCW(node)) {
1449 /* although 2 byte would be enough 4 byte performs best */
1450 const ir_mode *mode = mode_Iu;
1452 be_node_needs_frame_entity(env, node, mode, align);
1455 assert(is_ia32_St(node) ||
1456 is_ia32_xStoreSimple(node) ||
1457 is_ia32_vfst(node) ||
1458 is_ia32_vfist(node) ||
1459 is_ia32_vfisttp(node) ||
1460 is_ia32_FnstCW(node));
1467 * We transform Spill and Reload here. This needs to be done before
1468 * stack biasing otherwise we would miss the corrected offset for these nodes.
1470 static void ia32_after_ra(void *self) {
1471 ia32_code_gen_t *cg = self;
1472 ir_graph *irg = cg->irg;
1473 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1475 /* create and coalesce frame entities */
1476 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1477 be_assign_entities(fec_env);
1478 be_free_frame_entity_coalescer(fec_env);
1480 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1484 * Last touchups for the graph before emit: x87 simulation to replace the
1485 * virtual with real x87 instructions, creating a block schedule and peephole
1488 static void ia32_finish(void *self) {
1489 ia32_code_gen_t *cg = self;
1490 ir_graph *irg = cg->irg;
1492 ia32_finish_irg(irg, cg);
1494 /* we might have to rewrite x87 virtual registers */
1495 if (cg->do_x87_sim) {
1496 x87_simulate_graph(cg->arch_env, cg->birg);
1499 /* do peephole optimisations */
1500 ia32_peephole_optimization(cg);
1502 /* create block schedule, this also removes empty blocks which might
1503 * produce critical edges */
1504 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1508 * Emits the code, closes the output file and frees
1509 * the code generator interface.
1511 static void ia32_codegen(void *self) {
1512 ia32_code_gen_t *cg = self;
1513 ir_graph *irg = cg->irg;
1515 ia32_gen_routine(cg, irg);
1519 /* remove it from the isa */
1522 assert(ia32_current_cg == cg);
1523 ia32_current_cg = NULL;
1525 /* de-allocate code generator */
1526 del_set(cg->reg_set);
1531 * Returns the node representing the PIC base.
1533 static ir_node *ia32_get_pic_base(void *self) {
1535 ia32_code_gen_t *cg = self;
1536 ir_node *get_eip = cg->get_eip;
1537 if (get_eip != NULL)
1540 block = get_irg_start_block(cg->irg);
1541 get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
1542 cg->get_eip = get_eip;
1544 add_irn_dep(get_eip, get_irg_frame(cg->irg));
1549 static void *ia32_cg_init(be_irg_t *birg);
1551 static const arch_code_generator_if_t ia32_code_gen_if = {
1553 ia32_get_pic_base, /* return node used as base in pic code addresses */
1554 ia32_before_abi, /* before abi introduce hook */
1557 ia32_before_sched, /* before scheduling hook */
1558 ia32_before_ra, /* before register allocation hook */
1559 ia32_after_ra, /* after register allocation hook */
1560 ia32_finish, /* called before codegen */
1561 ia32_codegen /* emit && done */
1565 * Initializes a IA32 code generator.
1567 static void *ia32_cg_init(be_irg_t *birg) {
1568 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env.isa;
1569 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1571 cg->impl = &ia32_code_gen_if;
1572 cg->irg = birg->irg;
1573 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1574 cg->arch_env = &birg->main_env->arch_env;
1577 cg->blk_sched = NULL;
1578 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1579 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1582 /* Linux gprof implementation needs base pointer */
1583 birg->main_env->options->omit_fp = 0;
1590 if (isa->name_obst) {
1591 obstack_free(isa->name_obst, NULL);
1592 obstack_init(isa->name_obst);
1596 cur_reg_set = cg->reg_set;
1598 ia32_irn_ops.cg = cg;
1600 assert(ia32_current_cg == NULL);
1601 ia32_current_cg = cg;
1603 return (arch_code_generator_t *)cg;
1608 /*****************************************************************
1609 * ____ _ _ _____ _____
1610 * | _ \ | | | | |_ _|/ ____| /\
1611 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1612 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1613 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1614 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1616 *****************************************************************/
1619 * Set output modes for GCC
1621 static const tarval_mode_info mo_integer = {
1628 * set the tarval output mode of all integer modes to decimal
1630 static void set_tarval_output_modes(void)
1634 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1635 ir_mode *mode = get_irp_mode(i);
1637 if (mode_is_int(mode))
1638 set_tarval_mode_output_option(mode, &mo_integer);
1642 const arch_isa_if_t ia32_isa_if;
1645 * The template that generates a new ISA object.
1646 * Note that this template can be changed by command line
1649 static ia32_isa_t ia32_isa_template = {
1651 &ia32_isa_if, /* isa interface implementation */
1652 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1653 &ia32_gp_regs[REG_EBP], /* base pointer register */
1654 -1, /* stack direction */
1655 16, /* stack alignment */
1656 NULL, /* main environment */
1657 7, /* costs for a spill instruction */
1658 5, /* costs for a reload instruction */
1660 NULL, /* 16bit register names */
1661 NULL, /* 8bit register names */
1662 NULL, /* 8bit register names high */
1665 NULL, /* current code generator */
1666 NULL, /* abstract machine */
1668 NULL, /* name obstack */
1673 * Initializes the backend ISA.
1675 static void *ia32_init(FILE *file_handle) {
1676 static int inited = 0;
1683 set_tarval_output_modes();
1685 isa = xmalloc(sizeof(*isa));
1686 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1688 if(mode_fpcw == NULL) {
1689 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1692 ia32_register_init();
1693 ia32_create_opcodes();
1695 be_emit_init(file_handle);
1696 isa->regs_16bit = pmap_create();
1697 isa->regs_8bit = pmap_create();
1698 isa->regs_8bit_high = pmap_create();
1699 isa->types = pmap_create();
1700 isa->tv_ent = pmap_create();
1701 isa->cpu = ia32_init_machine_description();
1703 ia32_build_16bit_reg_map(isa->regs_16bit);
1704 ia32_build_8bit_reg_map(isa->regs_8bit);
1705 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1708 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1709 obstack_init(isa->name_obst);
1712 /* enter the ISA object into the intrinsic environment */
1713 intrinsic_env.isa = isa;
1714 ia32_handle_intrinsics();
1716 /* needed for the debug support */
1717 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1718 be_emit_cstring(".Ltext0:\n");
1719 be_emit_write_line();
1721 /* we mark referenced global entities, so we can only emit those which
1722 * are actually referenced. (Note: you mustn't use the type visited flag
1723 * elsewhere in the backend)
1725 inc_master_type_visited();
1733 * Closes the output file and frees the ISA structure.
1735 static void ia32_done(void *self) {
1736 ia32_isa_t *isa = self;
1738 /* emit now all global declarations */
1739 be_gas_emit_decls(isa->arch_isa.main_env, 1);
1741 pmap_destroy(isa->regs_16bit);
1742 pmap_destroy(isa->regs_8bit);
1743 pmap_destroy(isa->regs_8bit_high);
1744 pmap_destroy(isa->tv_ent);
1745 pmap_destroy(isa->types);
1748 obstack_free(isa->name_obst, NULL);
1758 * Return the number of register classes for this architecture.
1759 * We report always these:
1760 * - the general purpose registers
1761 * - the SSE floating point register set
1762 * - the virtual floating point registers
1763 * - the SSE vector register set
1765 static unsigned ia32_get_n_reg_class(const void *self) {
1771 * Return the register class for index i.
1773 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1777 assert(i < N_CLASSES);
1778 return &ia32_reg_classes[i];
1782 * Get the register class which shall be used to store a value of a given mode.
1783 * @param self The this pointer.
1784 * @param mode The mode in question.
1785 * @return A register class which can hold values of the given mode.
1787 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1788 const ir_mode *mode)
1792 if (mode_is_float(mode)) {
1793 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1796 return &ia32_reg_classes[CLASS_ia32_gp];
1800 * Get the ABI restrictions for procedure calls.
1801 * @param self The this pointer.
1802 * @param method_type The type of the method (procedure) in question.
1803 * @param abi The abi object to be modified
1805 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1812 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1815 /* set abi flags for calls */
1816 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1817 call_flags.bits.store_args_sequential = 0;
1818 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1819 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1820 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1822 /* set parameter passing style */
1823 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1825 if (get_method_variadicity(method_type) == variadicity_variadic) {
1826 /* pass all parameters of a variadic function on the stack */
1829 cc = get_method_calling_convention(method_type);
1830 if (get_method_additional_properties(method_type) & mtp_property_private
1831 && (ia32_cg_config.optimize_cc)) {
1832 /* set the calling conventions to register parameter */
1833 cc = (cc & ~cc_bits) | cc_reg_param;
1837 /* we have to pop the shadow parameter ourself for compound calls */
1838 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1839 && !(cc & cc_reg_param)) {
1840 be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
1843 n = get_method_n_params(method_type);
1844 for (i = regnum = 0; i < n; i++) {
1846 const arch_register_t *reg = NULL;
1848 tp = get_method_param_type(method_type, i);
1849 mode = get_type_mode(tp);
1851 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1854 be_abi_call_param_reg(abi, i, reg);
1857 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1858 * movl has a shorter opcode than mov[sz][bw]l */
1859 ir_mode *load_mode = mode;
1860 if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
1861 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1865 /* set return registers */
1866 n = get_method_n_ress(method_type);
1868 assert(n <= 2 && "more than two results not supported");
1870 /* In case of 64bit returns, we will have two 32bit values */
1872 tp = get_method_res_type(method_type, 0);
1873 mode = get_type_mode(tp);
1875 assert(!mode_is_float(mode) && "two FP results not supported");
1877 tp = get_method_res_type(method_type, 1);
1878 mode = get_type_mode(tp);
1880 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1882 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1883 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1886 const arch_register_t *reg;
1888 tp = get_method_res_type(method_type, 0);
1889 assert(is_atomic_type(tp));
1890 mode = get_type_mode(tp);
1892 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1894 be_abi_call_res_reg(abi, 0, reg);
1899 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
1904 return &ia32_irn_ops;
1907 const arch_irn_handler_t ia32_irn_handler = {
1911 const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
1914 return &ia32_irn_handler;
1917 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1921 if(!is_ia32_irn(irn)) {
1925 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1926 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1927 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1928 || is_ia32_Immediate(irn))
1935 * Initializes the code generator interface.
1937 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1940 return &ia32_code_gen_if;
1944 * Returns the estimated execution time of an ia32 irn.
1946 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1947 const arch_env_t *arch_env = env;
1948 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1951 list_sched_selector_t ia32_sched_selector;
1954 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1956 static const list_sched_selector_t *ia32_get_list_sched_selector(
1957 const void *self, list_sched_selector_t *selector)
1960 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1961 ia32_sched_selector.exectime = ia32_sched_exectime;
1962 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1963 return &ia32_sched_selector;
1966 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1973 * Returns the necessary byte alignment for storing a register of given class.
1975 static int ia32_get_reg_class_alignment(const void *self,
1976 const arch_register_class_t *cls)
1978 ir_mode *mode = arch_register_class_mode(cls);
1979 int bytes = get_mode_size_bytes(mode);
1982 if (mode_is_float(mode) && bytes > 8)
1987 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1988 const void *self, const ir_node *irn)
1990 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1991 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1992 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1995 static const be_execution_unit_t *_allowed_units_GP[] = {
1996 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1997 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1998 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1999 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2000 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2001 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2002 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2005 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2006 &be_machine_execution_units_DUMMY[0],
2009 static const be_execution_unit_t **_units_callret[] = {
2010 _allowed_units_BRANCH,
2013 static const be_execution_unit_t **_units_other[] = {
2017 static const be_execution_unit_t **_units_dummy[] = {
2018 _allowed_units_DUMMY,
2021 const be_execution_unit_t ***ret;
2024 if (is_ia32_irn(irn)) {
2025 ret = get_ia32_exec_units(irn);
2027 else if (is_be_node(irn)) {
2028 if (be_is_Call(irn) || be_is_Return(irn)) {
2029 ret = _units_callret;
2031 else if (be_is_Barrier(irn)) {
2046 * Return the abstract ia32 machine.
2048 static const be_machine_t *ia32_get_machine(const void *self) {
2049 const ia32_isa_t *isa = self;
2054 * Return irp irgs in the desired order.
2056 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2064 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2065 * @return 1 if allowed, 0 otherwise
2067 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2075 if(!ia32_cg_config.use_cmov) {
2076 /* TODO: we could still handle abs(x)... */
2080 /* we can't handle psis with 64bit compares yet */
2082 ir_node *pred = get_Proj_pred(sel);
2084 ir_node *left = get_Cmp_left(pred);
2085 ir_mode *cmp_mode = get_irn_mode(left);
2086 if(!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2091 /* check the Phi nodes */
2092 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2093 ir_mode *mode = get_irn_mode(phi);
2095 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2103 * Returns the libFirm configuration parameter for this backend.
2105 static const backend_params *ia32_get_libfirm_params(void) {
2106 static const ir_settings_if_conv_t ifconv = {
2107 4, /* maxdepth, doesn't matter for Psi-conversion */
2108 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2110 static const ir_settings_arch_dep_t ad = {
2111 1, /* also use subs */
2112 4, /* maximum shifts */
2113 31, /* maximum shift amount */
2114 ia32_evaluate_insn, /* evaluate the instruction sequence */
2116 1, /* allow Mulhs */
2117 1, /* allow Mulus */
2118 32 /* Mulh allowed up to 32 bit */
2120 static backend_params p = {
2121 1, /* need dword lowering */
2122 1, /* support inline assembly */
2123 NULL, /* no additional opcodes */
2124 NULL, /* will be set later */
2125 ia32_create_intrinsic_fkt,
2126 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2127 NULL, /* will be set below */
2130 ia32_setup_cg_config();
2133 p.if_conv_info = &ifconv;
2137 static const lc_opt_enum_int_items_t gas_items[] = {
2138 { "elf", GAS_FLAVOUR_ELF },
2139 { "mingw", GAS_FLAVOUR_MINGW },
2140 { "yasm", GAS_FLAVOUR_YASM },
2141 { "macho", GAS_FLAVOUR_MACH_O },
2145 static lc_opt_enum_int_var_t gas_var = {
2146 (int*) &be_gas_flavour, gas_items
2149 static const lc_opt_table_entry_t ia32_options[] = {
2150 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2151 LC_OPT_ENT_INT("stackalign", "set stack alignment for calls",
2152 &ia32_isa_template.arch_isa.stack_alignment),
2156 const arch_isa_if_t ia32_isa_if = {
2159 ia32_get_n_reg_class,
2161 ia32_get_reg_class_for_mode,
2163 ia32_get_irn_handler,
2164 ia32_get_code_generator_if,
2165 ia32_get_list_sched_selector,
2166 ia32_get_ilp_sched_selector,
2167 ia32_get_reg_class_alignment,
2168 ia32_get_libfirm_params,
2169 ia32_get_allowed_execution_units,
2174 void ia32_init_emitter(void);
2175 void ia32_init_finish(void);
2176 void ia32_init_optimize(void);
2177 void ia32_init_transform(void);
2178 void ia32_init_x87(void);
2180 void be_init_arch_ia32(void)
2182 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2183 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2185 lc_opt_add_table(ia32_grp, ia32_options);
2186 be_register_isa_if("ia32", &ia32_isa_if);
2188 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2190 ia32_init_emitter();
2192 ia32_init_optimize();
2193 ia32_init_transform();
2195 ia32_init_architecture();
2198 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);