2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
10 #include <libcore/lc_opts.h>
11 #include <libcore/lc_opts_enum.h>
15 #include "pseudo_irg.h"
19 #include "iredges_t.h"
33 #include "../benode_t.h"
34 #include "../belower.h"
35 #include "../besched_t.h"
38 #include "../beirgmod.h"
39 #include "../be_dbgout.h"
40 #include "../beblocksched.h"
41 #include "../bemachine.h"
42 #include "../beilpsched.h"
43 #include "../bespillslots.h"
44 #include "../bemodule.h"
45 #include "../begnuas.h"
46 #include "../bestate.h"
48 #include "bearch_ia32_t.h"
50 #include "ia32_new_nodes.h"
51 #include "gen_ia32_regalloc_if.h"
52 #include "gen_ia32_machine.h"
53 #include "ia32_transform.h"
54 #include "ia32_emitter.h"
55 #include "ia32_map_regs.h"
56 #include "ia32_optimize.h"
58 #include "ia32_dbg_stat.h"
59 #include "ia32_finish.h"
60 #include "ia32_util.h"
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
66 static set *cur_reg_set = NULL;
68 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
70 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
71 create_const_node_func func,
79 block = get_irg_start_block(cg->irg);
80 res = func(NULL, cg->irg, block);
81 arch_set_irn_register(cg->arch_env, res, reg);
85 /* keep the node so it isn't accidently removed when unused ... */
87 keep = be_new_Keep(arch_register_get_class(reg), cg->irg, block, 1, in);
89 add_irn_dep(get_irg_end(cg->irg), res);
90 /* add_irn_dep(get_irg_start(cg->irg), res); */
95 /* Creates the unique per irg GP NoReg node. */
96 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
97 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
98 &ia32_gp_regs[REG_GP_NOREG]);
101 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
102 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
103 &ia32_vfp_regs[REG_VFP_NOREG]);
106 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
107 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
108 &ia32_xmm_regs[REG_XMM_NOREG]);
111 /* Creates the unique per irg FP NoReg node. */
112 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
113 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
116 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
117 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
118 &ia32_gp_regs[REG_GP_UKNWN]);
121 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
122 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
123 &ia32_vfp_regs[REG_VFP_UKNWN]);
126 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
127 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
128 &ia32_xmm_regs[REG_XMM_UKNWN]);
131 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
132 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
133 &ia32_fp_cw_regs[REG_FPCW]);
138 * Returns gp_noreg or fp_noreg, depending in input requirements.
140 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
141 const arch_register_req_t *req;
143 req = arch_get_register_req(cg->arch_env, irn, pos);
144 assert(req != NULL && "Missing register requirements");
145 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
146 return ia32_new_NoReg_gp(cg);
148 return ia32_new_NoReg_fp(cg);
151 /**************************************************
154 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
155 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
156 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
157 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
160 **************************************************/
163 * Return register requirements for an ia32 node.
164 * If the node returns a tuple (mode_T) then the proj's
165 * will be asked for this information.
167 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
170 long node_pos = pos == -1 ? 0 : pos;
171 ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
173 if (is_Block(node) || mode == mode_X) {
174 return arch_no_register_req;
177 if (mode == mode_T && pos < 0) {
178 return arch_no_register_req;
183 return arch_no_register_req;
186 return arch_no_register_req;
189 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
190 node = skip_Proj_const(node);
193 if (is_ia32_irn(node)) {
194 const arch_register_req_t *req;
196 req = get_ia32_in_req(node, pos);
198 req = get_ia32_out_req(node, node_pos);
205 /* unknowns should be transformed already */
206 assert(!is_Unknown(node));
208 return arch_no_register_req;
211 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
214 if (get_irn_mode(irn) == mode_X) {
219 pos = get_Proj_proj(irn);
220 irn = skip_Proj(irn);
223 if (is_ia32_irn(irn)) {
224 const arch_register_t **slots;
226 slots = get_ia32_slots(irn);
229 ia32_set_firm_reg(irn, reg, cur_reg_set);
233 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
235 const arch_register_t *reg = NULL;
239 if (get_irn_mode(irn) == mode_X) {
243 pos = get_Proj_proj(irn);
244 irn = skip_Proj_const(irn);
247 if (is_ia32_irn(irn)) {
248 const arch_register_t **slots;
249 slots = get_ia32_slots(irn);
252 reg = ia32_get_firm_reg(irn, cur_reg_set);
258 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
259 arch_irn_class_t classification = arch_irn_class_normal;
261 irn = skip_Proj_const(irn);
264 classification |= arch_irn_class_branch;
266 if (! is_ia32_irn(irn))
267 return classification & ~arch_irn_class_normal;
269 if (is_ia32_Cnst(irn))
270 classification |= arch_irn_class_const;
273 classification |= arch_irn_class_load;
275 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
276 classification |= arch_irn_class_store;
278 if (is_ia32_need_stackent(irn))
279 classification |= arch_irn_class_reload;
281 return classification;
284 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
285 arch_irn_flags_t flags = arch_irn_flags_none;
288 return arch_irn_flags_ignore;
290 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
291 ir_node *pred = get_Proj_pred(irn);
293 if(is_ia32_irn(pred)) {
294 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
300 if (is_ia32_irn(irn)) {
301 flags |= get_ia32_flags(irn);
308 * The IA32 ABI callback object.
311 be_abi_call_flags_bits_t flags; /**< The call flags. */
312 const arch_isa_t *isa; /**< The ISA handle. */
313 const arch_env_t *aenv; /**< The architecture environment. */
314 ir_graph *irg; /**< The associated graph. */
317 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
318 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
321 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
322 set_ia32_frame_ent(irn, ent);
325 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
326 const ia32_irn_ops_t *ops = self;
328 if (get_ia32_frame_ent(irn)) {
329 ia32_am_flavour_t am_flav;
331 if (is_ia32_Pop(irn)) {
332 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
334 /* Pop nodes modify the stack pointer before calculating the destination
335 * address, so fix this here
341 am_flav = get_ia32_am_flavour(irn);
343 set_ia32_am_flavour(irn, am_flav);
345 add_ia32_am_offs_int(irn, bias);
349 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
351 long proj = get_Proj_proj(irn);
352 ir_node *pred = get_Proj_pred(irn);
354 if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack)
356 if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack)
364 * Put all registers which are saved by the prologue/epilogue in a set.
366 * @param self The callback object.
367 * @param s The result set.
369 static void ia32_abi_dont_save_regs(void *self, pset *s)
371 ia32_abi_env_t *env = self;
372 if(env->flags.try_omit_fp)
373 pset_insert_ptr(s, env->isa->bp);
377 * Generate the routine prologue.
379 * @param self The callback object.
380 * @param mem A pointer to the mem node. Update this if you define new memory.
381 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
383 * @return The register which shall be used as a stack frame base.
385 * All nodes which define registers in @p reg_map must keep @p reg_map current.
387 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
389 ia32_abi_env_t *env = self;
390 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
391 ia32_code_gen_t *cg = isa->cg;
393 if (! env->flags.try_omit_fp) {
394 ir_node *bl = get_irg_start_block(env->irg);
395 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
396 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
397 ir_node *noreg = ia32_new_NoReg_gp(cg);
401 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
402 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
403 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
405 /* the push must have SP out register */
406 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
407 set_ia32_flags(push, arch_irn_flags_ignore);
409 /* move esp to ebp */
410 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
411 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
412 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
413 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
415 /* beware: the copy must be done before any other sp use */
416 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
417 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
418 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
419 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
421 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
422 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
431 * Generate the routine epilogue.
432 * @param self The callback object.
433 * @param bl The block for the epilog
434 * @param mem A pointer to the mem node. Update this if you define new memory.
435 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
436 * @return The register which shall be used as a stack frame base.
438 * All nodes which define registers in @p reg_map must keep @p reg_map current.
440 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
442 ia32_abi_env_t *env = self;
443 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
444 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
446 if (env->flags.try_omit_fp) {
447 /* simply remove the stack frame here */
448 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
449 add_irn_dep(curr_sp, *mem);
451 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
452 ia32_code_gen_t *cg = isa->cg;
453 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
455 /* gcc always emits a leave at the end of a routine */
456 if (1 || ARCH_AMD(isa->opt_arch)) {
460 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
461 set_ia32_flags(leave, arch_irn_flags_ignore);
462 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
463 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
465 ir_node *noreg = ia32_new_NoReg_gp(cg);
468 /* copy ebp to esp */
469 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
472 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
473 set_ia32_flags(pop, arch_irn_flags_ignore);
474 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
475 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
477 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
479 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
480 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
483 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
484 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
488 * Initialize the callback object.
489 * @param call The call object.
490 * @param aenv The architecture environment.
491 * @param irg The graph with the method.
492 * @return Some pointer. This pointer is passed to all other callback functions as self object.
494 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
496 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
497 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
498 env->flags = fl.bits;
501 env->isa = aenv->isa;
506 * Destroy the callback object.
507 * @param self The callback object.
509 static void ia32_abi_done(void *self) {
514 * Produces the type which sits between the stack args and the locals on the stack.
515 * it will contain the return address and space to store the old base pointer.
516 * @return The Firm type modeling the ABI between type.
518 static ir_type *ia32_abi_get_between_type(void *self)
520 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
521 static ir_type *omit_fp_between_type = NULL;
522 static ir_type *between_type = NULL;
524 ia32_abi_env_t *env = self;
526 if (! between_type) {
527 ir_entity *old_bp_ent;
528 ir_entity *ret_addr_ent;
529 ir_entity *omit_fp_ret_addr_ent;
531 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
532 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
534 between_type = new_type_struct(IDENT("ia32_between_type"));
535 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
536 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
538 set_entity_offset(old_bp_ent, 0);
539 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
540 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
541 set_type_state(between_type, layout_fixed);
543 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
544 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
546 set_entity_offset(omit_fp_ret_addr_ent, 0);
547 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
548 set_type_state(omit_fp_between_type, layout_fixed);
551 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
556 * Get the estimated cycle count for @p irn.
558 * @param self The this pointer.
559 * @param irn The node.
561 * @return The estimated cycle count for this operation
563 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
566 ia32_op_type_t op_tp;
567 const ia32_irn_ops_t *ops = self;
571 if (!is_ia32_irn(irn))
574 assert(is_ia32_irn(irn));
576 cost = get_ia32_latency(irn);
577 op_tp = get_ia32_op_type(irn);
579 if (is_ia32_CopyB(irn)) {
581 if (ARCH_INTEL(ops->cg->arch))
584 else if (is_ia32_CopyB_i(irn)) {
585 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
586 cost = 20 + (int)ceil((4/3) * size);
587 if (ARCH_INTEL(ops->cg->arch))
590 /* in case of address mode operations add additional cycles */
591 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
593 In case of stack access add 5 cycles (we assume stack is in cache),
594 other memory operations cost 20 cycles.
596 cost += is_ia32_use_frame(irn) ? 5 : 20;
603 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
605 * @param irn The original operation
606 * @param i Index of the argument we want the inverse operation to yield
607 * @param inverse struct to be filled with the resulting inverse op
608 * @param obstack The obstack to use for allocation of the returned nodes array
609 * @return The inverse operation or NULL if operation invertible
611 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
615 ir_node *block, *noreg, *nomem;
618 /* we cannot invert non-ia32 irns */
619 if (! is_ia32_irn(irn))
622 /* operand must always be a real operand (not base, index or mem) */
623 if (i != 2 && i != 3)
626 /* we don't invert address mode operations */
627 if (get_ia32_op_type(irn) != ia32_Normal)
630 irg = get_irn_irg(irn);
631 block = get_nodes_block(irn);
632 mode = get_irn_mode(irn);
633 irn_mode = get_irn_mode(irn);
634 noreg = get_irn_n(irn, 0);
635 nomem = new_r_NoMem(irg);
636 dbg = get_irn_dbg_info(irn);
638 /* initialize structure */
639 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
643 switch (get_ia32_irn_opcode(irn)) {
645 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
646 /* we have an add with a const here */
647 /* invers == add with negated const */
648 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
650 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
651 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
652 set_ia32_commutative(inverse->nodes[0]);
654 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
655 /* we have an add with a symconst here */
656 /* invers == sub with const */
657 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
659 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
662 /* normal add: inverse == sub */
663 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
668 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
669 /* we have a sub with a const/symconst here */
670 /* invers == add with this const */
671 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
672 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
673 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
678 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
681 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
687 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
688 /* xor with const: inverse = xor */
689 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
690 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
691 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
695 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
700 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
705 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
710 /* inverse operation not supported */
717 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
719 if(mode_is_float(mode))
726 * Get the mode that should be used for spilling value node
728 static ir_mode *get_spill_mode(const ir_node *node)
730 ir_mode *mode = get_irn_mode(node);
731 return get_spill_mode_mode(mode);
735 * Checks wether an addressmode reload for a node with mode mode is compatible
736 * with a spillslot of mode spill_mode
738 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
740 if(mode_is_float(mode)) {
741 return mode == spillmode;
748 * Check if irn can load it's operand at position i from memory (source addressmode).
749 * @param self Pointer to irn ops itself
750 * @param irn The irn to be checked
751 * @param i The operands position
752 * @return Non-Zero if operand can be loaded
754 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
755 ir_node *op = get_irn_n(irn, i);
756 const ir_mode *mode = get_irn_mode(op);
757 const ir_mode *spillmode = get_spill_mode(op);
759 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
760 get_irn_arity(irn) != 5 || /* must be a binary operation */
761 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
762 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
763 ! ia32_is_spillmode_compatible(mode, spillmode) ||
764 (i != 2 && i != 3) || /* a "real" operand position must be requested */
765 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
766 is_ia32_use_frame(irn)) /* must not already use frame */
772 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
773 const ia32_irn_ops_t *ops = self;
774 ia32_code_gen_t *cg = ops->cg;
776 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
779 ir_node *tmp = get_irn_n(irn, 3);
780 set_irn_n(irn, 3, get_irn_n(irn, 2));
781 set_irn_n(irn, 2, tmp);
784 set_ia32_am_support(irn, ia32_am_Source);
785 set_ia32_op_type(irn, ia32_AddrModeS);
786 set_ia32_am_flavour(irn, ia32_B);
787 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
788 set_ia32_use_frame(irn);
789 set_ia32_need_stackent(irn);
791 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
792 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
793 set_irn_n(irn, 4, spill);
795 //FIXME DBG_OPT_AM_S(reload, irn);
798 static const be_abi_callbacks_t ia32_abi_callbacks = {
801 ia32_abi_get_between_type,
802 ia32_abi_dont_save_regs,
807 /* fill register allocator interface */
809 static const arch_irn_ops_if_t ia32_irn_ops_if = {
810 ia32_get_irn_reg_req,
815 ia32_get_frame_entity,
816 ia32_set_frame_entity,
817 ia32_set_frame_offset,
820 ia32_get_op_estimated_cost,
821 ia32_possible_memory_operand,
822 ia32_perform_memory_operand,
825 ia32_irn_ops_t ia32_irn_ops = {
832 /**************************************************
835 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
836 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
837 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
838 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
841 **************************************************/
844 * Transforms the standard firm graph into
847 static void ia32_prepare_graph(void *self) {
848 ia32_code_gen_t *cg = self;
850 /* transform psi condition trees */
851 ia32_pre_transform_phase(cg);
853 /* transform all remaining nodes */
854 ia32_transform_graph(cg);
855 //add_fpu_edges(cg->birg);
857 // Matze: disabled for now. Because after transformation start block has no
858 // self-loop anymore so it might be merged with its successor block. This
859 // will bring several nodes to the startblock which sometimes get scheduled
860 // before the initial IncSP/Barrier
861 local_optimize_graph(cg->irg);
864 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
866 /* optimize address mode */
867 ia32_optimize_addressmode(cg);
870 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
872 /* do code placement, to optimize the position of constants */
876 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
880 * Dummy functions for hooks we don't need but which must be filled.
882 static void ia32_before_sched(void *self) {
885 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
888 ir_node *mem_proj = NULL;
893 mode = get_irn_mode(irn);
895 /* check if we already saw this node or the node has more than one user */
896 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
900 /* mark irn visited */
901 bitset_add_irn(already_visited, irn);
903 /* non-Tuple nodes with one user: ok, return */
904 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
908 /* tuple node has one user which is not the mem proj-> ok */
909 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
910 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
911 if (mem_proj == NULL) {
916 arity = get_irn_arity(irn);
917 for (i = 0; i < arity; ++i) {
918 ir_node *pred = get_irn_n(irn, i);
920 /* do not follow memory edges or we will accidentally remove stores */
921 if (get_irn_mode(pred) == mode_M) {
922 if(mem_proj != NULL) {
923 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
929 set_irn_n(irn, i, new_Bad());
932 The current node is about to be removed: if the predecessor
933 has only this node as user, it need to be removed as well.
935 if (get_irn_n_edges(pred) <= 1)
936 remove_unused_nodes(pred, already_visited);
939 // we need to set the presd to Bad again to also get the memory edges
940 arity = get_irn_arity(irn);
941 for (i = 0; i < arity; ++i) {
942 set_irn_n(irn, i, new_Bad());
945 if (sched_is_scheduled(irn)) {
950 static void remove_unused_loads_walker(ir_node *irn, void *env) {
951 bitset_t *already_visited = env;
952 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
953 remove_unused_nodes(irn, env);
957 * Called before the register allocator.
958 * Calculate a block schedule here. We need it for the x87
959 * simulator and the emitter.
961 static void ia32_before_ra(void *self) {
962 ia32_code_gen_t *cg = self;
963 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
967 There are sometimes unused loads, only pinned by memory.
968 We need to remove those Loads and all other nodes which won't be used
969 after removing the Load from schedule.
971 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
973 /* setup fpu rounding modes */
974 ia32_setup_fpu_mode(cg);
979 * Transforms a be_Reload into a ia32 Load.
981 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
982 ir_graph *irg = get_irn_irg(node);
983 dbg_info *dbg = get_irn_dbg_info(node);
984 ir_node *block = get_nodes_block(node);
985 ir_entity *ent = be_get_frame_entity(node);
986 ir_mode *mode = get_irn_mode(node);
987 ir_mode *spillmode = get_spill_mode(node);
988 ir_node *noreg = ia32_new_NoReg_gp(cg);
989 ir_node *sched_point = NULL;
990 ir_node *ptr = get_irg_frame(irg);
991 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
992 ir_node *new_op, *proj;
993 const arch_register_t *reg;
995 if (sched_is_scheduled(node)) {
996 sched_point = sched_prev(node);
999 if (mode_is_float(spillmode)) {
1001 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
1003 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem);
1005 else if (get_mode_size_bits(spillmode) == 128) {
1006 // Reload 128 bit sse registers
1007 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1010 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1012 set_ia32_am_support(new_op, ia32_am_Source);
1013 set_ia32_op_type(new_op, ia32_AddrModeS);
1014 set_ia32_am_flavour(new_op, ia32_B);
1015 set_ia32_ls_mode(new_op, spillmode);
1016 set_ia32_frame_ent(new_op, ent);
1017 set_ia32_use_frame(new_op);
1019 DBG_OPT_RELOAD2LD(node, new_op);
1021 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1024 sched_add_after(sched_point, new_op);
1025 sched_add_after(new_op, proj);
1030 /* copy the register from the old node to the new Load */
1031 reg = arch_get_irn_register(cg->arch_env, node);
1032 arch_set_irn_register(cg->arch_env, new_op, reg);
1034 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1036 exchange(node, proj);
1040 * Transforms a be_Spill node into a ia32 Store.
1042 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1043 ir_graph *irg = get_irn_irg(node);
1044 dbg_info *dbg = get_irn_dbg_info(node);
1045 ir_node *block = get_nodes_block(node);
1046 ir_entity *ent = be_get_frame_entity(node);
1047 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1048 ir_mode *mode = get_spill_mode(spillval);
1049 ir_node *noreg = ia32_new_NoReg_gp(cg);
1050 ir_node *nomem = new_rd_NoMem(irg);
1051 ir_node *ptr = get_irg_frame(irg);
1052 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1054 ir_node *sched_point = NULL;
1056 if (sched_is_scheduled(node)) {
1057 sched_point = sched_prev(node);
1060 /* No need to spill unknown values... */
1061 if(is_ia32_Unknown_GP(val) ||
1062 is_ia32_Unknown_VFP(val) ||
1063 is_ia32_Unknown_XMM(val)) {
1068 exchange(node, store);
1072 if (mode_is_float(mode)) {
1074 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
1076 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem);
1078 else if (get_mode_size_bits(mode) == 128) {
1079 // Spill 128 bit SSE registers
1080 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, val, nomem);
1082 else if (get_mode_size_bits(mode) == 8) {
1083 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
1086 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
1089 set_ia32_am_support(store, ia32_am_Dest);
1090 set_ia32_op_type(store, ia32_AddrModeD);
1091 set_ia32_am_flavour(store, ia32_B);
1092 set_ia32_ls_mode(store, mode);
1093 set_ia32_frame_ent(store, ent);
1094 set_ia32_use_frame(store);
1095 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1096 DBG_OPT_SPILL2ST(node, store);
1099 sched_add_after(sched_point, store);
1103 exchange(node, store);
1106 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1107 ir_graph *irg = get_irn_irg(node);
1108 dbg_info *dbg = get_irn_dbg_info(node);
1109 ir_node *block = get_nodes_block(node);
1110 ir_node *noreg = ia32_new_NoReg_gp(cg);
1111 ir_node *frame = get_irg_frame(irg);
1113 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
1115 set_ia32_frame_ent(push, ent);
1116 set_ia32_use_frame(push);
1117 set_ia32_op_type(push, ia32_AddrModeS);
1118 set_ia32_am_flavour(push, ia32_B);
1119 set_ia32_ls_mode(push, mode_Is);
1121 sched_add_before(schedpoint, push);
1125 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1126 ir_graph *irg = get_irn_irg(node);
1127 dbg_info *dbg = get_irn_dbg_info(node);
1128 ir_node *block = get_nodes_block(node);
1129 ir_node *noreg = ia32_new_NoReg_gp(cg);
1130 ir_node *frame = get_irg_frame(irg);
1132 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
1134 set_ia32_frame_ent(pop, ent);
1135 set_ia32_use_frame(pop);
1136 set_ia32_op_type(pop, ia32_AddrModeD);
1137 set_ia32_am_flavour(pop, ia32_am_OB);
1138 set_ia32_ls_mode(pop, mode_Is);
1140 sched_add_before(schedpoint, pop);
1145 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos, ir_node *schedpoint) {
1146 ir_graph *irg = get_irn_irg(node);
1147 dbg_info *dbg = get_irn_dbg_info(node);
1148 ir_node *block = get_nodes_block(node);
1149 ir_mode *spmode = mode_Iu;
1150 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1153 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1154 arch_set_irn_register(cg->arch_env, sp, spreg);
1155 sched_add_before(schedpoint, sp);
1161 * Transform memperm, currently we do this the ugly way and produce
1162 * push/pop into/from memory cascades. This is possible without using
1165 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1166 ir_graph *irg = get_irn_irg(node);
1167 ir_node *block = get_nodes_block(node);
1171 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1172 const ir_edge_t *edge;
1173 const ir_edge_t *next;
1176 arity = be_get_MemPerm_entity_arity(node);
1177 pops = alloca(arity * sizeof(pops[0]));
1180 for(i = 0; i < arity; ++i) {
1181 ir_entity *ent = be_get_MemPerm_in_entity(node, i);
1182 ir_type *enttype = get_entity_type(ent);
1183 int entbits = get_type_size_bits(enttype);
1184 ir_node *mem = get_irn_n(node, i + 1);
1187 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1189 push = create_push(cg, node, node, sp, mem, ent);
1190 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1192 // add another push after the first one
1193 push = create_push(cg, node, node, sp, mem, ent);
1194 add_ia32_am_offs_int(push, 4);
1195 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1198 set_irn_n(node, i, new_Bad());
1202 for(i = arity - 1; i >= 0; --i) {
1203 ir_entity *ent = be_get_MemPerm_out_entity(node, i);
1204 ir_type *enttype = get_entity_type(ent);
1205 int entbits = get_type_size_bits(enttype);
1209 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1211 pop = create_pop(cg, node, node, sp, ent);
1212 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1214 add_ia32_am_offs_int(pop, 4);
1216 // add another pop after the first one
1217 pop = create_pop(cg, node, node, sp, ent);
1218 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1225 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1226 sched_add_before(node, keep);
1228 // exchange memprojs
1229 foreach_out_edge_safe(node, edge, next) {
1230 ir_node *proj = get_edge_src_irn(edge);
1231 int p = get_Proj_proj(proj);
1235 set_Proj_pred(proj, pops[p]);
1236 set_Proj_proj(proj, 3);
1240 arity = get_irn_arity(node);
1241 for(i = 0; i < arity; ++i) {
1242 set_irn_n(node, i, new_Bad());
1248 * Block-Walker: Calls the transform functions Spill and Reload.
1250 static void ia32_after_ra_walker(ir_node *block, void *env) {
1251 ir_node *node, *prev;
1252 ia32_code_gen_t *cg = env;
1254 /* beware: the schedule is changed here */
1255 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1256 prev = sched_prev(node);
1258 if (be_is_Reload(node)) {
1259 transform_to_Load(cg, node);
1260 } else if (be_is_Spill(node)) {
1261 transform_to_Store(cg, node);
1262 } else if(be_is_MemPerm(node)) {
1263 transform_MemPerm(cg, node);
1269 * Collects nodes that need frame entities assigned.
1271 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1273 be_fec_env_t *env = data;
1275 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1276 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1277 int align = get_mode_size_bytes(mode);
1278 be_node_needs_frame_entity(env, node, mode, align);
1279 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1280 && is_ia32_use_frame(node)) {
1281 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1282 const ir_mode *mode = get_ia32_ls_mode(node);
1283 int align = get_mode_size_bytes(mode);
1284 be_node_needs_frame_entity(env, node, mode, align);
1285 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)) {
1286 const ir_mode *mode = get_ia32_ls_mode(node);
1288 be_node_needs_frame_entity(env, node, mode, align);
1289 } else if(is_ia32_FldCW(node)) {
1290 const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
1292 be_node_needs_frame_entity(env, node, mode, align);
1293 } else if (is_ia32_SetST0(node)) {
1294 const ir_mode *mode = get_ia32_ls_mode(node);
1296 be_node_needs_frame_entity(env, node, mode, align);
1299 if(!is_ia32_Store(node)
1300 && !is_ia32_xStore(node)
1301 && !is_ia32_xStoreSimple(node)
1302 && !is_ia32_vfist(node)
1303 && !is_ia32_GetST0(node)
1304 && !is_ia32_FnstCW(node)) {
1313 * We transform Spill and Reload here. This needs to be done before
1314 * stack biasing otherwise we would miss the corrected offset for these nodes.
1316 static void ia32_after_ra(void *self) {
1317 ia32_code_gen_t *cg = self;
1318 ir_graph *irg = cg->irg;
1319 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1321 /* create and coalesce frame entities */
1322 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1323 be_assign_entities(fec_env);
1324 be_free_frame_entity_coalescer(fec_env);
1326 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1328 ia32_finish_irg(irg, cg);
1332 * Last touchups for the graph before emit: x87 simulation to replace the
1333 * virtual with real x87 instructions, creating a block schedule and peephole
1336 static void ia32_finish(void *self) {
1337 ia32_code_gen_t *cg = self;
1338 ir_graph *irg = cg->irg;
1340 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1341 if (cg->used_fp == fp_x87 || cg->force_sim) {
1342 x87_simulate_graph(cg->arch_env, cg->birg);
1345 /* create block schedule, this also removes empty blocks which might
1346 * produce critical edges */
1347 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1349 /* do peephole optimisations */
1350 ia32_peephole_optimization(irg, cg);
1354 * Emits the code, closes the output file and frees
1355 * the code generator interface.
1357 static void ia32_codegen(void *self) {
1358 ia32_code_gen_t *cg = self;
1359 ir_graph *irg = cg->irg;
1361 ia32_gen_routine(cg, irg);
1365 /* remove it from the isa */
1368 /* de-allocate code generator */
1369 del_set(cg->reg_set);
1373 static void *ia32_cg_init(be_irg_t *birg);
1375 static const arch_code_generator_if_t ia32_code_gen_if = {
1377 NULL, /* before abi introduce hook */
1380 ia32_before_sched, /* before scheduling hook */
1381 ia32_before_ra, /* before register allocation hook */
1382 ia32_after_ra, /* after register allocation hook */
1383 ia32_finish, /* called before codegen */
1384 ia32_codegen /* emit && done */
1388 * Initializes a IA32 code generator.
1390 static void *ia32_cg_init(be_irg_t *birg) {
1391 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1392 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1394 cg->impl = &ia32_code_gen_if;
1395 cg->irg = birg->irg;
1396 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1397 cg->arch_env = birg->main_env->arch_env;
1400 cg->blk_sched = NULL;
1401 cg->fp_kind = isa->fp_kind;
1402 cg->used_fp = fp_none;
1403 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1405 /* copy optimizations from isa for easier access */
1407 cg->arch = isa->arch;
1408 cg->opt_arch = isa->opt_arch;
1414 if (isa->name_obst) {
1415 obstack_free(isa->name_obst, NULL);
1416 obstack_init(isa->name_obst);
1420 cur_reg_set = cg->reg_set;
1422 ia32_irn_ops.cg = cg;
1424 return (arch_code_generator_t *)cg;
1429 /*****************************************************************
1430 * ____ _ _ _____ _____
1431 * | _ \ | | | | |_ _|/ ____| /\
1432 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1433 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1434 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1435 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1437 *****************************************************************/
1440 * Set output modes for GCC
1442 static const tarval_mode_info mo_integer = {
1449 * set the tarval output mode of all integer modes to decimal
1451 static void set_tarval_output_modes(void)
1455 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1456 ir_mode *mode = get_irp_mode(i);
1458 if (mode_is_int(mode))
1459 set_tarval_mode_output_option(mode, &mo_integer);
1463 const arch_isa_if_t ia32_isa_if;
1466 * The template that generates a new ISA object.
1467 * Note that this template can be changed by command line
1470 static ia32_isa_t ia32_isa_template = {
1472 &ia32_isa_if, /* isa interface implementation */
1473 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1474 &ia32_gp_regs[REG_EBP], /* base pointer register */
1475 -1, /* stack direction */
1476 NULL, /* main environment */
1478 { NULL, }, /* emitter environment */
1479 NULL, /* 16bit register names */
1480 NULL, /* 8bit register names */
1484 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1485 IA32_OPT_DOAM | /* optimize address mode default: on */
1486 IA32_OPT_LEA | /* optimize for LEAs default: on */
1487 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1488 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1489 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1490 arch_pentium_4, /* instruction architecture */
1491 arch_pentium_4, /* optimize for architecture */
1492 fp_sse2, /* use sse2 unit */
1493 NULL, /* current code generator */
1495 NULL, /* name obstack */
1496 0 /* name obst size */
1501 * Initializes the backend ISA.
1503 static void *ia32_init(FILE *file_handle) {
1504 static int inited = 0;
1511 set_tarval_output_modes();
1513 isa = xmalloc(sizeof(*isa));
1514 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1516 ia32_register_init(isa);
1517 ia32_create_opcodes();
1518 ia32_register_copy_attr_func();
1520 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1521 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1522 /* no SSE2 for these cpu's */
1523 isa->fp_kind = fp_x87;
1525 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1526 /* Pentium 4 don't like inc and dec instructions */
1527 isa->opt &= ~IA32_OPT_INCDEC;
1530 be_emit_init_env(&isa->emit, file_handle);
1531 isa->regs_16bit = pmap_create();
1532 isa->regs_8bit = pmap_create();
1533 isa->types = pmap_create();
1534 isa->tv_ent = pmap_create();
1535 isa->cpu = ia32_init_machine_description();
1537 ia32_build_16bit_reg_map(isa->regs_16bit);
1538 ia32_build_8bit_reg_map(isa->regs_8bit);
1540 /* patch register names of x87 registers */
1541 ia32_st_regs[0].name = "st";
1542 ia32_st_regs[1].name = "st(1)";
1543 ia32_st_regs[2].name = "st(2)";
1544 ia32_st_regs[3].name = "st(3)";
1545 ia32_st_regs[4].name = "st(4)";
1546 ia32_st_regs[5].name = "st(5)";
1547 ia32_st_regs[6].name = "st(6)";
1548 ia32_st_regs[7].name = "st(7)";
1551 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1552 obstack_init(isa->name_obst);
1555 ia32_handle_intrinsics();
1557 /* needed for the debug support */
1558 be_gas_emit_switch_section(&isa->emit, GAS_SECTION_TEXT);
1559 be_emit_cstring(&isa->emit, ".Ltext0:\n");
1560 be_emit_write_line(&isa->emit);
1562 /* we mark referenced global entities, so we can only emit those which
1563 * are actually referenced. (Note: you mustn't use the type visited flag
1564 * elsewhere in the backend)
1566 inc_master_type_visited();
1574 * Closes the output file and frees the ISA structure.
1576 static void ia32_done(void *self) {
1577 ia32_isa_t *isa = self;
1579 /* emit now all global declarations */
1580 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
1582 pmap_destroy(isa->regs_16bit);
1583 pmap_destroy(isa->regs_8bit);
1584 pmap_destroy(isa->tv_ent);
1585 pmap_destroy(isa->types);
1588 obstack_free(isa->name_obst, NULL);
1591 be_emit_destroy_env(&isa->emit);
1598 * Return the number of register classes for this architecture.
1599 * We report always these:
1600 * - the general purpose registers
1601 * - the SSE floating point register set
1602 * - the virtual floating point registers
1603 * - the SSE vector register set
1605 static int ia32_get_n_reg_class(const void *self) {
1610 * Return the register class for index i.
1612 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i)
1614 assert(i >= 0 && i < N_CLASSES);
1615 return &ia32_reg_classes[i];
1619 * Get the register class which shall be used to store a value of a given mode.
1620 * @param self The this pointer.
1621 * @param mode The mode in question.
1622 * @return A register class which can hold values of the given mode.
1624 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1625 const ia32_isa_t *isa = self;
1626 if (mode_is_float(mode)) {
1627 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1630 return &ia32_reg_classes[CLASS_ia32_gp];
1634 * Get the ABI restrictions for procedure calls.
1635 * @param self The this pointer.
1636 * @param method_type The type of the method (procedure) in question.
1637 * @param abi The abi object to be modified
1639 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1640 const ia32_isa_t *isa = self;
1643 unsigned cc = get_method_calling_convention(method_type);
1644 int n = get_method_n_params(method_type);
1647 int i, ignore_1, ignore_2;
1649 const arch_register_t *reg;
1650 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1652 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1654 /* set abi flags for calls */
1655 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1656 call_flags.bits.store_args_sequential = use_push;
1657 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1658 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1659 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1661 /* set stack parameter passing style */
1662 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1664 /* collect the mode for each type */
1665 modes = alloca(n * sizeof(modes[0]));
1667 for (i = 0; i < n; i++) {
1668 tp = get_method_param_type(method_type, i);
1669 modes[i] = get_type_mode(tp);
1672 /* set register parameters */
1673 if (cc & cc_reg_param) {
1674 /* determine the number of parameters passed via registers */
1675 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1677 /* loop over all parameters and set the register requirements */
1678 for (i = 0; i <= biggest_n; i++) {
1679 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1680 assert(reg && "kaputt");
1681 be_abi_call_param_reg(abi, i, reg);
1688 /* set stack parameters */
1689 for (i = stack_idx; i < n; i++) {
1690 /* parameters on the stack are 32 bit aligned */
1691 be_abi_call_param_stack(abi, i, 4, 0, 0);
1695 /* set return registers */
1696 n = get_method_n_ress(method_type);
1698 assert(n <= 2 && "more than two results not supported");
1700 /* In case of 64bit returns, we will have two 32bit values */
1702 tp = get_method_res_type(method_type, 0);
1703 mode = get_type_mode(tp);
1705 assert(!mode_is_float(mode) && "two FP results not supported");
1707 tp = get_method_res_type(method_type, 1);
1708 mode = get_type_mode(tp);
1710 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1712 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1713 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1716 const arch_register_t *reg;
1718 tp = get_method_res_type(method_type, 0);
1719 assert(is_atomic_type(tp));
1720 mode = get_type_mode(tp);
1722 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1724 be_abi_call_res_reg(abi, 0, reg);
1729 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1730 return &ia32_irn_ops;
1733 const arch_irn_handler_t ia32_irn_handler = {
1737 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1738 return &ia32_irn_handler;
1741 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1742 if(!is_ia32_irn(irn))
1745 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1746 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1747 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn))
1754 * Initializes the code generator interface.
1756 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1757 return &ia32_code_gen_if;
1761 * Returns the estimated execution time of an ia32 irn.
1763 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1764 const arch_env_t *arch_env = env;
1765 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1768 list_sched_selector_t ia32_sched_selector;
1771 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1773 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1774 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1775 ia32_sched_selector.exectime = ia32_sched_exectime;
1776 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1777 return &ia32_sched_selector;
1780 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
1785 * Returns the necessary byte alignment for storing a register of given class.
1787 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1788 ir_mode *mode = arch_register_class_mode(cls);
1789 int bytes = get_mode_size_bytes(mode);
1791 if (mode_is_float(mode) && bytes > 8)
1796 static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
1797 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1798 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1799 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1802 static const be_execution_unit_t *_allowed_units_GP[] = {
1803 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1804 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1805 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1806 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1807 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1808 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1809 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1812 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1813 &be_machine_execution_units_DUMMY[0],
1816 static const be_execution_unit_t **_units_callret[] = {
1817 _allowed_units_BRANCH,
1820 static const be_execution_unit_t **_units_other[] = {
1824 static const be_execution_unit_t **_units_dummy[] = {
1825 _allowed_units_DUMMY,
1828 const be_execution_unit_t ***ret;
1830 if (is_ia32_irn(irn)) {
1831 ret = get_ia32_exec_units(irn);
1833 else if (is_be_node(irn)) {
1834 if (be_is_Call(irn) || be_is_Return(irn)) {
1835 ret = _units_callret;
1837 else if (be_is_Barrier(irn)) {
1852 * Return the abstract ia32 machine.
1854 static const be_machine_t *ia32_get_machine(const void *self) {
1855 const ia32_isa_t *isa = self;
1860 * Return irp irgs in the desired order.
1862 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) {
1867 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1868 * @return 1 if allowed, 0 otherwise
1870 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1872 ir_node *cmp, *cmp_a, *phi;
1875 /* we don't want long long an floating point Psi */
1876 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
1878 if (get_irn_mode(sel) != mode_b)
1881 cmp = get_Proj_pred(sel);
1882 cmp_a = get_Cmp_left(cmp);
1883 mode = get_irn_mode(cmp_a);
1885 if (IS_BAD_PSI_MODE(mode))
1888 /* check the Phi nodes */
1889 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1890 ir_node *pred_i = get_irn_n(phi, i);
1891 ir_node *pred_j = get_irn_n(phi, j);
1892 ir_mode *mode_i = get_irn_mode(pred_i);
1893 ir_mode *mode_j = get_irn_mode(pred_j);
1895 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1899 #undef IS_BAD_PSI_MODE
1904 static ia32_intrinsic_env_t intrinsic_env = {
1905 NULL, /**< the irg, these entities belong to */
1906 NULL, /**< entity for first div operand (move into FPU) */
1907 NULL, /**< entity for second div operand (move into FPU) */
1908 NULL, /**< entity for converts ll -> d */
1909 NULL, /**< entity for converts d -> ll */
1913 * Returns the libFirm configuration parameter for this backend.
1915 static const backend_params *ia32_get_libfirm_params(void) {
1916 static const opt_if_conv_info_t ifconv = {
1917 4, /* maxdepth, doesn't matter for Psi-conversion */
1918 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
1920 static const arch_dep_params_t ad = {
1921 1, /* also use subs */
1922 4, /* maximum shifts */
1923 31, /* maximum shift amount */
1925 1, /* allow Mulhs */
1926 1, /* allow Mulus */
1927 32 /* Mulh allowed up to 32 bit */
1929 static backend_params p = {
1930 NULL, /* no additional opcodes */
1931 NULL, /* will be set later */
1932 1, /* need dword lowering */
1933 ia32_create_intrinsic_fkt,
1934 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1935 NULL, /* will be set later */
1939 p.if_conv_info = &ifconv;
1943 /* instruction set architectures. */
1944 static const lc_opt_enum_int_items_t arch_items[] = {
1945 { "386", arch_i386, },
1946 { "486", arch_i486, },
1947 { "pentium", arch_pentium, },
1948 { "586", arch_pentium, },
1949 { "pentiumpro", arch_pentium_pro, },
1950 { "686", arch_pentium_pro, },
1951 { "pentiummmx", arch_pentium_mmx, },
1952 { "pentium2", arch_pentium_2, },
1953 { "p2", arch_pentium_2, },
1954 { "pentium3", arch_pentium_3, },
1955 { "p3", arch_pentium_3, },
1956 { "pentium4", arch_pentium_4, },
1957 { "p4", arch_pentium_4, },
1958 { "pentiumm", arch_pentium_m, },
1959 { "pm", arch_pentium_m, },
1960 { "core", arch_core, },
1962 { "athlon", arch_athlon, },
1963 { "athlon64", arch_athlon_64, },
1964 { "opteron", arch_opteron, },
1968 static lc_opt_enum_int_var_t arch_var = {
1969 &ia32_isa_template.arch, arch_items
1972 static lc_opt_enum_int_var_t opt_arch_var = {
1973 &ia32_isa_template.opt_arch, arch_items
1976 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1978 { "sse2", fp_sse2 },
1982 static lc_opt_enum_int_var_t fp_unit_var = {
1983 &ia32_isa_template.fp_kind, fp_unit_items
1986 static const lc_opt_enum_int_items_t gas_items[] = {
1987 { "normal", GAS_FLAVOUR_NORMAL },
1988 { "mingw", GAS_FLAVOUR_MINGW },
1992 static lc_opt_enum_int_var_t gas_var = {
1993 (int*) &be_gas_flavour, gas_items
1996 static const lc_opt_table_entry_t ia32_options[] = {
1997 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1998 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1999 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
2000 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
2001 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
2002 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
2003 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
2004 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
2005 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2009 const arch_isa_if_t ia32_isa_if = {
2012 ia32_get_n_reg_class,
2014 ia32_get_reg_class_for_mode,
2016 ia32_get_irn_handler,
2017 ia32_get_code_generator_if,
2018 ia32_get_list_sched_selector,
2019 ia32_get_ilp_sched_selector,
2020 ia32_get_reg_class_alignment,
2021 ia32_get_libfirm_params,
2022 ia32_get_allowed_execution_units,
2027 void ia32_init_emitter(void);
2028 void ia32_init_finish(void);
2029 void ia32_init_optimize(void);
2030 void ia32_init_transform(void);
2031 void ia32_init_x87(void);
2033 void be_init_arch_ia32(void)
2035 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2036 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2038 lc_opt_add_table(ia32_grp, ia32_options);
2039 be_register_isa_if("ia32", &ia32_isa_if);
2041 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2043 ia32_init_emitter();
2045 ia32_init_optimize();
2046 ia32_init_transform();
2050 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);