11 #include "pseudo_irg.h"
15 #include "iredges_t.h"
22 #include "../beabi.h" /* the general register allocator interface */
23 #include "../benode_t.h"
24 #include "../belower.h"
25 #include "../besched_t.h"
26 #include "bearch_ia32_t.h"
28 #include "ia32_new_nodes.h" /* ia32 nodes interface */
29 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
30 #include "ia32_gen_decls.h" /* interface declaration emitter */
31 #include "ia32_transform.h"
32 #include "ia32_emitter.h"
33 #include "ia32_map_regs.h"
34 #include "ia32_optimize.h"
36 #define DEBUG_MODULE "firm.be.ia32.isa"
39 static set *cur_reg_set = NULL;
42 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
44 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
46 cg->noreg_gp = be_new_NoReg(&ia32_gp_regs[REG_XXX], cg->irg, get_irg_start_block(cg->irg));
52 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
54 cg->noreg_fp = be_new_NoReg(&ia32_fp_regs[REG_XXXX], cg->irg, get_irg_start_block(cg->irg));
60 /**************************************************
63 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
64 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
65 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
66 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
69 **************************************************/
71 static ir_node *my_skip_proj(const ir_node *n) {
77 static int is_Call_Proj(const ir_node *n) {
79 is_Proj(get_Proj_pred(n)) &&
80 get_irn_mode(get_Proj_pred(n)) == mode_T &&
81 is_ia32_Call(get_Proj_pred(get_Proj_pred(n))))
89 static int is_Start_Proj(const ir_node *n) {
91 is_Proj(get_Proj_pred(n)) &&
92 get_irn_mode(get_Proj_pred(n)) == mode_T &&
93 is_Start(get_Proj_pred(get_Proj_pred(n))))
101 static int is_P_frame_base_Proj(const ir_node *n) {
103 is_Start(get_Proj_pred(n)) &&
104 get_Proj_proj(n) == pn_Start_P_frame_base)
112 static int is_used_by_Keep(const ir_node *n) {
113 return be_is_Keep(get_edge_src_irn(get_irn_out_edge_first(n)));
117 * Return register requirements for an ia32 node.
118 * If the node returns a tuple (mode_T) then the proj's
119 * will be asked for this information.
121 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
122 const ia32_register_req_t *irn_req;
123 long node_pos = pos == -1 ? 0 : pos;
124 ir_mode *mode = get_irn_mode(irn);
125 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
126 const ia32_irn_ops_t *ops = self;
128 if (mode == mode_T || mode == mode_M) {
129 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
133 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
136 if (is_Call_Proj(irn) && is_used_by_Keep(irn)) {
141 irn_req = ia32_projnum_reg_req_map[get_Proj_proj(irn)];
142 memcpy(req, &(irn_req->req), sizeof(*req));
147 else if (is_Start_Proj(irn)) {
148 /* irn_req = ops->cg->reg_param_req[get_Proj_proj(irn)];
149 assert(irn_req && "missing requirement for regparam");
150 memcpy(req, &(irn_req->req), sizeof(*req)); */
151 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
155 else if (is_Proj(irn)) {
157 node_pos = ia32_translate_proj_pos(irn);
163 irn = my_skip_proj(irn);
165 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
168 if (is_ia32_irn(irn)) {
170 irn_req = get_ia32_in_req(irn, pos);
173 irn_req = get_ia32_out_req(irn, node_pos);
176 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
178 memcpy(req, &(irn_req->req), sizeof(*req));
180 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
181 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
182 req->other_same = get_irn_n(irn, irn_req->same_pos);
185 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
186 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
187 req->other_different = get_irn_n(irn, irn_req->different_pos);
191 /* treat Phi like Const with default requirements */
193 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
194 if (mode_is_float(mode))
195 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
196 else if (mode_is_int(mode) || mode_is_reference(mode))
197 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
198 else if (mode == mode_T || mode == mode_M) {
199 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
203 assert(0 && "unsupported Phi-Mode");
205 else if (is_Start(irn)) {
206 DB((mod, LEVEL_1, "returning reqs none for ProjX -> Start (%+F )\n", irn));
208 case pn_Start_X_initial_exec:
209 case pn_Start_P_value_arg_base:
210 case pn_Start_P_globals:
211 case pn_Start_P_frame_base:
212 memcpy(req, &(ia32_default_req_none.req), sizeof(*req));
214 case pn_Start_T_args:
215 assert(0 && "ProjT(pn_Start_T_args) should not be asked");
218 else if (get_irn_op(irn) == op_Return && pos > 0) {
219 DB((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
220 memcpy(req, &(ia32_default_req_ia32_gp_eax.req), sizeof(*req));
223 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
231 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
235 pos = ia32_translate_proj_pos(irn);
236 irn = my_skip_proj(irn);
239 if (is_ia32_irn(irn)) {
240 const arch_register_t **slots;
242 slots = get_ia32_slots(irn);
246 ia32_set_firm_reg(irn, reg, cur_reg_set);
250 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
252 const arch_register_t *reg = NULL;
255 pos = ia32_translate_proj_pos(irn);
256 irn = my_skip_proj(irn);
259 if (is_ia32_irn(irn)) {
260 const arch_register_t **slots;
261 slots = get_ia32_slots(irn);
265 reg = ia32_get_firm_reg(irn, cur_reg_set);
271 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
272 irn = my_skip_proj(irn);
274 return arch_irn_class_branch;
275 else if (is_ia32_Call(irn))
276 return arch_irn_class_call;
277 else if (is_ia32_irn(irn))
278 return arch_irn_class_normal;
283 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
284 irn = my_skip_proj(irn);
285 if (is_ia32_irn(irn))
286 return get_ia32_flags(irn);
292 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
293 if (get_ia32_use_frame(irn)) {
294 /* TODO: correct offset */
298 /* fill register allocator interface */
300 static const arch_irn_ops_if_t ia32_irn_ops_if = {
301 ia32_get_irn_reg_req,
309 ia32_irn_ops_t ia32_irn_ops = {
316 /**************************************************
319 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
320 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
321 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
322 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
325 **************************************************/
328 * Transforms the standard firm graph into
331 static void ia32_prepare_graph(void *self) {
332 ia32_code_gen_t *cg = self;
334 irg_walk_blkwise_graph(cg->irg, ia32_place_consts, ia32_transform_node, cg);
335 dump_ir_block_graph_sched(cg->irg, "-transformed");
336 edges_deactivate(cg->irg);
337 edges_activate(cg->irg);
338 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
339 dump_ir_block_graph_sched(cg->irg, "-am");
345 * Stack reservation and StackParam lowering.
347 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
349 firm_dbg_module_t *mod = cg->mod;
350 ir_node *frame = get_irg_frame(irg);
351 ir_node *end_block = get_irg_end_block(irg);
352 ir_node **returns, **in, **new_in;
353 ir_node *stack_reserve, *sched_point;
354 ir_node *stack_free, *new_ret, *return_block;
355 int stack_size = 0, i, n_arg;
356 arch_register_t *stack_reg;
357 tarval *stack_size_tv;
360 /* Determine stack register */
361 if (cg->has_alloca) {
362 stack_reg = &ia32_gp_regs[REG_EBP];
365 stack_reg = &ia32_gp_regs[REG_ESP];
368 /* If frame is used, then we need to reserve some stackspace. */
369 if (get_irn_n_edges(frame) > 0) {
370 /* The initial stack reservation. */
371 stack_size = get_type_size_bytes(get_irg_frame_type(irg));
372 frame_dbg = get_irn_dbg_info(frame);
373 stack_reserve = new_rd_ia32_Sub_i(frame_dbg, irg, get_nodes_block(frame), new_NoMem(), mode_Is);
374 stack_size_tv = new_tarval_from_long(stack_size, mode_Is);
375 set_ia32_Immop_tarval(stack_reserve, stack_size_tv);
377 assert(stack_size && "bOrken stack layout");
379 /* reroute all edges from frame pointer to corrected frame pointer */
380 edges_reroute(frame, stack_reserve, irg);
381 set_irn_n(stack_reserve, 0, frame);
383 /* schedule frame pointer */
384 if (! sched_is_scheduled(frame)) {
385 sched_add_after(get_irg_start(irg), frame);
389 arch_set_irn_register(cg->arch_env, frame, stack_reg);
390 arch_set_irn_register(cg->arch_env, stack_reserve, stack_reg);
392 /* insert into schedule */
393 sched_add_after(frame, stack_reserve);
395 /* Free stack for each Return node */
396 returns = get_Block_cfgpred_arr(end_block);
397 for (i = 0; i < get_Block_n_cfgpreds(end_block); i++) {
398 assert(get_irn_opcode(returns[i]) == iro_Return && "cfgpred of endblock is not a return");
400 return_block = get_nodes_block(returns[i]);
403 stack_free = new_rd_ia32_Add_i(frame_dbg, irg, return_block, stack_reserve, mode_Is);
404 set_ia32_Immop_tarval(stack_free, stack_size_tv);
405 arch_set_irn_register(cg->arch_env, stack_free, stack_reg);
407 DBG((mod, LEVEL_1, "examining %+F, %+F created, block %+F", returns[i], stack_free, return_block));
409 /* get the old Return arguments */
410 n_arg = get_Return_n_ress(returns[i]);
411 in = get_Return_res_arr(returns[i]);
412 new_in = alloca((n_arg + 2) * sizeof(new_in[0]));
414 /* copy the old to the new in's */
415 memcpy(new_in, in, n_arg * sizeof(in[0]));
416 new_in[n_arg++] = stack_free;
417 new_in[n_arg++] = get_Return_mem(returns[i]);
419 /* create the new return node */
420 new_ret = new_rd_ia32_Return(get_irn_dbg_info(returns[i]), irg, return_block, n_arg, new_in);
422 /* In case the return node is the only node in the block, */
423 /* it is not scheduled, so we need this work-around. */
424 if (! sched_is_scheduled(returns[i])) {
425 sched_point = return_block;
428 sched_point = sched_prev(returns[i]);
429 sched_remove(returns[i]);
432 /* exchange the old return with the new one */
433 exchange(returns[i], new_ret);
435 DB((mod, LEVEL_1, " ... replaced with %+F\n", new_ret));
437 /* remove the old one from schedule and add the new nodes properly */
438 sched_add_after(sched_point, new_ret);
439 sched_add_after(sched_point, stack_free);
448 * Dummy functions for hooks we don't need but which must be filled.
450 static void ia32_before_sched(void *self) {
451 ia32_code_gen_t *cg = self;
453 lower_nodes_before_sched(cg->irg, cg->arch_env);
456 static void ia32_before_ra(void *self) {
461 * Creates a Store for a Spill
463 static ir_node *ia32_lower_spill(void *self, ir_node *spill) {
464 ia32_code_gen_t *cg = self;
465 ir_graph *irg = cg->irg;
466 dbg_info *dbg = get_irn_dbg_info(spill);
467 ir_node *block = get_nodes_block(spill);
468 ir_node *ptr = get_irg_frame(irg);
469 ir_node *val = be_get_Spill_context(spill);
470 ir_node *mem = new_rd_NoMem(irg);
471 ir_mode *mode = get_irn_mode(spill);
472 entity *ent = be_get_spill_entity(spill);
473 unsigned offs = get_entity_offset_bytes(ent);
474 ir_node *noreg, *res;
477 DB((cg->mod, LEVEL_1, "lower_spill: got offset %d for %+F\n", offs, ent));
479 if (mode_is_float(mode)) {
480 noreg = ia32_new_NoReg_fp(cg);
481 res = new_rd_ia32_fStore(dbg, irg, block, ptr, noreg, val, mem, mode);
484 noreg = ia32_new_NoReg_gp(cg);
485 res = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, mem, mode);
488 snprintf(buf, sizeof(buf), "%d", offs);
489 add_ia32_am_offs(res, buf);
495 * Create a Load for a Spill
497 static ir_node *ia32_lower_reload(void *self, ir_node *reload) {
498 ia32_code_gen_t *cg = self;
499 ir_graph *irg = cg->irg;
500 dbg_info *dbg = get_irn_dbg_info(reload);
501 ir_node *block = get_nodes_block(reload);
502 ir_node *ptr = get_irg_frame(irg);
503 ir_mode *mode = get_irn_mode(reload);
504 ir_node *pred = get_irn_n(reload, 0);
507 ir_node *noreg, *res;
509 /* Get the offset to Load from. It can either be a Spill or a Store. */
510 if (be_is_Spill(pred)) {
511 entity *ent = be_get_spill_entity(pred);
512 unsigned offs = get_entity_offset_bytes(ent);
513 DB((cg->mod, LEVEL_1, "lower_reload: got offset %d for %+F\n", offs, ent));
515 snprintf(buf, sizeof(buf), "%d", offs);
517 else if (is_ia32_Store(pred) || is_ia32_fStore(pred)) {
518 ofs = get_ia32_am_offs(pred);
519 strncpy(buf, ofs, sizeof(buf));
523 assert(0 && "unsupported Reload predecessor");
526 /* Create the Load */
527 if (mode_is_float(mode)) {
528 noreg = ia32_new_NoReg_fp(cg);
529 res = new_rd_ia32_fLoad(dbg, irg, block, ptr, noreg, pred, mode_T);
532 noreg = ia32_new_NoReg_gp(cg);
533 res = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, pred, mode_T);
537 add_ia32_am_offs(res, buf);
539 /* Return the result Proj */
540 return new_rd_Proj(dbg, irg, block, res, mode, 0);
544 * Emits the code, closes the output file and frees
545 * the code generator interface.
547 static void ia32_codegen(void *self) {
548 ia32_code_gen_t *cg = self;
549 ir_graph *irg = cg->irg;
552 if (cg->emit_decls) {
553 ia32_gen_decls(cg->out);
557 ia32_finish_irg(irg, cg);
558 //dump_ir_block_graph_sched(irg, "-finished");
559 ia32_gen_routine(out, irg, cg);
563 pmap_destroy(cg->tv_ent);
564 pmap_destroy(cg->types);
566 /* de-allocate code generator */
567 del_set(cg->reg_set);
571 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env);
573 static const arch_code_generator_if_t ia32_code_gen_if = {
576 ia32_before_sched, /* before scheduling hook */
577 ia32_before_ra, /* before register allocation hook */
580 ia32_codegen /* emit && done */
584 * Initializes the code generator.
586 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env) {
587 ia32_isa_t *isa = (ia32_isa_t *)arch_env->isa;
588 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
590 cg->impl = &ia32_code_gen_if;
592 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
593 cg->mod = firm_dbg_register("firm.be.ia32.cg");
595 cg->arch_env = arch_env;
596 cg->types = pmap_create();
597 cg->tv_ent = pmap_create();
603 if (isa->num_codegens > 1)
608 cur_reg_set = cg->reg_set;
610 ia32_irn_ops.cg = cg;
612 return (arch_code_generator_t *)cg;
617 /*****************************************************************
618 * ____ _ _ _____ _____
619 * | _ \ | | | | |_ _|/ ____| /\
620 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
621 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
622 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
623 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
625 *****************************************************************/
627 static ia32_isa_t ia32_isa_template = {
629 &ia32_gp_regs[REG_ESP],
630 &ia32_gp_regs[REG_EBP],
637 * Initializes the backend ISA.
639 static void *ia32_init(void) {
640 static int inited = 0;
646 isa = xcalloc(1, sizeof(*isa));
647 memcpy(isa, &ia32_isa_template, sizeof(*isa));
649 isa->reg_projnum_map = new_set(ia32_cmp_reg_projnum_assoc, 1024);
651 ia32_register_init(isa);
652 ia32_create_opcodes();
662 * Closes the output file and frees the ISA structure.
664 static void ia32_done(void *self) {
670 static int ia32_get_n_reg_class(const void *self) {
674 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
675 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
676 return &ia32_reg_classes[i];
680 * Get the register class which shall be used to store a value of a given mode.
681 * @param self The this pointer.
682 * @param mode The mode in question.
683 * @return A register class which can hold values of the given mode.
685 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
686 if (mode_is_float(mode))
687 return &ia32_reg_classes[CLASS_ia32_fp];
689 return &ia32_reg_classes[CLASS_ia32_gp];
693 * Get the ABI restrictions for procedure calls.
694 * @param self The this pointer.
695 * @param method_type The type of the method (procedure) in question.
696 * @param abi The abi object to be modified
698 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
701 unsigned cc = get_method_calling_convention(method_type);
702 int n = get_method_n_params(method_type);
707 const arch_register_t *reg;
709 /* set stack parameter passing style */
710 be_abi_call_set_flags(abi, BE_ABI_FRAME_POINTER_DEDICATED, 4);
712 /* collect the mode for each type */
713 modes = alloca(n * sizeof(modes[0]));
715 for (i = 0; i < n; i++) {
716 tp = get_method_param_type(method_type, i);
717 modes[i] = get_type_mode(tp);
720 /* set register parameters */
721 if (cc & cc_reg_param) {
722 /* determine the number of parameters passed via registers */
723 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore, &ignore);
725 /* loop over all parameters and set the register requirements */
726 for (i = 0; i <= biggest_n; i++) {
727 reg = ia32_get_RegParam_reg(n, modes, i, cc);
728 assert(reg && "kaputt");
729 be_abi_call_param_reg(abi, i, reg);
736 /* set stack parameters */
737 for (i = stack_idx; i < n; i++) {
738 be_abi_call_param_stack(abi, i);
742 /* set return registers */
743 n = get_method_n_ress(method_type);
745 assert(n <= 2 && "more than two results not supported");
747 /* In case of 64bit returns, we will have two 32bit values */
749 tp = get_method_res_type(method_type, 0);
750 mode = get_type_mode(tp);
752 assert(!mode_is_float(mode) && "two FP results not supported");
754 tp = get_method_res_type(method_type, 1);
755 mode = get_type_mode(tp);
757 assert(!mode_is_float(mode) && "two FP results not supported");
759 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
760 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
763 tp = get_method_res_type(method_type, 0);
764 mode = get_type_mode(tp);
766 if (mode_is_float(mode)) {
767 be_abi_call_res_reg(abi, 1, &ia32_fp_regs[REG_XMM0]);
770 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EAX]);
776 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
777 return &ia32_irn_ops;
780 const arch_irn_handler_t ia32_irn_handler = {
784 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
785 return &ia32_irn_handler;
788 long ia32_handle_call_proj(const void *self, ir_node *proj, int is_keep) {
789 ia32_isa_t *isa = (ia32_isa_t *)self;
790 long pn = get_Proj_proj(proj);
793 /* It's not a Keep proj, which means, that it is a result proj. */
794 /* Possible result proj numbers are 0 and 1 */
795 /* Set the correct register (depends on the mode) and the */
796 /* corresponding proj number */
797 if (mode_is_float(get_irn_mode(proj))) {
798 assert(pn == 0 && "only one floating point result supported");
800 /* Get the proj number for the floating point result */
801 pn = ia32_get_reg_projnum(&ia32_fp_regs[REG_XMM0], isa->reg_projnum_map);
804 /* In case of 64bit return value, the result is */
805 /* in EDX:EAX and we have two result projs. */
808 pn = ia32_get_reg_projnum(&ia32_gp_regs[REG_EAX], isa->reg_projnum_map);
811 pn = ia32_get_reg_projnum(&ia32_gp_regs[REG_EDX], isa->reg_projnum_map);
814 assert(0 && "only two int results supported");
818 /* Set the correct proj number */
819 set_Proj_proj(proj, pn);
822 /* Set mode to floating point if required */
823 if (!strcmp(ia32_reg_classes[CLASS_ia32_fp].name,
824 ia32_projnum_reg_req_map[pn]->req.cls->name)) {
825 set_irn_mode(proj, mode_F);
832 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
833 return is_ia32_irn(irn);
837 * Initializes the code generator interface.
839 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
840 return &ia32_code_gen_if;
843 list_sched_selector_t ia32_sched_selector;
846 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
848 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
849 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
850 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
851 return &ia32_sched_selector;
855 static void ia32_register_options(lc_opt_entry_t *ent)
858 #endif /* WITH_LIBCORE */
860 const arch_isa_if_t ia32_isa_if = {
862 ia32_register_options,
866 ia32_get_n_reg_class,
868 ia32_get_reg_class_for_mode,
870 ia32_get_irn_handler,
871 ia32_get_code_generator_if,
872 ia32_get_list_sched_selector,
873 ia32_handle_call_proj