2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
26 #include "pseudo_irg.h"
30 #include "iredges_t.h"
39 #include "../beabi.h" /* the general register allocator interface */
40 #include "../benode_t.h"
41 #include "../belower.h"
42 #include "../besched_t.h"
45 #include "../beirgmod.h"
46 #include "../be_dbgout.h"
47 #include "../beblocksched.h"
48 #include "../bemachine.h"
49 #include "../beilpsched.h"
50 #include "../bespillslots.h"
51 #include "../bemodule.h"
53 #include "bearch_ia32_t.h"
55 #include "ia32_new_nodes.h" /* ia32 nodes interface */
56 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
57 #include "gen_ia32_machine.h"
58 #include "ia32_gen_decls.h" /* interface declaration emitter */
59 #include "ia32_transform.h"
60 #include "ia32_emitter.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_optimize.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_finish.h"
66 #include "ia32_util.h"
68 #define DEBUG_MODULE "firm.be.ia32.isa"
71 static set *cur_reg_set = NULL;
73 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
75 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
76 create_const_node_func func, arch_register_t* reg)
84 block = get_irg_start_block(cg->irg);
85 res = func(NULL, cg->irg, block);
86 arch_set_irn_register(cg->arch_env, res, reg);
89 startnode = get_irg_start(cg->irg);
90 if(sched_is_scheduled(startnode)) {
91 sched_add_before(startnode, res);
97 /* Creates the unique per irg GP NoReg node. */
98 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
99 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
100 &ia32_gp_regs[REG_GP_NOREG]);
103 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
104 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
105 &ia32_vfp_regs[REG_VFP_NOREG]);
108 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
109 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
110 &ia32_xmm_regs[REG_XMM_NOREG]);
113 /* Creates the unique per irg FP NoReg node. */
114 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
115 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
118 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
119 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
120 &ia32_gp_regs[REG_GP_UKNWN]);
123 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
124 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
125 &ia32_vfp_regs[REG_VFP_UKNWN]);
128 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
129 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
130 &ia32_xmm_regs[REG_XMM_UKNWN]);
135 * Returns gp_noreg or fp_noreg, depending in input requirements.
137 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
138 arch_register_req_t req;
139 const arch_register_req_t *p_req;
141 p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
142 assert(p_req && "Missing register requirements");
143 if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
144 return ia32_new_NoReg_gp(cg);
146 return ia32_new_NoReg_fp(cg);
149 /**************************************************
152 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
153 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
154 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
155 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
158 **************************************************/
161 * Return register requirements for an ia32 node.
162 * If the node returns a tuple (mode_T) then the proj's
163 * will be asked for this information.
165 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
166 const ia32_irn_ops_t *ops = self;
167 const ia32_register_req_t *irn_req;
168 long node_pos = pos == -1 ? 0 : pos;
169 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
170 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
172 if (is_Block(irn) || mode == mode_X) {
173 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
177 if (mode == mode_T && pos < 0) {
178 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
182 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
189 DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
193 node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
194 irn = skip_Proj_const(irn);
196 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
199 if (is_ia32_irn(irn)) {
200 irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
201 if (irn_req == NULL) {
202 /* no requirements */
206 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
208 memcpy(req, &(irn_req->req), sizeof(*req));
210 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
211 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
212 req->other_same = get_irn_n(irn, irn_req->same_pos);
215 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
216 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
217 req->other_different = get_irn_n(irn, irn_req->different_pos);
221 /* treat Unknowns like Const with default requirements */
222 if (is_Unknown(irn)) {
223 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
224 if (mode_is_float(mode)) {
225 if (USE_SSE2(ops->cg))
226 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
228 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
230 else if (mode_is_int(mode) || mode_is_reference(mode))
231 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
232 else if (mode == mode_T || mode == mode_M) {
233 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
237 assert(0 && "unsupported Unknown-Mode");
240 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
248 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
250 const ia32_irn_ops_t *ops = self;
252 if (get_irn_mode(irn) == mode_X) {
256 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
259 pos = get_Proj_proj(irn);
260 irn = skip_Proj(irn);
263 if (is_ia32_irn(irn)) {
264 const arch_register_t **slots;
266 slots = get_ia32_slots(irn);
270 ia32_set_firm_reg(irn, reg, cur_reg_set);
274 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
276 const arch_register_t *reg = NULL;
280 if (get_irn_mode(irn) == mode_X) {
284 pos = get_Proj_proj(irn);
285 irn = skip_Proj_const(irn);
288 if (is_ia32_irn(irn)) {
289 const arch_register_t **slots;
290 slots = get_ia32_slots(irn);
294 reg = ia32_get_firm_reg(irn, cur_reg_set);
300 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
301 arch_irn_class_t classification = arch_irn_class_normal;
303 irn = skip_Proj_const(irn);
306 classification |= arch_irn_class_branch;
308 if (! is_ia32_irn(irn))
309 return classification & ~arch_irn_class_normal;
311 if (is_ia32_Cnst(irn))
312 classification |= arch_irn_class_const;
315 classification |= arch_irn_class_load;
317 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
318 classification |= arch_irn_class_store;
320 if (is_ia32_got_reload(irn))
321 classification |= arch_irn_class_reload;
323 return classification;
326 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
327 arch_irn_flags_t flags = arch_irn_flags_none;
330 return arch_irn_flags_ignore;
332 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
333 ir_node *pred = get_Proj_pred(irn);
335 if(is_ia32_irn(pred)) {
336 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
342 if (is_ia32_irn(irn)) {
343 flags |= get_ia32_flags(irn);
350 * The IA32 ABI callback object.
353 be_abi_call_flags_bits_t flags; /**< The call flags. */
354 const arch_isa_t *isa; /**< The ISA handle. */
355 const arch_env_t *aenv; /**< The architecture environment. */
356 ir_graph *irg; /**< The associated graph. */
359 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
360 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
363 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
364 set_ia32_frame_ent(irn, ent);
367 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
368 const ia32_irn_ops_t *ops = self;
370 if (get_ia32_frame_ent(irn)) {
371 ia32_am_flavour_t am_flav;
373 if (is_ia32_Pop(irn)) {
374 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
376 /* Pop nodes modify the stack pointer before calculating the destination
377 * address, so fix this here
383 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
385 am_flav = get_ia32_am_flavour(irn);
387 set_ia32_am_flavour(irn, am_flav);
389 add_ia32_am_offs_int(irn, bias);
393 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
395 long proj = get_Proj_proj(irn);
396 ir_node *pred = get_Proj_pred(irn);
398 if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack)
400 if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack)
408 * Put all registers which are saved by the prologue/epilogue in a set.
410 * @param self The callback object.
411 * @param s The result set.
413 static void ia32_abi_dont_save_regs(void *self, pset *s)
415 ia32_abi_env_t *env = self;
416 if(env->flags.try_omit_fp)
417 pset_insert_ptr(s, env->isa->bp);
421 * Generate the routine prologue.
423 * @param self The callback object.
424 * @param mem A pointer to the mem node. Update this if you define new memory.
425 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
427 * @return The register which shall be used as a stack frame base.
429 * All nodes which define registers in @p reg_map must keep @p reg_map current.
431 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
433 ia32_abi_env_t *env = self;
434 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
435 ia32_code_gen_t *cg = isa->cg;
437 if (! env->flags.try_omit_fp) {
438 ir_node *bl = get_irg_start_block(env->irg);
439 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
440 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
441 ir_node *noreg = ia32_new_NoReg_gp(cg);
445 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
446 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
447 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
449 /* the push must have SP out register */
450 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
451 set_ia32_flags(push, arch_irn_flags_ignore);
453 /* move esp to ebp */
454 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
455 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
456 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
457 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
459 /* beware: the copy must be done before any other sp use */
460 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
461 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
462 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
463 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
465 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
466 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
475 * Generate the routine epilogue.
476 * @param self The callback object.
477 * @param bl The block for the epilog
478 * @param mem A pointer to the mem node. Update this if you define new memory.
479 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
480 * @return The register which shall be used as a stack frame base.
482 * All nodes which define registers in @p reg_map must keep @p reg_map current.
484 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
486 ia32_abi_env_t *env = self;
487 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
488 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
490 if (env->flags.try_omit_fp) {
491 /* simply remove the stack frame here */
492 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
493 add_irn_dep(curr_sp, *mem);
495 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
496 ia32_code_gen_t *cg = isa->cg;
497 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
499 /* gcc always emits a leave at the end of a routine */
500 if (1 || ARCH_AMD(isa->opt_arch)) {
504 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
505 set_ia32_flags(leave, arch_irn_flags_ignore);
506 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
507 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
509 ir_node *noreg = ia32_new_NoReg_gp(cg);
512 /* copy ebp to esp */
513 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
516 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
517 set_ia32_flags(pop, arch_irn_flags_ignore);
518 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
519 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
521 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
523 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
524 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
527 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
528 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
532 * Initialize the callback object.
533 * @param call The call object.
534 * @param aenv The architecture environment.
535 * @param irg The graph with the method.
536 * @return Some pointer. This pointer is passed to all other callback functions as self object.
538 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
540 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
541 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
542 env->flags = fl.bits;
545 env->isa = aenv->isa;
550 * Destroy the callback object.
551 * @param self The callback object.
553 static void ia32_abi_done(void *self) {
558 * Produces the type which sits between the stack args and the locals on the stack.
559 * it will contain the return address and space to store the old base pointer.
560 * @return The Firm type modeling the ABI between type.
562 static ir_type *ia32_abi_get_between_type(void *self)
564 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
565 static ir_type *omit_fp_between_type = NULL;
566 static ir_type *between_type = NULL;
568 ia32_abi_env_t *env = self;
570 if (! between_type) {
571 ir_entity *old_bp_ent;
572 ir_entity *ret_addr_ent;
573 ir_entity *omit_fp_ret_addr_ent;
575 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
576 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
578 between_type = new_type_struct(IDENT("ia32_between_type"));
579 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
580 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
582 set_entity_offset(old_bp_ent, 0);
583 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
584 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
585 set_type_state(between_type, layout_fixed);
587 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
588 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
590 set_entity_offset(omit_fp_ret_addr_ent, 0);
591 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
592 set_type_state(omit_fp_between_type, layout_fixed);
595 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
600 * Get the estimated cycle count for @p irn.
602 * @param self The this pointer.
603 * @param irn The node.
605 * @return The estimated cycle count for this operation
607 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
610 ia32_op_type_t op_tp;
611 const ia32_irn_ops_t *ops = self;
615 if (!is_ia32_irn(irn))
618 assert(is_ia32_irn(irn));
620 cost = get_ia32_latency(irn);
621 op_tp = get_ia32_op_type(irn);
623 if (is_ia32_CopyB(irn)) {
625 if (ARCH_INTEL(ops->cg->arch))
628 else if (is_ia32_CopyB_i(irn)) {
629 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
630 cost = 20 + (int)ceil((4/3) * size);
631 if (ARCH_INTEL(ops->cg->arch))
634 /* in case of address mode operations add additional cycles */
635 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
637 In case of stack access add 5 cycles (we assume stack is in cache),
638 other memory operations cost 20 cycles.
640 cost += is_ia32_use_frame(irn) ? 5 : 20;
647 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
649 * @param irn The original operation
650 * @param i Index of the argument we want the inverse operation to yield
651 * @param inverse struct to be filled with the resulting inverse op
652 * @param obstack The obstack to use for allocation of the returned nodes array
653 * @return The inverse operation or NULL if operation invertible
655 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
659 ir_node *block, *noreg, *nomem;
662 /* we cannot invert non-ia32 irns */
663 if (! is_ia32_irn(irn))
666 /* operand must always be a real operand (not base, index or mem) */
667 if (i != 2 && i != 3)
670 /* we don't invert address mode operations */
671 if (get_ia32_op_type(irn) != ia32_Normal)
674 irg = get_irn_irg(irn);
675 block = get_nodes_block(irn);
676 mode = get_irn_mode(irn);
677 irn_mode = get_irn_mode(irn);
678 noreg = get_irn_n(irn, 0);
679 nomem = new_r_NoMem(irg);
680 dbg = get_irn_dbg_info(irn);
682 /* initialize structure */
683 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
687 switch (get_ia32_irn_opcode(irn)) {
689 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
690 /* we have an add with a const here */
691 /* invers == add with negated const */
692 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
694 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
695 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
696 set_ia32_commutative(inverse->nodes[0]);
698 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
699 /* we have an add with a symconst here */
700 /* invers == sub with const */
701 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
703 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
706 /* normal add: inverse == sub */
707 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
712 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
713 /* we have a sub with a const/symconst here */
714 /* invers == add with this const */
715 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
716 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
717 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
722 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
725 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
731 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
732 /* xor with const: inverse = xor */
733 inverse->nodes[0] = new_rd_ia32_Eor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
734 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
735 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
739 inverse->nodes[0] = new_rd_ia32_Eor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
744 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
748 case iro_ia32_Minus: {
749 inverse->nodes[0] = new_rd_ia32_Minus(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
754 /* inverse operation not supported */
762 * Get the mode that should be used for spilling value node
764 static ir_mode *get_spill_mode(ia32_code_gen_t *cg, const ir_node *node)
766 ir_mode *mode = get_irn_mode(node);
767 if (mode_is_float(mode)) {
769 // super exact spilling...
786 * Checks wether an addressmode reload for a node with mode mode is compatible
787 * with a spillslot of mode spill_mode
789 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
791 if(mode_is_float(mode)) {
792 return mode == spillmode;
799 * Check if irn can load it's operand at position i from memory (source addressmode).
800 * @param self Pointer to irn ops itself
801 * @param irn The irn to be checked
802 * @param i The operands position
803 * @return Non-Zero if operand can be loaded
805 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
806 const ia32_irn_ops_t *ops = self;
807 ia32_code_gen_t *cg = ops->cg;
808 ir_node *op = get_irn_n(irn, i);
809 const ir_mode *mode = get_irn_mode(op);
810 const ir_mode *spillmode = get_spill_mode(cg, op);
812 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
813 get_irn_arity(irn) != 5 || /* must be a binary operation */
814 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
815 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
816 ! ia32_is_spillmode_compatible(mode, spillmode) ||
817 (i != 2 && i != 3) || /* a "real" operand position must be requested */
818 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
819 is_ia32_use_frame(irn)) /* must not already use frame */
825 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
826 const ia32_irn_ops_t *ops = self;
827 ia32_code_gen_t *cg = ops->cg;
829 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
832 ir_node *tmp = get_irn_n(irn, 3);
833 set_irn_n(irn, 3, get_irn_n(irn, 2));
834 set_irn_n(irn, 2, tmp);
837 set_ia32_am_support(irn, ia32_am_Source);
838 set_ia32_op_type(irn, ia32_AddrModeS);
839 set_ia32_am_flavour(irn, ia32_B);
840 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
841 set_ia32_use_frame(irn);
842 set_ia32_got_reload(irn);
844 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
845 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
846 set_irn_n(irn, 4, spill);
848 //FIXME DBG_OPT_AM_S(reload, irn);
851 static const be_abi_callbacks_t ia32_abi_callbacks = {
854 ia32_abi_get_between_type,
855 ia32_abi_dont_save_regs,
860 /* fill register allocator interface */
862 static const arch_irn_ops_if_t ia32_irn_ops_if = {
863 ia32_get_irn_reg_req,
868 ia32_get_frame_entity,
869 ia32_set_frame_entity,
870 ia32_set_frame_offset,
873 ia32_get_op_estimated_cost,
874 ia32_possible_memory_operand,
875 ia32_perform_memory_operand,
878 ia32_irn_ops_t ia32_irn_ops = {
885 /**************************************************
888 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
889 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
890 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
891 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
894 **************************************************/
897 * Transform the Thread Local Store base.
899 static void transform_tls(ir_graph *irg) {
900 ir_node *irn = get_irg_tls(irg);
903 dbg_info *dbg = get_irn_dbg_info(irn);
904 ir_node *blk = get_nodes_block(irn);
906 newn = new_rd_ia32_LdTls(dbg, irg, blk, get_irn_mode(irn));
909 set_irg_tls(irg, newn);
914 * Transforms the standard firm graph into
917 static void ia32_prepare_graph(void *self) {
918 ia32_code_gen_t *cg = self;
919 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
921 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
923 /* 1st: transform constants and psi condition trees */
924 ia32_pre_transform_phase(cg);
926 /* 2nd: transform all remaining nodes */
927 transform_tls(cg->irg);
928 ia32_transform_graph(cg);
929 // Matze: disabled for now. Because after transformation start block has no
930 // self-loop anymore so it will probably melt with its successor block.
932 // This will bring several nodes to the startblock and we still can't
933 // handle spill before the initial IncSP nicely
934 //local_optimize_graph(cg->irg);
937 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
939 /* 3rd: optimize address mode */
940 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
941 ia32_optimize_addressmode(cg);
944 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
946 DEBUG_ONLY(cg->mod = old_mod;)
950 * Dummy functions for hooks we don't need but which must be filled.
952 static void ia32_before_sched(void *self) {
955 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
958 ir_node *mem_proj = NULL;
963 mode = get_irn_mode(irn);
965 /* check if we already saw this node or the node has more than one user */
966 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
970 /* mark irn visited */
971 bitset_add_irn(already_visited, irn);
973 /* non-Tuple nodes with one user: ok, return */
974 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
978 /* tuple node has one user which is not the mem proj-> ok */
979 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
980 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
981 if (mem_proj == NULL) {
986 arity = get_irn_arity(irn);
987 for (i = 0; i < arity; ++i) {
988 ir_node *pred = get_irn_n(irn, i);
990 /* do not follow memory edges or we will accidentally remove stores */
991 if (get_irn_mode(pred) == mode_M) {
992 if(mem_proj != NULL) {
993 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
999 set_irn_n(irn, i, new_Bad());
1002 The current node is about to be removed: if the predecessor
1003 has only this node as user, it need to be removed as well.
1005 if (get_irn_n_edges(pred) <= 1)
1006 remove_unused_nodes(pred, already_visited);
1009 // we need to set the presd to Bad again to also get the memory edges
1010 arity = get_irn_arity(irn);
1011 for (i = 0; i < arity; ++i) {
1012 set_irn_n(irn, i, new_Bad());
1015 if (sched_is_scheduled(irn)) {
1020 static void remove_unused_loads_walker(ir_node *irn, void *env) {
1021 bitset_t *already_visited = env;
1022 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
1023 remove_unused_nodes(irn, env);
1027 * Called before the register allocator.
1028 * Calculate a block schedule here. We need it for the x87
1029 * simulator and the emitter.
1031 static void ia32_before_ra(void *self) {
1032 ia32_code_gen_t *cg = self;
1033 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
1036 Handle special case:
1037 There are sometimes unused loads, only pinned by memory.
1038 We need to remove those Loads and all other nodes which won't be used
1039 after removing the Load from schedule.
1041 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
1046 * Transforms a be_Reload into a ia32 Load.
1048 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1049 ir_graph *irg = get_irn_irg(node);
1050 dbg_info *dbg = get_irn_dbg_info(node);
1051 ir_node *block = get_nodes_block(node);
1052 ir_entity *ent = be_get_frame_entity(node);
1053 ir_mode *mode = get_irn_mode(node);
1054 ir_mode *spillmode = get_spill_mode(cg, node);
1055 ir_node *noreg = ia32_new_NoReg_gp(cg);
1056 ir_node *sched_point = NULL;
1057 ir_node *ptr = get_irg_frame(irg);
1058 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1059 ir_node *new_op, *proj;
1060 const arch_register_t *reg;
1062 if (sched_is_scheduled(node)) {
1063 sched_point = sched_prev(node);
1066 if (mode_is_float(spillmode)) {
1068 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
1070 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem);
1073 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1075 set_ia32_am_support(new_op, ia32_am_Source);
1076 set_ia32_op_type(new_op, ia32_AddrModeS);
1077 set_ia32_am_flavour(new_op, ia32_B);
1078 set_ia32_ls_mode(new_op, spillmode);
1079 set_ia32_frame_ent(new_op, ent);
1080 set_ia32_use_frame(new_op);
1082 DBG_OPT_RELOAD2LD(node, new_op);
1084 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1087 sched_add_after(sched_point, new_op);
1088 sched_add_after(new_op, proj);
1093 /* copy the register from the old node to the new Load */
1094 reg = arch_get_irn_register(cg->arch_env, node);
1095 arch_set_irn_register(cg->arch_env, new_op, reg);
1097 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1099 exchange(node, proj);
1103 * Transforms a be_Spill node into a ia32 Store.
1105 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1106 ir_graph *irg = get_irn_irg(node);
1107 dbg_info *dbg = get_irn_dbg_info(node);
1108 ir_node *block = get_nodes_block(node);
1109 ir_entity *ent = be_get_frame_entity(node);
1110 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1111 ir_mode *mode = get_spill_mode(cg, spillval);
1112 ir_node *noreg = ia32_new_NoReg_gp(cg);
1113 ir_node *nomem = new_rd_NoMem(irg);
1114 ir_node *ptr = get_irg_frame(irg);
1115 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1117 ir_node *sched_point = NULL;
1119 if (sched_is_scheduled(node)) {
1120 sched_point = sched_prev(node);
1123 if (mode_is_float(mode)) {
1125 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
1127 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem);
1129 else if (get_mode_size_bits(mode) == 8) {
1130 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
1133 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
1136 set_ia32_am_support(store, ia32_am_Dest);
1137 set_ia32_op_type(store, ia32_AddrModeD);
1138 set_ia32_am_flavour(store, ia32_B);
1139 set_ia32_ls_mode(store, mode);
1140 set_ia32_frame_ent(store, ent);
1141 set_ia32_use_frame(store);
1143 DBG_OPT_SPILL2ST(node, store);
1144 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1147 sched_add_after(sched_point, store);
1151 exchange(node, store);
1154 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1155 ir_graph *irg = get_irn_irg(node);
1156 dbg_info *dbg = get_irn_dbg_info(node);
1157 ir_node *block = get_nodes_block(node);
1158 ir_node *noreg = ia32_new_NoReg_gp(cg);
1159 ir_node *frame = get_irg_frame(irg);
1161 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
1163 set_ia32_frame_ent(push, ent);
1164 set_ia32_use_frame(push);
1165 set_ia32_op_type(push, ia32_AddrModeS);
1166 set_ia32_am_flavour(push, ia32_B);
1167 set_ia32_ls_mode(push, mode_Is);
1169 sched_add_before(schedpoint, push);
1173 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1174 ir_graph *irg = get_irn_irg(node);
1175 dbg_info *dbg = get_irn_dbg_info(node);
1176 ir_node *block = get_nodes_block(node);
1177 ir_node *noreg = ia32_new_NoReg_gp(cg);
1178 ir_node *frame = get_irg_frame(irg);
1180 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
1182 set_ia32_frame_ent(pop, ent);
1183 set_ia32_use_frame(pop);
1184 set_ia32_op_type(pop, ia32_AddrModeD);
1185 set_ia32_am_flavour(pop, ia32_am_OB);
1186 set_ia32_ls_mode(pop, mode_Is);
1188 sched_add_before(schedpoint, pop);
1193 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos, ir_node *schedpoint) {
1194 ir_graph *irg = get_irn_irg(node);
1195 dbg_info *dbg = get_irn_dbg_info(node);
1196 ir_node *block = get_nodes_block(node);
1197 ir_mode *spmode = mode_Iu;
1198 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1201 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1202 arch_set_irn_register(cg->arch_env, sp, spreg);
1203 sched_add_before(schedpoint, sp);
1209 * Transform memperm, currently we do this the ugly way and produce
1210 * push/pop into/from memory cascades. This is possible without using
1213 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1214 ir_graph *irg = get_irn_irg(node);
1215 ir_node *block = get_nodes_block(node);
1219 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1220 const ir_edge_t *edge;
1221 const ir_edge_t *next;
1224 arity = be_get_MemPerm_entity_arity(node);
1225 pops = alloca(arity * sizeof(pops[0]));
1228 for(i = 0; i < arity; ++i) {
1229 ir_entity *ent = be_get_MemPerm_in_entity(node, i);
1230 ir_type *enttype = get_entity_type(ent);
1231 int entbits = get_type_size_bits(enttype);
1232 ir_node *mem = get_irn_n(node, i + 1);
1235 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1237 push = create_push(cg, node, node, sp, mem, ent);
1238 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1240 // add another push after the first one
1241 push = create_push(cg, node, node, sp, mem, ent);
1242 add_ia32_am_offs_int(push, 4);
1243 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1246 set_irn_n(node, i, new_Bad());
1250 for(i = arity - 1; i >= 0; --i) {
1251 ir_entity *ent = be_get_MemPerm_out_entity(node, i);
1252 ir_type *enttype = get_entity_type(ent);
1253 int entbits = get_type_size_bits(enttype);
1257 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1259 pop = create_pop(cg, node, node, sp, ent);
1260 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1262 add_ia32_am_offs_int(pop, 4);
1264 // add another pop after the first one
1265 pop = create_pop(cg, node, node, sp, ent);
1266 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1273 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1274 sched_add_before(node, keep);
1276 // exchange memprojs
1277 foreach_out_edge_safe(node, edge, next) {
1278 ir_node *proj = get_edge_src_irn(edge);
1279 int p = get_Proj_proj(proj);
1283 set_Proj_pred(proj, pops[p]);
1284 set_Proj_proj(proj, 3);
1288 arity = get_irn_arity(node);
1289 for(i = 0; i < arity; ++i) {
1290 set_irn_n(node, i, new_Bad());
1296 * Block-Walker: Calls the transform functions Spill and Reload.
1298 static void ia32_after_ra_walker(ir_node *block, void *env) {
1299 ir_node *node, *prev;
1300 ia32_code_gen_t *cg = env;
1302 /* beware: the schedule is changed here */
1303 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1304 prev = sched_prev(node);
1306 if (be_is_Reload(node)) {
1307 transform_to_Load(cg, node);
1308 } else if (be_is_Spill(node)) {
1309 transform_to_Store(cg, node);
1310 } else if(be_is_MemPerm(node)) {
1311 transform_MemPerm(cg, node);
1317 * Collects nodes that need frame entities assigned.
1319 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1321 be_fec_env_t *env = data;
1323 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1324 const ir_mode *mode = get_irn_mode(node);
1325 int align = get_mode_size_bytes(mode);
1326 be_node_needs_frame_entity(env, node, mode, align);
1327 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1328 && is_ia32_use_frame(node)) {
1329 if (is_ia32_Load(node)) {
1330 const ir_mode *mode = get_ia32_ls_mode(node);
1331 int align = get_mode_size_bytes(mode);
1332 be_node_needs_frame_entity(env, node, mode, align);
1333 } else if (is_ia32_vfild(node)) {
1334 const ir_mode *mode = get_ia32_ls_mode(node);
1336 be_node_needs_frame_entity(env, node, mode, align);
1337 } else if (is_ia32_SetST0(node)) {
1338 const ir_mode *mode = get_ia32_ls_mode(node);
1340 be_node_needs_frame_entity(env, node, mode, align);
1343 if(!is_ia32_Store(node)
1344 && !is_ia32_xStore(node)
1345 && !is_ia32_xStoreSimple(node)
1346 && !is_ia32_vfist(node)) {
1355 * We transform Spill and Reload here. This needs to be done before
1356 * stack biasing otherwise we would miss the corrected offset for these nodes.
1358 static void ia32_after_ra(void *self) {
1359 ia32_code_gen_t *cg = self;
1360 ir_graph *irg = cg->irg;
1361 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1363 /* create and coalesce frame entities */
1364 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1365 be_assign_entities(fec_env);
1366 be_free_frame_entity_coalescer(fec_env);
1368 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1370 ia32_finish_irg(irg, cg);
1374 * Last touchups for the graph before emit: x87 simulation to replace the
1375 * virtual with real x87 instructions, creating a block schedule and peephole
1378 static void ia32_finish(void *self) {
1379 ia32_code_gen_t *cg = self;
1380 ir_graph *irg = cg->irg;
1382 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1383 if (cg->used_fp == fp_x87 || cg->force_sim) {
1384 x87_simulate_graph(cg->arch_env, cg->birg);
1387 /* create block schedule, this also removes empty blocks which might
1388 * produce critical edges */
1389 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1391 /* do peephole optimisations */
1392 ia32_peephole_optimization(irg, cg);
1396 * Emits the code, closes the output file and frees
1397 * the code generator interface.
1399 static void ia32_codegen(void *self) {
1400 ia32_code_gen_t *cg = self;
1401 ir_graph *irg = cg->irg;
1403 ia32_gen_routine(cg->isa->out, irg, cg);
1407 /* remove it from the isa */
1410 /* de-allocate code generator */
1411 del_set(cg->reg_set);
1415 static void *ia32_cg_init(be_irg_t *birg);
1417 static const arch_code_generator_if_t ia32_code_gen_if = {
1419 NULL, /* before abi introduce hook */
1422 ia32_before_sched, /* before scheduling hook */
1423 ia32_before_ra, /* before register allocation hook */
1424 ia32_after_ra, /* after register allocation hook */
1425 ia32_finish, /* called before codegen */
1426 ia32_codegen /* emit && done */
1430 * Initializes a IA32 code generator.
1432 static void *ia32_cg_init(be_irg_t *birg) {
1433 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1434 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1436 cg->impl = &ia32_code_gen_if;
1437 cg->irg = birg->irg;
1438 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1439 cg->arch_env = birg->main_env->arch_env;
1442 cg->blk_sched = NULL;
1443 cg->fp_kind = isa->fp_kind;
1444 cg->used_fp = fp_none;
1445 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1447 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1449 /* copy optimizations from isa for easier access */
1451 cg->arch = isa->arch;
1452 cg->opt_arch = isa->opt_arch;
1458 if (isa->name_obst) {
1459 obstack_free(isa->name_obst, NULL);
1460 obstack_init(isa->name_obst);
1464 cur_reg_set = cg->reg_set;
1466 ia32_irn_ops.cg = cg;
1468 return (arch_code_generator_t *)cg;
1473 /*****************************************************************
1474 * ____ _ _ _____ _____
1475 * | _ \ | | | | |_ _|/ ____| /\
1476 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1477 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1478 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1479 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1481 *****************************************************************/
1484 * Set output modes for GCC
1486 static const tarval_mode_info mo_integer = {
1493 * set the tarval output mode of all integer modes to decimal
1495 static void set_tarval_output_modes(void)
1499 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1500 ir_mode *mode = get_irp_mode(i);
1502 if (mode_is_int(mode))
1503 set_tarval_mode_output_option(mode, &mo_integer);
1507 const arch_isa_if_t ia32_isa_if;
1510 * The template that generates a new ISA object.
1511 * Note that this template can be changed by command line
1514 static ia32_isa_t ia32_isa_template = {
1516 &ia32_isa_if, /* isa interface implementation */
1517 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1518 &ia32_gp_regs[REG_EBP], /* base pointer register */
1519 -1, /* stack direction */
1520 NULL, /* main environment */
1522 NULL, /* 16bit register names */
1523 NULL, /* 8bit register names */
1527 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1528 IA32_OPT_DOAM | /* optimize address mode default: on */
1529 IA32_OPT_LEA | /* optimize for LEAs default: on */
1530 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1531 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1532 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1533 arch_pentium_4, /* instruction architecture */
1534 arch_pentium_4, /* optimize for architecture */
1535 fp_sse2, /* use sse2 unit */
1536 NULL, /* current code generator */
1537 NULL, /* output file */
1539 NULL, /* name obstack */
1540 0 /* name obst size */
1545 * Initializes the backend ISA.
1547 static void *ia32_init(FILE *file_handle) {
1548 static int inited = 0;
1554 set_tarval_output_modes();
1556 isa = xmalloc(sizeof(*isa));
1557 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1559 ia32_register_init(isa);
1560 ia32_create_opcodes();
1561 ia32_register_copy_attr_func();
1563 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1564 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1565 /* no SSE2 for these cpu's */
1566 isa->fp_kind = fp_x87;
1568 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1569 /* Pentium 4 don't like inc and dec instructions */
1570 isa->opt &= ~IA32_OPT_INCDEC;
1573 isa->regs_16bit = pmap_create();
1574 isa->regs_8bit = pmap_create();
1575 isa->types = pmap_create();
1576 isa->tv_ent = pmap_create();
1577 isa->out = file_handle;
1578 isa->cpu = ia32_init_machine_description();
1580 ia32_build_16bit_reg_map(isa->regs_16bit);
1581 ia32_build_8bit_reg_map(isa->regs_8bit);
1583 /* patch register names of x87 registers */
1584 ia32_st_regs[0].name = "st";
1585 ia32_st_regs[1].name = "st(1)";
1586 ia32_st_regs[2].name = "st(2)";
1587 ia32_st_regs[3].name = "st(3)";
1588 ia32_st_regs[4].name = "st(4)";
1589 ia32_st_regs[5].name = "st(5)";
1590 ia32_st_regs[6].name = "st(6)";
1591 ia32_st_regs[7].name = "st(7)";
1594 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1595 obstack_init(isa->name_obst);
1598 ia32_handle_intrinsics();
1599 ia32_switch_section(isa->out, NO_SECTION);
1600 fprintf(isa->out, "\t.intel_syntax\n");
1602 /* needed for the debug support */
1603 ia32_switch_section(isa->out, SECTION_TEXT);
1604 fprintf(isa->out, ".Ltext0:\n");
1614 * Closes the output file and frees the ISA structure.
1616 static void ia32_done(void *self) {
1617 ia32_isa_t *isa = self;
1619 /* emit now all global declarations */
1620 ia32_gen_decls(isa->out, isa->arch_isa.main_env);
1622 pmap_destroy(isa->regs_16bit);
1623 pmap_destroy(isa->regs_8bit);
1624 pmap_destroy(isa->tv_ent);
1625 pmap_destroy(isa->types);
1628 obstack_free(isa->name_obst, NULL);
1636 * Return the number of register classes for this architecture.
1637 * We report always these:
1638 * - the general purpose registers
1639 * - the SSE floating point register set
1640 * - the virtual floating point registers
1642 static int ia32_get_n_reg_class(const void *self) {
1647 * Return the register class for index i.
1649 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1650 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1652 return &ia32_reg_classes[CLASS_ia32_gp];
1654 return &ia32_reg_classes[CLASS_ia32_xmm];
1656 return &ia32_reg_classes[CLASS_ia32_vfp];
1660 * Get the register class which shall be used to store a value of a given mode.
1661 * @param self The this pointer.
1662 * @param mode The mode in question.
1663 * @return A register class which can hold values of the given mode.
1665 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1666 const ia32_isa_t *isa = self;
1667 if (mode_is_float(mode)) {
1668 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1671 return &ia32_reg_classes[CLASS_ia32_gp];
1675 * Get the ABI restrictions for procedure calls.
1676 * @param self The this pointer.
1677 * @param method_type The type of the method (procedure) in question.
1678 * @param abi The abi object to be modified
1680 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1681 const ia32_isa_t *isa = self;
1684 unsigned cc = get_method_calling_convention(method_type);
1685 int n = get_method_n_params(method_type);
1688 int i, ignore_1, ignore_2;
1690 const arch_register_t *reg;
1691 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1693 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1695 /* set abi flags for calls */
1696 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1697 call_flags.bits.store_args_sequential = use_push;
1698 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1699 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1700 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1702 /* set stack parameter passing style */
1703 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1705 /* collect the mode for each type */
1706 modes = alloca(n * sizeof(modes[0]));
1708 for (i = 0; i < n; i++) {
1709 tp = get_method_param_type(method_type, i);
1710 modes[i] = get_type_mode(tp);
1713 /* set register parameters */
1714 if (cc & cc_reg_param) {
1715 /* determine the number of parameters passed via registers */
1716 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1718 /* loop over all parameters and set the register requirements */
1719 for (i = 0; i <= biggest_n; i++) {
1720 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1721 assert(reg && "kaputt");
1722 be_abi_call_param_reg(abi, i, reg);
1729 /* set stack parameters */
1730 for (i = stack_idx; i < n; i++) {
1731 /* parameters on the stack are 32 bit aligned */
1732 be_abi_call_param_stack(abi, i, 4, 0, 0);
1736 /* set return registers */
1737 n = get_method_n_ress(method_type);
1739 assert(n <= 2 && "more than two results not supported");
1741 /* In case of 64bit returns, we will have two 32bit values */
1743 tp = get_method_res_type(method_type, 0);
1744 mode = get_type_mode(tp);
1746 assert(!mode_is_float(mode) && "two FP results not supported");
1748 tp = get_method_res_type(method_type, 1);
1749 mode = get_type_mode(tp);
1751 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1753 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1754 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1757 const arch_register_t *reg;
1759 tp = get_method_res_type(method_type, 0);
1760 assert(is_atomic_type(tp));
1761 mode = get_type_mode(tp);
1763 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1765 be_abi_call_res_reg(abi, 0, reg);
1770 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1771 return &ia32_irn_ops;
1774 const arch_irn_handler_t ia32_irn_handler = {
1778 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1779 return &ia32_irn_handler;
1782 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1783 return is_ia32_irn(irn) ? 1 : -1;
1787 * Initializes the code generator interface.
1789 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1790 return &ia32_code_gen_if;
1794 * Returns the estimated execution time of an ia32 irn.
1796 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1797 const arch_env_t *arch_env = env;
1798 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1801 list_sched_selector_t ia32_sched_selector;
1804 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1806 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1807 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1808 ia32_sched_selector.exectime = ia32_sched_exectime;
1809 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1810 return &ia32_sched_selector;
1813 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
1818 * Returns the necessary byte alignment for storing a register of given class.
1820 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1821 ir_mode *mode = arch_register_class_mode(cls);
1822 int bytes = get_mode_size_bytes(mode);
1824 if (mode_is_float(mode) && bytes > 8)
1829 static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
1830 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1831 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1832 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1835 static const be_execution_unit_t *_allowed_units_GP[] = {
1836 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1837 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1838 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1839 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1840 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1841 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1842 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1845 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1846 &be_machine_execution_units_DUMMY[0],
1849 static const be_execution_unit_t **_units_callret[] = {
1850 _allowed_units_BRANCH,
1853 static const be_execution_unit_t **_units_other[] = {
1857 static const be_execution_unit_t **_units_dummy[] = {
1858 _allowed_units_DUMMY,
1861 const be_execution_unit_t ***ret;
1863 if (is_ia32_irn(irn)) {
1864 ret = get_ia32_exec_units(irn);
1866 else if (is_be_node(irn)) {
1867 if (be_is_Call(irn) || be_is_Return(irn)) {
1868 ret = _units_callret;
1870 else if (be_is_Barrier(irn)) {
1885 * Return the abstract ia32 machine.
1887 static const be_machine_t *ia32_get_machine(const void *self) {
1888 const ia32_isa_t *isa = self;
1893 * Return irp irgs in the desired order.
1895 static ir_graph **ia32_get_irg_list(const void *self, ir_graph **irg_list) {
1900 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1901 * @return 1 if allowed, 0 otherwise
1903 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1905 ir_node *cmp, *cmp_a, *phi;
1908 /* we don't want long long an floating point Psi */
1909 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
1911 if (get_irn_mode(sel) != mode_b)
1914 cmp = get_Proj_pred(sel);
1915 cmp_a = get_Cmp_left(cmp);
1916 mode = get_irn_mode(cmp_a);
1918 if (IS_BAD_PSI_MODE(mode))
1921 /* check the Phi nodes */
1922 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1923 ir_node *pred_i = get_irn_n(phi, i);
1924 ir_node *pred_j = get_irn_n(phi, j);
1925 ir_mode *mode_i = get_irn_mode(pred_i);
1926 ir_mode *mode_j = get_irn_mode(pred_j);
1928 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1932 #undef IS_BAD_PSI_MODE
1937 static ia32_intrinsic_env_t intrinsic_env = {
1938 NULL, /**< the irg, these entities belong to */
1939 NULL, /**< entity for first div operand (move into FPU) */
1940 NULL, /**< entity for second div operand (move into FPU) */
1941 NULL, /**< entity for converts ll -> d */
1942 NULL, /**< entity for converts d -> ll */
1946 * Returns the libFirm configuration parameter for this backend.
1948 static const backend_params *ia32_get_libfirm_params(void) {
1949 static const opt_if_conv_info_t ifconv = {
1950 4, /* maxdepth, doesn't matter for Psi-conversion */
1951 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
1953 static const arch_dep_params_t ad = {
1954 1, /* also use subs */
1955 4, /* maximum shifts */
1956 31, /* maximum shift amount */
1958 1, /* allow Mulhs */
1959 1, /* allow Mulus */
1960 32 /* Mulh allowed up to 32 bit */
1962 static backend_params p = {
1963 NULL, /* no additional opcodes */
1964 NULL, /* will be set later */
1965 1, /* need dword lowering */
1966 ia32_create_intrinsic_fkt,
1967 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1968 NULL, /* will be set later */
1972 p.if_conv_info = &ifconv;
1977 /* instruction set architectures. */
1978 static const lc_opt_enum_int_items_t arch_items[] = {
1979 { "386", arch_i386, },
1980 { "486", arch_i486, },
1981 { "pentium", arch_pentium, },
1982 { "586", arch_pentium, },
1983 { "pentiumpro", arch_pentium_pro, },
1984 { "686", arch_pentium_pro, },
1985 { "pentiummmx", arch_pentium_mmx, },
1986 { "pentium2", arch_pentium_2, },
1987 { "p2", arch_pentium_2, },
1988 { "pentium3", arch_pentium_3, },
1989 { "p3", arch_pentium_3, },
1990 { "pentium4", arch_pentium_4, },
1991 { "p4", arch_pentium_4, },
1992 { "pentiumm", arch_pentium_m, },
1993 { "pm", arch_pentium_m, },
1994 { "core", arch_core, },
1996 { "athlon", arch_athlon, },
1997 { "athlon64", arch_athlon_64, },
1998 { "opteron", arch_opteron, },
2002 static lc_opt_enum_int_var_t arch_var = {
2003 &ia32_isa_template.arch, arch_items
2006 static lc_opt_enum_int_var_t opt_arch_var = {
2007 &ia32_isa_template.opt_arch, arch_items
2010 static const lc_opt_enum_int_items_t fp_unit_items[] = {
2012 { "sse2", fp_sse2 },
2016 static lc_opt_enum_int_var_t fp_unit_var = {
2017 &ia32_isa_template.fp_kind, fp_unit_items
2020 static const lc_opt_enum_int_items_t gas_items[] = {
2021 { "linux", ASM_LINUX_GAS },
2022 { "mingw", ASM_MINGW_GAS },
2026 static lc_opt_enum_int_var_t gas_var = {
2027 (int *)&asm_flavour, gas_items
2030 static const lc_opt_table_entry_t ia32_options[] = {
2031 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
2032 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
2033 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
2034 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
2035 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
2036 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
2037 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
2038 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
2039 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2042 #endif /* WITH_LIBCORE */
2044 const arch_isa_if_t ia32_isa_if = {
2047 ia32_get_n_reg_class,
2049 ia32_get_reg_class_for_mode,
2051 ia32_get_irn_handler,
2052 ia32_get_code_generator_if,
2053 ia32_get_list_sched_selector,
2054 ia32_get_ilp_sched_selector,
2055 ia32_get_reg_class_alignment,
2056 ia32_get_libfirm_params,
2057 ia32_get_allowed_execution_units,
2062 void be_init_arch_ia32(void)
2064 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2065 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2067 lc_opt_add_table(ia32_grp, ia32_options);
2068 be_register_isa_if("ia32", &ia32_isa_if);
2071 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);