11 #include "pseudo_irg.h"
15 #include "iredges_t.h"
22 #include "../beabi.h" /* the general register allocator interface */
23 #include "../benode_t.h"
24 #include "../belower.h"
25 #include "../besched_t.h"
26 #include "bearch_ia32_t.h"
28 #include "ia32_new_nodes.h" /* ia32 nodes interface */
29 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
30 #include "ia32_gen_decls.h" /* interface declaration emitter */
31 #include "ia32_transform.h"
32 #include "ia32_emitter.h"
33 #include "ia32_map_regs.h"
34 #include "ia32_optimize.h"
36 #define DEBUG_MODULE "firm.be.ia32.isa"
39 static set *cur_reg_set = NULL;
42 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
44 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
46 cg->noreg_gp = be_new_NoReg(&ia32_gp_regs[REG_XXX], cg->irg, get_irg_start_block(cg->irg));
52 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
54 cg->noreg_fp = be_new_NoReg(&ia32_fp_regs[REG_XXXX], cg->irg, get_irg_start_block(cg->irg));
60 /**************************************************
63 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
64 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
65 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
66 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
69 **************************************************/
71 static ir_node *my_skip_proj(const ir_node *n) {
77 static int is_Call_Proj(const ir_node *n) {
79 is_Proj(get_Proj_pred(n)) &&
80 get_irn_mode(get_Proj_pred(n)) == mode_T &&
81 is_ia32_Call(get_Proj_pred(get_Proj_pred(n))))
89 static int is_Start_Proj(const ir_node *n) {
91 is_Proj(get_Proj_pred(n)) &&
92 get_irn_mode(get_Proj_pred(n)) == mode_T &&
93 is_Start(get_Proj_pred(get_Proj_pred(n))))
101 static int is_P_frame_base_Proj(const ir_node *n) {
103 is_Start(get_Proj_pred(n)) &&
104 get_Proj_proj(n) == pn_Start_P_frame_base)
112 static int is_used_by_Keep(const ir_node *n) {
113 return be_is_Keep(get_edge_src_irn(get_irn_out_edge_first(n)));
117 * Return register requirements for an ia32 node.
118 * If the node returns a tuple (mode_T) then the proj's
119 * will be asked for this information.
121 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
122 const ia32_register_req_t *irn_req;
123 long node_pos = pos == -1 ? 0 : pos;
124 ir_mode *mode = get_irn_mode(irn);
125 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
126 const ia32_irn_ops_t *ops = self;
128 if (mode == mode_T || mode == mode_M) {
129 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
133 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
136 if (is_Call_Proj(irn) && is_used_by_Keep(irn)) {
141 irn_req = ia32_projnum_reg_req_map[get_Proj_proj(irn)];
142 memcpy(req, &(irn_req->req), sizeof(*req));
147 else if (is_Start_Proj(irn)) {
148 irn_req = ops->cg->reg_param_req[get_Proj_proj(irn)];
149 assert(irn_req && "missing requirement for regparam");
150 memcpy(req, &(irn_req->req), sizeof(*req));
154 else if (is_Proj(irn)) {
156 node_pos = ia32_translate_proj_pos(irn);
162 irn = my_skip_proj(irn);
164 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
167 if (is_ia32_irn(irn)) {
169 irn_req = get_ia32_in_req(irn, pos);
172 irn_req = get_ia32_out_req(irn, node_pos);
175 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
177 memcpy(req, &(irn_req->req), sizeof(*req));
179 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
180 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
181 req->other_same = get_irn_n(irn, irn_req->same_pos);
184 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
185 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
186 req->other_different = get_irn_n(irn, irn_req->different_pos);
190 /* treat Phi like Const with default requirements */
192 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
193 if (mode_is_float(mode))
194 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
195 else if (mode_is_int(mode) || mode_is_reference(mode))
196 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
197 else if (mode == mode_T || mode == mode_M) {
198 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
202 assert(0 && "unsupported Phi-Mode");
204 else if (is_Start(irn)) {
205 DB((mod, LEVEL_1, "returning reqs none for ProjX -> Start (%+F )\n", irn));
207 case pn_Start_X_initial_exec:
208 case pn_Start_P_value_arg_base:
209 case pn_Start_P_globals:
210 case pn_Start_P_frame_base:
211 memcpy(req, &(ia32_default_req_none.req), sizeof(*req));
213 case pn_Start_T_args:
214 assert(0 && "ProjT(pn_Start_T_args) should not be asked");
217 else if (get_irn_op(irn) == op_Return && pos > 0) {
218 DB((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
219 memcpy(req, &(ia32_default_req_ia32_gp_eax.req), sizeof(*req));
222 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
230 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
234 pos = ia32_translate_proj_pos(irn);
235 irn = my_skip_proj(irn);
238 if (is_ia32_irn(irn)) {
239 const arch_register_t **slots;
241 slots = get_ia32_slots(irn);
245 ia32_set_firm_reg(irn, reg, cur_reg_set);
249 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
251 const arch_register_t *reg = NULL;
254 pos = ia32_translate_proj_pos(irn);
255 irn = my_skip_proj(irn);
258 if (is_ia32_irn(irn)) {
259 const arch_register_t **slots;
260 slots = get_ia32_slots(irn);
264 reg = ia32_get_firm_reg(irn, cur_reg_set);
270 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
271 irn = my_skip_proj(irn);
273 return arch_irn_class_branch;
274 else if (is_ia32_Call(irn))
275 return arch_irn_class_call;
276 else if (is_ia32_irn(irn))
277 return arch_irn_class_normal;
282 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
283 irn = my_skip_proj(irn);
284 if (is_ia32_irn(irn))
285 return get_ia32_flags(irn);
291 /* fill register allocator interface */
293 static const arch_irn_ops_if_t ia32_irn_ops_if = {
294 ia32_get_irn_reg_req,
301 ia32_irn_ops_t ia32_irn_ops = {
308 /**************************************************
311 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
312 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
313 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
314 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
317 **************************************************/
320 * Transforms the standard firm graph into
323 static void ia32_prepare_graph(void *self) {
324 ia32_code_gen_t *cg = self;
326 if (! is_pseudo_ir_graph(cg->irg)) {
327 irg_walk_blkwise_graph(cg->irg, ia32_place_consts, ia32_transform_node, cg);
328 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
335 * Stack reservation and StackParam lowering.
337 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
339 firm_dbg_module_t *mod = cg->mod;
340 ir_node *frame = get_irg_frame(irg);
341 ir_node *end_block = get_irg_end_block(irg);
342 ir_node **returns, **in, **new_in;
343 ir_node *stack_reserve, *sched_point;
344 ir_node *stack_free, *new_ret, *return_block;
345 int stack_size = 0, i, n_arg;
346 arch_register_t *stack_reg;
347 tarval *stack_size_tv;
350 /* Determine stack register */
351 if (cg->has_alloca) {
352 stack_reg = &ia32_gp_regs[REG_EBP];
355 stack_reg = &ia32_gp_regs[REG_ESP];
358 /* If frame is used, then we need to reserve some stackspace. */
359 if (get_irn_n_edges(frame) > 0) {
360 /* The initial stack reservation. */
361 stack_size = get_type_size_bytes(get_irg_frame_type(irg));
362 frame_dbg = get_irn_dbg_info(frame);
363 stack_reserve = new_rd_ia32_Sub_i(frame_dbg, irg, get_nodes_block(frame), new_NoMem(), mode_Is);
364 stack_size_tv = new_tarval_from_long(stack_size, mode_Is);
365 set_ia32_Immop_tarval(stack_reserve, stack_size_tv);
367 assert(stack_size && "bOrken stack layout");
369 /* reroute all edges from frame pointer to corrected frame pointer */
370 edges_reroute(frame, stack_reserve, irg);
371 set_irn_n(stack_reserve, 0, frame);
373 /* schedule frame pointer */
374 if (! sched_is_scheduled(frame)) {
375 sched_add_after(get_irg_start(irg), frame);
379 arch_set_irn_register(cg->arch_env, frame, stack_reg);
380 arch_set_irn_register(cg->arch_env, stack_reserve, stack_reg);
382 /* insert into schedule */
383 sched_add_after(frame, stack_reserve);
385 /* Free stack for each Return node */
386 returns = get_Block_cfgpred_arr(end_block);
387 for (i = 0; i < get_Block_n_cfgpreds(end_block); i++) {
388 assert(get_irn_opcode(returns[i]) == iro_Return && "cfgpred of endblock is not a return");
390 return_block = get_nodes_block(returns[i]);
393 stack_free = new_rd_ia32_Add_i(frame_dbg, irg, return_block, stack_reserve, mode_Is);
394 set_ia32_Immop_tarval(stack_free, stack_size_tv);
395 arch_set_irn_register(cg->arch_env, stack_free, stack_reg);
397 DBG((mod, LEVEL_1, "examining %+F, %+F created, block %+F", returns[i], stack_free, return_block));
399 /* get the old Return arguments */
400 n_arg = get_Return_n_ress(returns[i]);
401 in = get_Return_res_arr(returns[i]);
402 new_in = alloca((n_arg + 2) * sizeof(new_in[0]));
404 /* copy the old to the new in's */
405 memcpy(new_in, in, n_arg * sizeof(in[0]));
406 new_in[n_arg++] = stack_free;
407 new_in[n_arg++] = get_Return_mem(returns[i]);
409 /* create the new return node */
410 new_ret = new_rd_ia32_Return(get_irn_dbg_info(returns[i]), irg, return_block, n_arg, new_in);
412 /* In case the return node is the only node in the block, */
413 /* it is not scheduled, so we need this work-around. */
414 if (! sched_is_scheduled(returns[i])) {
415 sched_point = return_block;
418 sched_point = sched_prev(returns[i]);
419 sched_remove(returns[i]);
422 /* exchange the old return with the new one */
423 exchange(returns[i], new_ret);
425 DB((mod, LEVEL_1, " ... replaced with %+F\n", new_ret));
427 /* remove the old one from schedule and add the new nodes properly */
428 sched_add_after(sched_point, new_ret);
429 sched_add_after(sched_point, stack_free);
438 * Dummy functions for hooks we don't need but which must be filled.
440 static void ia32_before_sched(void *self) {
441 ia32_code_gen_t *cg = self;
443 lower_nodes_before_sched(cg->irg, cg->arch_env);
446 static void ia32_before_ra(void *self) {
451 * Creates a Store for a Spill
453 static ir_node *ia32_lower_spill(void *self, ir_node *spill) {
454 ia32_code_gen_t *cg = self;
455 ir_graph *irg = cg->irg;
456 dbg_info *dbg = get_irn_dbg_info(spill);
457 ir_node *block = get_nodes_block(spill);
458 ir_node *ptr = get_irg_frame(irg);
459 ir_node *val = be_get_Spill_context(spill);
460 ir_node *mem = new_rd_NoMem(irg);
461 ir_mode *mode = get_irn_mode(spill);
462 entity *ent = be_get_spill_entity(spill);
463 unsigned offs = get_entity_offset_bytes(ent);
464 ir_node *noreg, *res;
467 DB((cg->mod, LEVEL_1, "lower_spill: got offset %d for %+F\n", offs, ent));
469 if (mode_is_float(mode)) {
470 ia32_new_NoReg_fp(cg);
471 res = new_rd_ia32_fStore(dbg, irg, block, ptr, noreg, val, mem, mode);
474 ia32_new_NoReg_gp(cg);
475 res = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, mem, mode);
478 snprintf(buf, sizeof(buf), "%d", offs);
479 add_ia32_am_offs(res, buf);
485 * Create a Load for a Spill
487 static ir_node *ia32_lower_reload(void *self, ir_node *reload) {
488 ia32_code_gen_t *cg = self;
489 ir_graph *irg = cg->irg;
490 dbg_info *dbg = get_irn_dbg_info(reload);
491 ir_node *block = get_nodes_block(reload);
492 ir_node *ptr = get_irg_frame(irg);
493 ir_mode *mode = get_irn_mode(reload);
494 ir_node *pred = get_irn_n(reload, 0);
497 ir_node *noreg, *res;
499 /* Get the offset to Load from. It can either be a Spill or a Store. */
500 if (be_is_Spill(pred)) {
501 entity *ent = be_get_spill_entity(pred);
502 unsigned offs = get_entity_offset_bytes(ent);
503 DB((cg->mod, LEVEL_1, "lower_reload: got offset %d for %+F\n", offs, ent));
505 snprintf(buf, sizeof(buf), "%d", offs);
507 else if (is_ia32_Store(pred) || is_ia32_fStore(pred)) {
508 ofs = get_ia32_am_offs(pred);
509 strncpy(buf, ofs, sizeof(buf));
513 assert(0 && "unsupported Reload predecessor");
516 /* Create the Load */
517 if (mode_is_float(mode)) {
518 noreg = ia32_new_NoReg_fp(cg);
519 res = new_rd_ia32_fLoad(dbg, irg, block, ptr, noreg, pred, mode_T);
522 noreg = ia32_new_NoReg_gp(cg);
523 res = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, pred, mode_T);
527 add_ia32_am_offs(res, buf);
529 /* Return the result Proj */
530 return new_rd_Proj(dbg, irg, block, res, mode);
534 * Emits the code, closes the output file and frees
535 * the code generator interface.
537 static void ia32_codegen(void *self) {
538 ia32_code_gen_t *cg = self;
539 ir_graph *irg = cg->irg;
542 if (cg->emit_decls) {
543 ia32_gen_decls(cg->out);
547 ia32_finish_irg(irg, cg);
548 //dump_ir_block_graph_sched(irg, "-finished");
549 ia32_gen_routine(out, irg, cg);
553 pmap_destroy(cg->tv_ent);
554 pmap_destroy(cg->types);
556 /* de-allocate code generator */
557 del_set(cg->reg_set);
561 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env);
563 static const arch_code_generator_if_t ia32_code_gen_if = {
566 ia32_before_sched, /* before scheduling hook */
567 ia32_before_ra, /* before register allocation hook */
570 ia32_codegen /* emit && done */
574 * Initializes the code generator.
576 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env) {
577 ia32_isa_t *isa = (ia32_isa_t *)arch_env->isa;
578 ia32_code_gen_t *cg = xmalloc(sizeof(*cg));
580 cg->impl = &ia32_code_gen_if;
582 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
583 cg->mod = firm_dbg_register("firm.be.ia32.cg");
585 cg->arch_env = arch_env;
586 cg->types = pmap_create();
587 cg->tv_ent = pmap_create();
591 if (isa->num_codegens > 1)
596 cur_reg_set = cg->reg_set;
598 ia32_irn_ops.cg = cg;
600 return (arch_code_generator_t *)cg;
605 /*****************************************************************
606 * ____ _ _ _____ _____
607 * | _ \ | | | | |_ _|/ ____| /\
608 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
609 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
610 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
611 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
613 *****************************************************************/
615 static ia32_isa_t ia32_isa_template = {
617 &ia32_gp_regs[REG_ESP],
618 &ia32_gp_regs[REG_EBP],
625 * Initializes the backend ISA.
627 static void *ia32_init(void) {
628 static int inited = 0;
634 isa = xcalloc(1, sizeof(*isa));
635 memcpy(isa, &ia32_isa_template, sizeof(*isa));
637 isa->reg_projnum_map = new_set(ia32_cmp_reg_projnum_assoc, 1024);
639 ia32_register_init(isa);
640 ia32_create_opcodes();
650 * Closes the output file and frees the ISA structure.
652 static void ia32_done(void *self) {
658 static int ia32_get_n_reg_class(const void *self) {
662 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
663 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
664 return &ia32_reg_classes[i];
668 * Get the register class which shall be used to store a value of a given mode.
669 * @param self The this pointer.
670 * @param mode The mode in question.
671 * @return A register class which can hold values of the given mode.
673 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
674 if (mode_is_float(mode))
675 return &ia32_reg_classes[CLASS_ia32_fp];
677 return &ia32_reg_classes[CLASS_ia32_gp];
681 * Get the ABI restrictions for procedure calls.
682 * @param self The this pointer.
683 * @param method_type The type of the method (procedure) in question.
684 * @param abi The abi object to be modified
686 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
689 unsigned cc = get_method_calling_convention(method_type);
690 int n = get_method_n_params(method_type);
695 const arch_register_t *reg;
697 /* set stack parameter passing style */
698 be_abi_call_set_flags(abi, BE_ABI_LEFT_TO_RIGHT);
700 /* collect the mode for each type */
701 modes = alloca(n * sizeof(modes[0]));
703 for (i = 0; i < n; i++) {
704 tp = get_method_param_type(method_type, i);
705 modes[i] = get_type_mode(tp);
708 /* set register parameters */
709 if (cc & cc_reg_param) {
710 /* determine the number of parameters passed via registers */
711 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore, &ignore);
713 /* loop over all parameters and set the register requirements */
714 for (i = 0; i <= biggest_n; i++) {
715 reg = ia32_get_RegParam_reg(n, modes, i, cc);
716 assert(reg && "kaputt");
717 be_abi_call_param_reg(abi, i, reg);
724 /* set stack parameters */
725 for (i = stack_idx; i < n; i++) {
726 be_abi_call_param_stack(abi, i);
730 /* set return registers */
731 n = get_method_n_ress(method_type);
733 assert(n <= 2 && "more than two results not supported");
735 /* In case of 64bit returns, we will have two 32bit values */
737 tp = get_method_res_type(method_type, 0);
738 mode = get_type_mode(tp);
740 assert(!mode_is_float(mode) && "two FP results not supported");
742 tp = get_method_res_type(method_type, 1);
743 mode = get_type_mode(tp);
745 assert(!mode_is_float(mode) && "two FP results not supported");
747 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
748 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
751 tp = get_method_res_type(method_type, 0);
752 mode = get_type_mode(tp);
754 if (mode_is_float(mode)) {
755 be_abi_call_res_reg(abi, 1, &ia32_fp_regs[REG_XMM0]);
758 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EAX]);
764 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
765 return &ia32_irn_ops;
768 const arch_irn_handler_t ia32_irn_handler = {
772 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
773 return &ia32_irn_handler;
776 long ia32_handle_call_proj(const void *self, ir_node *proj, int is_keep) {
777 ia32_isa_t *isa = (ia32_isa_t *)self;
778 long pn = get_Proj_proj(proj);
781 /* It's not a Keep proj, which means, that it is a result proj. */
782 /* Possible result proj numbers are 0 and 1 */
783 /* Set the correct register (depends on the mode) and the */
784 /* corresponding proj number */
785 if (mode_is_float(get_irn_mode(proj))) {
786 assert(pn == 0 && "only one floating point result supported");
788 /* Get the proj number for the floating point result */
789 pn = ia32_get_reg_projnum(&ia32_fp_regs[REG_XMM0], isa->reg_projnum_map);
792 /* In case of 64bit return value, the result is */
793 /* in EDX:EAX and we have two result projs. */
796 pn = ia32_get_reg_projnum(&ia32_gp_regs[REG_EAX], isa->reg_projnum_map);
799 pn = ia32_get_reg_projnum(&ia32_gp_regs[REG_EDX], isa->reg_projnum_map);
802 assert(0 && "only two int results supported");
806 /* Set the correct proj number */
807 set_Proj_proj(proj, pn);
810 /* Set mode to floating point if required */
811 if (!strcmp(ia32_reg_classes[CLASS_ia32_fp].name,
812 ia32_projnum_reg_req_map[pn]->req.cls->name)) {
813 set_irn_mode(proj, mode_F);
820 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
821 return is_ia32_irn(irn);
825 * Initializes the code generator interface.
827 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
828 return &ia32_code_gen_if;
831 list_sched_selector_t ia32_sched_selector;
834 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
836 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
837 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
838 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
839 return &ia32_sched_selector;
843 static void ia32_register_options(lc_opt_entry_t *ent)
846 #endif /* WITH_LIBCORE */
848 const arch_isa_if_t ia32_isa_if = {
850 ia32_register_options,
854 ia32_get_n_reg_class,
856 ia32_get_reg_class_for_mode,
858 ia32_get_irn_handler,
859 ia32_get_code_generator_if,
860 ia32_get_list_sched_selector,
861 ia32_handle_call_proj