2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
26 #include "pseudo_irg.h"
30 #include "iredges_t.h"
39 #include "../beabi.h" /* the general register allocator interface */
40 #include "../benode_t.h"
41 #include "../belower.h"
42 #include "../besched_t.h"
45 #include "../beirgmod.h"
46 #include "../be_dbgout.h"
47 #include "../beblocksched.h"
48 #include "../bemachine.h"
50 #include "bearch_ia32_t.h"
52 #include "ia32_new_nodes.h" /* ia32 nodes interface */
53 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
54 #include "gen_ia32_machine.h"
55 #include "ia32_gen_decls.h" /* interface declaration emitter */
56 #include "ia32_transform.h"
57 #include "ia32_emitter.h"
58 #include "ia32_map_regs.h"
59 #include "ia32_optimize.h"
61 #include "ia32_dbg_stat.h"
62 #include "ia32_finish.h"
63 #include "ia32_util.h"
65 #define DEBUG_MODULE "firm.be.ia32.isa"
68 static set *cur_reg_set = NULL;
70 /* Creates the unique per irg GP NoReg node. */
71 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
72 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
75 /* Creates the unique per irg FP NoReg node. */
76 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
77 return be_abi_get_callee_save_irn(cg->birg->abi,
78 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
82 * Returns gp_noreg or fp_noreg, depending in input requirements.
84 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
85 arch_register_req_t req;
86 const arch_register_req_t *p_req;
88 p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
89 assert(p_req && "Missing register requirements");
90 if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
91 return ia32_new_NoReg_gp(cg);
93 return ia32_new_NoReg_fp(cg);
96 /**************************************************
99 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
100 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
101 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
102 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
105 **************************************************/
108 * Return register requirements for an ia32 node.
109 * If the node returns a tuple (mode_T) then the proj's
110 * will be asked for this information.
112 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
113 const ia32_irn_ops_t *ops = self;
114 const ia32_register_req_t *irn_req;
115 long node_pos = pos == -1 ? 0 : pos;
116 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
117 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
119 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
120 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
124 if (mode == mode_T && pos < 0) {
125 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
129 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
133 DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
137 node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
138 irn = skip_Proj(irn);
140 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
143 if (is_ia32_irn(irn)) {
144 irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
145 if (irn_req == NULL) {
146 /* no requirements */
150 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
152 memcpy(req, &(irn_req->req), sizeof(*req));
154 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
155 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
156 req->other_same = get_irn_n(irn, irn_req->same_pos);
159 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
160 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
161 req->other_different = get_irn_n(irn, irn_req->different_pos);
165 /* treat Unknowns like Const with default requirements */
166 if (is_Unknown(irn)) {
167 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
168 if (mode_is_float(mode)) {
169 if (USE_SSE2(ops->cg))
170 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
172 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
174 else if (mode_is_int(mode) || mode_is_reference(mode))
175 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
176 else if (mode == mode_T || mode == mode_M) {
177 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
181 assert(0 && "unsupported Unknown-Mode");
184 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
192 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
194 const ia32_irn_ops_t *ops = self;
196 if (get_irn_mode(irn) == mode_X) {
200 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
203 pos = get_Proj_proj(irn);
204 irn = skip_Proj(irn);
207 if (is_ia32_irn(irn)) {
208 const arch_register_t **slots;
210 slots = get_ia32_slots(irn);
214 ia32_set_firm_reg(irn, reg, cur_reg_set);
218 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
220 const arch_register_t *reg = NULL;
224 if (get_irn_mode(irn) == mode_X) {
228 pos = get_Proj_proj(irn);
229 irn = skip_Proj(irn);
232 if (is_ia32_irn(irn)) {
233 const arch_register_t **slots;
234 slots = get_ia32_slots(irn);
238 reg = ia32_get_firm_reg(irn, cur_reg_set);
244 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
245 arch_irn_class_t classification = arch_irn_class_normal;
247 irn = skip_Proj(irn);
250 classification |= arch_irn_class_branch;
252 if (! is_ia32_irn(irn))
253 return classification & ~arch_irn_class_normal;
255 if (is_ia32_Cnst(irn))
256 classification |= arch_irn_class_const;
259 classification |= arch_irn_class_load;
261 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
262 classification |= arch_irn_class_store;
264 if (is_ia32_got_reload(irn))
265 classification |= arch_irn_class_reload;
267 return classification;
270 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
271 arch_irn_flags_t flags;
272 ir_node *pred = is_Proj(irn) && mode_is_datab(get_irn_mode(irn)) ? get_Proj_pred(irn) : NULL;
275 flags = arch_irn_flags_ignore;
277 /* pred is only set, if we have a Proj */
278 flags = pred && is_ia32_irn(pred) ? get_ia32_out_flags(pred, get_Proj_proj(irn)) : arch_irn_flags_none;
280 irn = skip_Proj(irn);
281 if (is_ia32_irn(irn))
282 flags |= get_ia32_flags(irn);
289 * The IA32 ABI callback object.
292 be_abi_call_flags_bits_t flags; /**< The call flags. */
293 const arch_isa_t *isa; /**< The ISA handle. */
294 const arch_env_t *aenv; /**< The architecture environment. */
295 ir_graph *irg; /**< The associated graph. */
298 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
299 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
302 static void ia32_set_frame_entity(const void *self, ir_node *irn, entity *ent) {
303 set_ia32_frame_ent(irn, ent);
306 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
308 const ia32_irn_ops_t *ops = self;
310 if (get_ia32_frame_ent(irn)) {
311 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
313 if(is_ia32_Pop(irn)) {
314 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
316 /* Pop nodes modify the stack pointer before calculating the destination
317 * address, so fix this here
323 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
325 snprintf(buf, sizeof(buf), "%d", bias);
327 if (get_ia32_op_type(irn) == ia32_Normal) {
328 set_ia32_cnst(irn, buf);
330 add_ia32_am_offs(irn, buf);
332 set_ia32_am_flavour(irn, am_flav);
337 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
339 long proj = get_Proj_proj(irn);
340 ir_node *pred = get_Proj_pred(irn);
342 if (proj == pn_ia32_Push_stack && is_ia32_Push(pred))
344 if (proj == pn_ia32_Pop_stack && is_ia32_Pop(pred))
352 * Put all registers which are saved by the prologue/epilogue in a set.
354 * @param self The callback object.
355 * @param s The result set.
357 static void ia32_abi_dont_save_regs(void *self, pset *s)
359 ia32_abi_env_t *env = self;
360 if(env->flags.try_omit_fp)
361 pset_insert_ptr(s, env->isa->bp);
365 * Generate the routine prologue.
367 * @param self The callback object.
368 * @param mem A pointer to the mem node. Update this if you define new memory.
369 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
371 * @return The register which shall be used as a stack frame base.
373 * All nodes which define registers in @p reg_map must keep @p reg_map current.
375 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
377 ia32_abi_env_t *env = self;
379 if (! env->flags.try_omit_fp) {
380 ir_node *bl = get_irg_start_block(env->irg);
381 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
382 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
383 ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
387 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
388 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
389 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
391 /* the push must have SP out register */
392 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
393 set_ia32_flags(push, arch_irn_flags_ignore);
395 /* move esp to ebp */
396 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
397 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
398 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
399 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
401 /* beware: the copy must be done before any other sp use */
402 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
403 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
404 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
405 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
407 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
408 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
417 * Generate the routine epilogue.
418 * @param self The callback object.
419 * @param bl The block for the epilog
420 * @param mem A pointer to the mem node. Update this if you define new memory.
421 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
422 * @return The register which shall be used as a stack frame base.
424 * All nodes which define registers in @p reg_map must keep @p reg_map current.
426 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
428 ia32_abi_env_t *env = self;
429 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
430 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
432 if (env->flags.try_omit_fp) {
433 /* simply remove the stack frame here */
434 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
435 add_irn_dep(curr_sp, *mem);
438 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
439 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
441 /* gcc always emits a leave at the end of a routine */
442 if (1 || ARCH_AMD(isa->opt_arch)) {
446 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
447 set_ia32_flags(leave, arch_irn_flags_ignore);
448 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
449 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
450 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
453 ir_node *noreg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_GP_NOREG]);
456 /* copy ebp to esp */
457 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
460 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
461 set_ia32_flags(pop, arch_irn_flags_ignore);
462 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
463 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
464 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
466 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
467 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
470 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
471 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
475 * Initialize the callback object.
476 * @param call The call object.
477 * @param aenv The architecture environment.
478 * @param irg The graph with the method.
479 * @return Some pointer. This pointer is passed to all other callback functions as self object.
481 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
483 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
484 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
485 env->flags = fl.bits;
488 env->isa = aenv->isa;
493 * Destroy the callback object.
494 * @param self The callback object.
496 static void ia32_abi_done(void *self) {
501 * Produces the type which sits between the stack args and the locals on the stack.
502 * it will contain the return address and space to store the old base pointer.
503 * @return The Firm type modeling the ABI between type.
505 static ir_type *ia32_abi_get_between_type(void *self)
507 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
508 static ir_type *omit_fp_between_type = NULL;
509 static ir_type *between_type = NULL;
511 ia32_abi_env_t *env = self;
513 if (! between_type) {
515 entity *ret_addr_ent;
516 entity *omit_fp_ret_addr_ent;
518 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_P);
519 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_P);
521 between_type = new_type_struct(IDENT("ia32_between_type"));
522 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
523 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
525 set_entity_offset_bytes(old_bp_ent, 0);
526 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
527 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
528 set_type_state(between_type, layout_fixed);
530 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
531 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
533 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
534 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
535 set_type_state(omit_fp_between_type, layout_fixed);
538 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
543 * Get the estimated cycle count for @p irn.
545 * @param self The this pointer.
546 * @param irn The node.
548 * @return The estimated cycle count for this operation
550 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
553 ia32_op_type_t op_tp;
554 const ia32_irn_ops_t *ops = self;
558 if (!is_ia32_irn(irn))
561 assert(is_ia32_irn(irn));
563 cost = get_ia32_latency(irn);
564 op_tp = get_ia32_op_type(irn);
566 if (is_ia32_CopyB(irn)) {
568 if (ARCH_INTEL(ops->cg->arch))
571 else if (is_ia32_CopyB_i(irn)) {
572 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
573 cost = 20 + (int)ceil((4/3) * size);
574 if (ARCH_INTEL(ops->cg->arch))
577 /* in case of address mode operations add additional cycles */
578 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
580 In case of stack access add 5 cycles (we assume stack is in cache),
581 other memory operations cost 20 cycles.
583 cost += is_ia32_use_frame(irn) ? 5 : 20;
590 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
592 * @param irn The original operation
593 * @param i Index of the argument we want the inverse operation to yield
594 * @param inverse struct to be filled with the resulting inverse op
595 * @param obstack The obstack to use for allocation of the returned nodes array
596 * @return The inverse operation or NULL if operation invertible
598 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
601 ir_node *block, *noreg, *nomem;
604 /* we cannot invert non-ia32 irns */
605 if (! is_ia32_irn(irn))
608 /* operand must always be a real operand (not base, index or mem) */
609 if (i != 2 && i != 3)
612 /* we don't invert address mode operations */
613 if (get_ia32_op_type(irn) != ia32_Normal)
616 irg = get_irn_irg(irn);
617 block = get_nodes_block(irn);
618 mode = get_ia32_res_mode(irn);
619 noreg = get_irn_n(irn, 0);
620 nomem = new_r_NoMem(irg);
622 /* initialize structure */
623 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
627 switch (get_ia32_irn_opcode(irn)) {
629 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
630 /* we have an add with a const here */
631 /* invers == add with negated const */
632 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
633 pnc = pn_ia32_Add_res;
635 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
636 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
637 set_ia32_commutative(inverse->nodes[0]);
639 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
640 /* we have an add with a symconst here */
641 /* invers == sub with const */
642 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
643 pnc = pn_ia32_Sub_res;
645 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
648 /* normal add: inverse == sub */
649 ir_node *proj = ia32_get_res_proj(irn);
652 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
653 pnc = pn_ia32_Sub_res;
658 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
659 /* we have a sub with a const/symconst here */
660 /* invers == add with this const */
661 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
662 pnc = pn_ia32_Add_res;
663 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
664 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
668 ir_node *proj = ia32_get_res_proj(irn);
672 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
675 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
677 pnc = pn_ia32_Sub_res;
682 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
683 /* xor with const: inverse = xor */
684 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
685 pnc = pn_ia32_Eor_res;
686 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
687 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
691 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
692 pnc = pn_ia32_Eor_res;
697 ir_node *proj = ia32_get_res_proj(irn);
700 inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, proj, nomem);
701 pnc = pn_ia32_Not_res;
705 case iro_ia32_Minus: {
706 ir_node *proj = ia32_get_res_proj(irn);
709 inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, proj, nomem);
710 pnc = pn_ia32_Minus_res;
715 /* inverse operation not supported */
719 set_ia32_res_mode(inverse->nodes[0], mode);
720 inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
726 * Check if irn can load it's operand at position i from memory (source addressmode).
727 * @param self Pointer to irn ops itself
728 * @param irn The irn to be checked
729 * @param i The operands position
730 * @return Non-Zero if operand can be loaded
732 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
733 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
734 get_irn_arity(irn) != 5 || /* must be a binary operation */
735 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
736 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
737 (i != 2 && i != 3) || /* a "real" operand position must be requested */
738 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
739 is_ia32_use_frame(irn)) /* must not already use frame */
745 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
746 const ia32_irn_ops_t *ops = self;
747 ia32_code_gen_t *cg = ops->cg;
749 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
752 ir_node *tmp = get_irn_n(irn, 3);
753 set_irn_n(irn, 3, get_irn_n(irn, 2));
754 set_irn_n(irn, 2, tmp);
757 set_ia32_am_support(irn, ia32_am_Source);
758 set_ia32_op_type(irn, ia32_AddrModeS);
759 set_ia32_am_flavour(irn, ia32_B);
760 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
761 set_ia32_use_frame(irn);
762 set_ia32_got_reload(irn);
764 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
765 set_irn_n(irn, 4, spill);
768 Input at position one is index register, which is NoReg.
769 We would need cg object to get a real noreg, but we cannot
772 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
774 //FIXME DBG_OPT_AM_S(reload, irn);
777 static const be_abi_callbacks_t ia32_abi_callbacks = {
780 ia32_abi_get_between_type,
781 ia32_abi_dont_save_regs,
786 /* fill register allocator interface */
788 static const arch_irn_ops_if_t ia32_irn_ops_if = {
789 ia32_get_irn_reg_req,
794 ia32_get_frame_entity,
795 ia32_set_frame_entity,
796 ia32_set_frame_offset,
799 ia32_get_op_estimated_cost,
800 ia32_possible_memory_operand,
801 ia32_perform_memory_operand,
804 ia32_irn_ops_t ia32_irn_ops = {
811 /**************************************************
814 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
815 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
816 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
817 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
820 **************************************************/
822 static void ia32_kill_convs(ia32_code_gen_t *cg) {
825 /* BEWARE: the Projs are inserted in the set */
826 foreach_nodeset(cg->kill_conv, irn) {
827 ir_node *in = get_irn_n(get_Proj_pred(irn), 2);
828 edges_reroute(irn, in, cg->birg->irg);
833 * Transform the Thread Local Store base.
835 static void transform_tls(ir_graph *irg) {
836 ir_node *irn = get_irg_tls(irg);
839 dbg_info *dbg = get_irn_dbg_info(irn);
840 ir_node *blk = get_nodes_block(irn);
842 newn = new_rd_ia32_LdTls(dbg, irg, blk, get_irn_mode(irn));
849 * Transforms the standard firm graph into
852 static void ia32_prepare_graph(void *self) {
853 ia32_code_gen_t *cg = self;
854 dom_front_info_t *dom;
855 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
857 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
859 /* 1st: transform constants and psi condition trees */
860 ia32_pre_transform_phase(cg);
862 /* 2nd: transform all remaining nodes */
863 ia32_register_transformers();
864 dom = be_compute_dominance_frontiers(cg->irg);
866 cg->kill_conv = new_nodeset(5);
867 transform_tls(cg->irg);
868 edges_deactivate(cg->irg);
869 edges_activate(cg->irg);
870 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
872 del_nodeset(cg->kill_conv);
874 be_free_dominance_frontiers(dom);
877 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
879 /* 3rd: optimize address mode */
880 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
881 ia32_optimize_addressmode(cg);
884 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
886 DEBUG_ONLY(cg->mod = old_mod;)
890 * Dummy functions for hooks we don't need but which must be filled.
892 static void ia32_before_sched(void *self) {
895 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
898 ir_node *mem_proj = NULL;
903 mode = get_irn_mode(irn);
905 /* check if we already saw this node or the node has more than one user */
906 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
910 /* mark irn visited */
911 bitset_add_irn(already_visited, irn);
913 /* non-Tuple nodes with one user: ok, return */
914 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
918 /* tuple node has one user which is not the mem proj-> ok */
919 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
920 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
921 if (mem_proj == NULL) {
926 arity = get_irn_arity(irn);
927 for (i = 0; i < arity; ++i) {
928 ir_node *pred = get_irn_n(irn, i);
930 /* do not follow memory edges or we will accidentally remove stores */
931 if (get_irn_mode(pred) == mode_M) {
932 if(mem_proj != NULL) {
933 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
939 set_irn_n(irn, i, new_Bad());
942 The current node is about to be removed: if the predecessor
943 has only this node as user, it need to be removed as well.
945 if (get_irn_n_edges(pred) <= 1)
946 remove_unused_nodes(pred, already_visited);
949 // we need to set the presd to Bad again to also get the memory edges
950 arity = get_irn_arity(irn);
951 for (i = 0; i < arity; ++i) {
952 set_irn_n(irn, i, new_Bad());
955 if (sched_is_scheduled(irn)) {
960 static void remove_unused_loads_walker(ir_node *irn, void *env) {
961 bitset_t *already_visited = env;
962 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
963 remove_unused_nodes(irn, env);
967 * Called before the register allocator.
968 * Calculate a block schedule here. We need it for the x87
969 * simulator and the emitter.
971 static void ia32_before_ra(void *self) {
972 ia32_code_gen_t *cg = self;
973 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
977 There are sometimes unused loads, only pinned by memory.
978 We need to remove those Loads and all other nodes which won't be used
979 after removing the Load from schedule.
981 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
986 * Transforms a be node into a Load.
988 static void transform_to_Load(ia32_transform_env_t *env) {
989 ir_node *irn = env->irn;
990 entity *ent = be_get_frame_entity(irn);
991 ir_mode *mode = env->mode;
992 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
993 ir_node *nomem = new_rd_NoMem(env->irg);
994 ir_node *sched_point = NULL;
995 ir_node *ptr = get_irn_n(irn, 0);
996 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
997 ir_node *new_op, *proj;
998 const arch_register_t *reg;
1000 if (sched_is_scheduled(irn)) {
1001 sched_point = sched_prev(irn);
1004 if (mode_is_float(mode)) {
1005 if (USE_SSE2(env->cg))
1006 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
1008 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
1011 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
1013 set_ia32_am_support(new_op, ia32_am_Source);
1014 set_ia32_op_type(new_op, ia32_AddrModeS);
1015 set_ia32_am_flavour(new_op, ia32_B);
1016 set_ia32_ls_mode(new_op, mode);
1017 set_ia32_frame_ent(new_op, ent);
1018 set_ia32_use_frame(new_op);
1020 DBG_OPT_RELOAD2LD(irn, new_op);
1022 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1025 sched_add_after(sched_point, new_op);
1026 sched_add_after(new_op, proj);
1031 /* copy the register from the old node to the new Load */
1032 reg = arch_get_irn_register(env->cg->arch_env, irn);
1033 arch_set_irn_register(env->cg->arch_env, new_op, reg);
1035 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
1037 exchange(irn, proj);
1041 * Transforms a be node into a Store.
1043 static void transform_to_Store(ia32_transform_env_t *env) {
1044 ir_node *irn = env->irn;
1045 entity *ent = be_get_frame_entity(irn);
1046 ir_mode *mode = env->mode;
1047 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1048 ir_node *nomem = new_rd_NoMem(env->irg);
1049 ir_node *ptr = get_irn_n(irn, 0);
1050 ir_node *val = get_irn_n(irn, 1);
1051 ir_node *new_op, *proj;
1052 ir_node *sched_point = NULL;
1054 if (sched_is_scheduled(irn)) {
1055 sched_point = sched_prev(irn);
1058 if (mode_is_float(mode)) {
1059 if (USE_SSE2(env->cg))
1060 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1062 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1064 else if (get_mode_size_bits(mode) == 8) {
1065 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1068 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
1071 set_ia32_am_support(new_op, ia32_am_Dest);
1072 set_ia32_op_type(new_op, ia32_AddrModeD);
1073 set_ia32_am_flavour(new_op, ia32_B);
1074 set_ia32_ls_mode(new_op, mode);
1075 set_ia32_frame_ent(new_op, ent);
1076 set_ia32_use_frame(new_op);
1078 DBG_OPT_SPILL2ST(irn, new_op);
1080 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
1083 sched_add_after(sched_point, new_op);
1087 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
1089 exchange(irn, proj);
1092 static ir_node *create_push(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, ir_node *mem, entity *ent) {
1093 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1094 ir_node *frame = get_irg_frame(env->irg);
1096 ir_node *push = new_rd_ia32_Push(env->dbg, env->irg, env->block, frame, noreg, noreg, sp, mem);
1098 set_ia32_frame_ent(push, ent);
1099 set_ia32_use_frame(push);
1100 set_ia32_op_type(push, ia32_AddrModeS);
1101 set_ia32_am_flavour(push, ia32_B);
1102 set_ia32_ls_mode(push, mode_Is);
1104 sched_add_before(schedpoint, push);
1108 static ir_node *create_pop(ia32_transform_env_t *env, ir_node *schedpoint, ir_node *sp, entity *ent) {
1109 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1110 ir_node *frame = get_irg_frame(env->irg);
1112 ir_node *pop = new_rd_ia32_Pop(env->dbg, env->irg, env->block, frame, noreg, sp, new_NoMem());
1114 set_ia32_frame_ent(pop, ent);
1115 set_ia32_use_frame(pop);
1116 set_ia32_op_type(pop, ia32_AddrModeD);
1117 set_ia32_am_flavour(pop, ia32_B);
1118 set_ia32_ls_mode(pop, mode_Is);
1120 sched_add_before(schedpoint, pop);
1125 static ir_node* create_spproj(ia32_transform_env_t *env, ir_node *pred, int pos, ir_node *schedpoint) {
1126 ir_mode *spmode = mode_Iu;
1127 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1130 sp = new_rd_Proj(env->dbg, env->irg, env->block, pred, spmode, pos);
1131 arch_set_irn_register(env->cg->arch_env, sp, spreg);
1132 sched_add_before(schedpoint, sp);
1138 * Transform memperm, currently we do this the ugly way and produce
1139 * push/pop into/from memory cascades. This is possible without using
1142 static void transform_MemPerm(ia32_transform_env_t *env) {
1143 ir_node *node = env->irn;
1145 ir_node *sp = be_abi_get_ignore_irn(env->cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1146 const ir_edge_t *edge;
1147 const ir_edge_t *next;
1150 arity = be_get_MemPerm_entity_arity(node);
1151 pops = alloca(arity * sizeof(pops[0]));
1154 for(i = 0; i < arity; ++i) {
1155 entity *ent = be_get_MemPerm_in_entity(node, i);
1156 ir_type *enttype = get_entity_type(ent);
1157 int entbits = get_type_size_bits(enttype);
1158 ir_node *mem = get_irn_n(node, i + 1);
1161 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1163 push = create_push(env, node, sp, mem, ent);
1164 sp = create_spproj(env, push, 0, node);
1166 // add another push after the first one
1167 push = create_push(env, node, sp, mem, ent);
1168 add_ia32_am_offs_int(push, 4);
1169 sp = create_spproj(env, push, 0, node);
1172 set_irn_n(node, i, new_Bad());
1176 for(i = arity - 1; i >= 0; --i) {
1177 entity *ent = be_get_MemPerm_out_entity(node, i);
1178 ir_type *enttype = get_entity_type(ent);
1179 int entbits = get_type_size_bits(enttype);
1183 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1185 pop = create_pop(env, node, sp, ent);
1187 // add another pop after the first one
1188 sp = create_spproj(env, pop, 1, node);
1189 pop = create_pop(env, node, sp, ent);
1190 add_ia32_am_offs_int(pop, 4);
1192 sp = create_spproj(env, pop, 1, node);
1197 // exchange memprojs
1198 foreach_out_edge_safe(node, edge, next) {
1199 ir_node *proj = get_edge_src_irn(edge);
1200 int p = get_Proj_proj(proj);
1204 set_Proj_pred(proj, pops[p]);
1205 set_Proj_proj(proj, 3);
1209 arity = get_irn_arity(node);
1210 for(i = 0; i < arity; ++i) {
1211 set_irn_n(node, i, new_Bad());
1217 * Fix the mode of Spill/Reload
1219 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
1221 if (mode_is_float(mode)) {
1233 * Block-Walker: Calls the transform functions Spill and Reload.
1235 static void ia32_after_ra_walker(ir_node *block, void *env) {
1236 ir_node *node, *prev;
1237 ia32_code_gen_t *cg = env;
1238 ia32_transform_env_t tenv;
1241 tenv.irg = current_ir_graph;
1243 DEBUG_ONLY(tenv.mod = cg->mod;)
1245 /* beware: the schedule is changed here */
1246 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1247 prev = sched_prev(node);
1248 if (be_is_Reload(node)) {
1249 /* we always reload the whole register */
1250 tenv.dbg = get_irn_dbg_info(node);
1252 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
1253 transform_to_Load(&tenv);
1255 else if (be_is_Spill(node)) {
1256 ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1257 /* we always spill the whole register */
1258 tenv.dbg = get_irn_dbg_info(node);
1260 tenv.mode = fix_spill_mode(cg, get_irn_mode(spillval));
1261 transform_to_Store(&tenv);
1263 else if(be_is_MemPerm(node)) {
1264 tenv.dbg = get_irn_dbg_info(node);
1266 transform_MemPerm(&tenv);
1272 * We transform Spill and Reload here. This needs to be done before
1273 * stack biasing otherwise we would miss the corrected offset for these nodes.
1275 * If x87 instruction should be emitted, run the x87 simulator and patch
1276 * the virtual instructions. This must obviously be done after register allocation.
1278 static void ia32_after_ra(void *self) {
1279 ia32_code_gen_t *cg = self;
1280 ir_graph *irg = cg->irg;
1282 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1284 ia32_finish_irg(irg, cg);
1288 * Last touchups for the graph before emit
1290 static void ia32_finish(void *self) {
1291 ia32_code_gen_t *cg = self;
1292 ir_graph *irg = cg->irg;
1294 //be_remove_empty_blocks(irg);
1295 cg->blk_sched = be_create_block_schedule(irg, cg->birg->execfreqs);
1297 //cg->blk_sched = sched_create_block_schedule(cg->irg, cg->birg->execfreqs);
1299 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1300 if (cg->used_fp == fp_x87 || cg->force_sim) {
1301 x87_simulate_graph(cg->arch_env, irg, cg->blk_sched);
1304 ia32_peephole_optimization(irg, cg);
1308 * Emits the code, closes the output file and frees
1309 * the code generator interface.
1311 static void ia32_codegen(void *self) {
1312 ia32_code_gen_t *cg = self;
1313 ir_graph *irg = cg->irg;
1315 ia32_gen_routine(cg->isa->out, irg, cg);
1319 /* remove it from the isa */
1322 /* de-allocate code generator */
1323 del_set(cg->reg_set);
1327 static void *ia32_cg_init(const be_irg_t *birg);
1329 static const arch_code_generator_if_t ia32_code_gen_if = {
1331 NULL, /* before abi introduce hook */
1333 ia32_before_sched, /* before scheduling hook */
1334 ia32_before_ra, /* before register allocation hook */
1335 ia32_after_ra, /* after register allocation hook */
1336 ia32_finish, /* called before codegen */
1337 ia32_codegen /* emit && done */
1341 * Initializes a IA32 code generator.
1343 static void *ia32_cg_init(const be_irg_t *birg) {
1344 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1345 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1347 cg->impl = &ia32_code_gen_if;
1348 cg->irg = birg->irg;
1349 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1350 cg->arch_env = birg->main_env->arch_env;
1353 cg->blk_sched = NULL;
1354 cg->fp_to_gp = NULL;
1355 cg->gp_to_fp = NULL;
1356 cg->fp_kind = isa->fp_kind;
1357 cg->used_fp = fp_none;
1358 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1360 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1362 /* copy optimizations from isa for easier access */
1364 cg->arch = isa->arch;
1365 cg->opt_arch = isa->opt_arch;
1371 if (isa->name_obst) {
1372 obstack_free(isa->name_obst, NULL);
1373 obstack_init(isa->name_obst);
1377 cur_reg_set = cg->reg_set;
1379 ia32_irn_ops.cg = cg;
1381 return (arch_code_generator_t *)cg;
1386 /*****************************************************************
1387 * ____ _ _ _____ _____
1388 * | _ \ | | | | |_ _|/ ____| /\
1389 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1390 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1391 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1392 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1394 *****************************************************************/
1397 * Set output modes for GCC
1399 static const tarval_mode_info mo_integer = {
1406 * set the tarval output mode of all integer modes to decimal
1408 static void set_tarval_output_modes(void)
1412 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1413 ir_mode *mode = get_irp_mode(i);
1415 if (mode_is_int(mode))
1416 set_tarval_mode_output_option(mode, &mo_integer);
1422 * The template that generates a new ISA object.
1423 * Note that this template can be changed by command line
1426 static ia32_isa_t ia32_isa_template = {
1428 &ia32_isa_if, /* isa interface implementation */
1429 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1430 &ia32_gp_regs[REG_EBP], /* base pointer register */
1431 -1, /* stack direction */
1432 NULL, /* main environment */
1434 NULL, /* 16bit register names */
1435 NULL, /* 8bit register names */
1439 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1440 IA32_OPT_DOAM | /* optimize address mode default: on */
1441 IA32_OPT_LEA | /* optimize for LEAs default: on */
1442 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1443 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1444 IA32_OPT_EXTBB | /* use extended basic block scheduling, default: on */
1445 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1446 arch_pentium_4, /* instruction architecture */
1447 arch_pentium_4, /* optimize for architecture */
1448 fp_sse2, /* use sse2 unit */
1449 NULL, /* current code generator */
1450 NULL, /* output file */
1452 NULL, /* name obstack */
1453 0 /* name obst size */
1458 * Initializes the backend ISA.
1460 static void *ia32_init(FILE *file_handle) {
1461 static int inited = 0;
1467 set_tarval_output_modes();
1469 isa = xmalloc(sizeof(*isa));
1470 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1472 ia32_register_init(isa);
1473 ia32_create_opcodes();
1475 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1476 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1477 /* no SSE2 for these cpu's */
1478 isa->fp_kind = fp_x87;
1480 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1481 /* Pentium 4 don't like inc and dec instructions */
1482 isa->opt &= ~IA32_OPT_INCDEC;
1485 isa->regs_16bit = pmap_create();
1486 isa->regs_8bit = pmap_create();
1487 isa->types = pmap_create();
1488 isa->tv_ent = pmap_create();
1489 isa->out = file_handle;
1490 isa->cpu = ia32_init_machine_description();
1492 ia32_build_16bit_reg_map(isa->regs_16bit);
1493 ia32_build_8bit_reg_map(isa->regs_8bit);
1495 /* patch register names of x87 registers */
1496 ia32_st_regs[0].name = "st";
1497 ia32_st_regs[1].name = "st(1)";
1498 ia32_st_regs[2].name = "st(2)";
1499 ia32_st_regs[3].name = "st(3)";
1500 ia32_st_regs[4].name = "st(4)";
1501 ia32_st_regs[5].name = "st(5)";
1502 ia32_st_regs[6].name = "st(6)";
1503 ia32_st_regs[7].name = "st(7)";
1506 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1507 obstack_init(isa->name_obst);
1510 ia32_handle_intrinsics();
1511 ia32_switch_section(isa->out, NO_SECTION);
1512 fprintf(isa->out, "\t.intel_syntax\n");
1514 /* needed for the debug support */
1515 ia32_switch_section(isa->out, SECTION_TEXT);
1516 fprintf(isa->out, ".Ltext0:\n");
1526 * Closes the output file and frees the ISA structure.
1528 static void ia32_done(void *self) {
1529 ia32_isa_t *isa = self;
1531 /* emit now all global declarations */
1532 ia32_gen_decls(isa->out, isa->arch_isa.main_env);
1534 pmap_destroy(isa->regs_16bit);
1535 pmap_destroy(isa->regs_8bit);
1536 pmap_destroy(isa->tv_ent);
1537 pmap_destroy(isa->types);
1540 obstack_free(isa->name_obst, NULL);
1548 * Return the number of register classes for this architecture.
1549 * We report always these:
1550 * - the general purpose registers
1551 * - the SSE floating point register set
1552 * - the virtual floating point registers
1554 static int ia32_get_n_reg_class(const void *self) {
1559 * Return the register class for index i.
1561 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1562 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1564 return &ia32_reg_classes[CLASS_ia32_gp];
1566 return &ia32_reg_classes[CLASS_ia32_xmm];
1568 return &ia32_reg_classes[CLASS_ia32_vfp];
1572 * Get the register class which shall be used to store a value of a given mode.
1573 * @param self The this pointer.
1574 * @param mode The mode in question.
1575 * @return A register class which can hold values of the given mode.
1577 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1578 const ia32_isa_t *isa = self;
1579 if (mode_is_float(mode)) {
1580 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1583 return &ia32_reg_classes[CLASS_ia32_gp];
1587 * Get the ABI restrictions for procedure calls.
1588 * @param self The this pointer.
1589 * @param method_type The type of the method (procedure) in question.
1590 * @param abi The abi object to be modified
1592 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1593 const ia32_isa_t *isa = self;
1596 unsigned cc = get_method_calling_convention(method_type);
1597 int n = get_method_n_params(method_type);
1600 int i, ignore_1, ignore_2;
1602 const arch_register_t *reg;
1603 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1605 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1607 /* set abi flags for calls */
1608 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1609 call_flags.bits.store_args_sequential = use_push;
1610 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1611 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1612 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1614 /* set stack parameter passing style */
1615 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1617 /* collect the mode for each type */
1618 modes = alloca(n * sizeof(modes[0]));
1620 for (i = 0; i < n; i++) {
1621 tp = get_method_param_type(method_type, i);
1622 modes[i] = get_type_mode(tp);
1625 /* set register parameters */
1626 if (cc & cc_reg_param) {
1627 /* determine the number of parameters passed via registers */
1628 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1630 /* loop over all parameters and set the register requirements */
1631 for (i = 0; i <= biggest_n; i++) {
1632 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1633 assert(reg && "kaputt");
1634 be_abi_call_param_reg(abi, i, reg);
1641 /* set stack parameters */
1642 for (i = stack_idx; i < n; i++) {
1643 /* parameters on the stack are 32 bit aligned */
1644 be_abi_call_param_stack(abi, i, 4, 0, 0);
1648 /* set return registers */
1649 n = get_method_n_ress(method_type);
1651 assert(n <= 2 && "more than two results not supported");
1653 /* In case of 64bit returns, we will have two 32bit values */
1655 tp = get_method_res_type(method_type, 0);
1656 mode = get_type_mode(tp);
1658 assert(!mode_is_float(mode) && "two FP results not supported");
1660 tp = get_method_res_type(method_type, 1);
1661 mode = get_type_mode(tp);
1663 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1665 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1666 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1669 const arch_register_t *reg;
1671 tp = get_method_res_type(method_type, 0);
1672 assert(is_atomic_type(tp));
1673 mode = get_type_mode(tp);
1675 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1677 be_abi_call_res_reg(abi, 0, reg);
1682 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1683 return &ia32_irn_ops;
1686 const arch_irn_handler_t ia32_irn_handler = {
1690 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1691 return &ia32_irn_handler;
1694 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1695 return is_ia32_irn(irn) ? 1 : -1;
1699 * Initializes the code generator interface.
1701 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1702 return &ia32_code_gen_if;
1706 * Returns the estimated execution time of an ia32 irn.
1708 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1709 const arch_env_t *arch_env = env;
1710 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1713 list_sched_selector_t ia32_sched_selector;
1716 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1718 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1719 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1720 ia32_sched_selector.exectime = ia32_sched_exectime;
1721 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1722 return &ia32_sched_selector;
1726 * Returns the necessary byte alignment for storing a register of given class.
1728 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1729 ir_mode *mode = arch_register_class_mode(cls);
1730 int bytes = get_mode_size_bytes(mode);
1732 if (mode_is_float(mode) && bytes > 8)
1737 static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
1738 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1739 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1740 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1743 static const be_execution_unit_t *_allowed_units_ALU[] = {
1744 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU1],
1745 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU2],
1746 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU3],
1747 &ia32_execution_units_ALU[IA32_EXECUNIT_TP_ALU_ALU4],
1750 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1751 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY1],
1752 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY2],
1753 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY3],
1754 &ia32_execution_units_DUMMY[IA32_EXECUNIT_TP_DUMMY_DUMMY4],
1757 static const be_execution_unit_t **_units_callret[] = {
1758 _allowed_units_BRANCH,
1761 static const be_execution_unit_t **_units_other[] = {
1765 static const be_execution_unit_t **_units_dummy[] = {
1766 _allowed_units_DUMMY,
1769 const be_execution_unit_t ***ret;
1771 if (is_ia32_irn(irn)) {
1772 ret = get_ia32_exec_units(irn);
1774 else if (is_be_node(irn)) {
1775 if (be_is_Call(irn) || be_is_Return(irn)) {
1776 ret = _units_callret;
1778 else if (be_is_Barrier(irn)) {
1793 * Return the abstract ia32 machine.
1795 static const be_machine_t *ia32_get_machine(const void *self) {
1796 const ia32_isa_t *isa = self;
1801 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1802 * @return 1 if allowed, 0 otherwise
1804 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1806 ir_node *cmp, *cmp_a, *phi;
1809 /* we don't want long long an floating point Psi */
1810 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
1812 if (get_irn_mode(sel) != mode_b)
1815 cmp = get_Proj_pred(sel);
1816 cmp_a = get_Cmp_left(cmp);
1817 mode = get_irn_mode(cmp_a);
1819 if (IS_BAD_PSI_MODE(mode))
1822 /* check the Phi nodes */
1823 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1824 ir_node *pred_i = get_irn_n(phi, i);
1825 ir_node *pred_j = get_irn_n(phi, j);
1826 ir_mode *mode_i = get_irn_mode(pred_i);
1827 ir_mode *mode_j = get_irn_mode(pred_j);
1829 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1833 #undef IS_BAD_PSI_MODE
1838 static ia32_intrinsic_env_t intrinsic_env = {
1839 NULL, /**< the irg, these entities belong to */
1840 NULL, /**< entity for first div operand (move into FPU) */
1841 NULL, /**< entity for second div operand (move into FPU) */
1842 NULL, /**< entity for converts ll -> d */
1843 NULL, /**< entity for converts d -> ll */
1847 * Returns the libFirm configuration parameter for this backend.
1849 static const backend_params *ia32_get_libfirm_params(void) {
1850 static const opt_if_conv_info_t ifconv = {
1851 4, /* maxdepth, doesn't matter for Psi-conversion */
1852 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
1854 static const arch_dep_params_t ad = {
1855 1, /* also use subs */
1856 4, /* maximum shifts */
1857 31, /* maximum shift amount */
1859 1, /* allow Mulhs */
1860 1, /* allow Mulus */
1861 32 /* Mulh allowed up to 32 bit */
1863 static backend_params p = {
1864 NULL, /* no additional opcodes */
1865 NULL, /* will be set later */
1866 1, /* need dword lowering */
1867 ia32_create_intrinsic_fkt,
1868 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1869 NULL, /* will be set later */
1873 p.if_conv_info = &ifconv;
1878 /* instruction set architectures. */
1879 static const lc_opt_enum_int_items_t arch_items[] = {
1880 { "386", arch_i386, },
1881 { "486", arch_i486, },
1882 { "pentium", arch_pentium, },
1883 { "586", arch_pentium, },
1884 { "pentiumpro", arch_pentium_pro, },
1885 { "686", arch_pentium_pro, },
1886 { "pentiummmx", arch_pentium_mmx, },
1887 { "pentium2", arch_pentium_2, },
1888 { "p2", arch_pentium_2, },
1889 { "pentium3", arch_pentium_3, },
1890 { "p3", arch_pentium_3, },
1891 { "pentium4", arch_pentium_4, },
1892 { "p4", arch_pentium_4, },
1893 { "pentiumm", arch_pentium_m, },
1894 { "pm", arch_pentium_m, },
1895 { "core", arch_core, },
1897 { "athlon", arch_athlon, },
1898 { "athlon64", arch_athlon_64, },
1899 { "opteron", arch_opteron, },
1903 static lc_opt_enum_int_var_t arch_var = {
1904 &ia32_isa_template.arch, arch_items
1907 static lc_opt_enum_int_var_t opt_arch_var = {
1908 &ia32_isa_template.opt_arch, arch_items
1911 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1913 { "sse2", fp_sse2 },
1917 static lc_opt_enum_int_var_t fp_unit_var = {
1918 &ia32_isa_template.fp_kind, fp_unit_items
1921 static const lc_opt_enum_int_items_t gas_items[] = {
1922 { "linux", ASM_LINUX_GAS },
1923 { "mingw", ASM_MINGW_GAS },
1927 static lc_opt_enum_int_var_t gas_var = {
1928 (int *)&asm_flavour, gas_items
1931 static const lc_opt_table_entry_t ia32_options[] = {
1932 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1933 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1934 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1935 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1936 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1937 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1938 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1939 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1940 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
1941 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1946 * Register command line options for the ia32 backend.
1950 * ia32-arch=arch create instruction for arch
1951 * ia32-opt=arch optimize for run on arch
1952 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1953 * ia32-incdec optimize for inc/dec
1954 * ia32-noaddrmode do not use address mode
1955 * ia32-nolea do not optimize for LEAs
1956 * ia32-noplacecnst do not place constants,
1957 * ia32-noimmop no operations with immediates
1958 * ia32-noextbb do not use extended basic block scheduling
1959 * ia32-nopushargs do not create pushs for function argument passing
1960 * ia32-gasmode set the GAS compatibility mode
1962 static void ia32_register_options(lc_opt_entry_t *ent)
1964 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1965 lc_opt_add_table(be_grp_ia32, ia32_options);
1967 #endif /* WITH_LIBCORE */
1969 const arch_isa_if_t ia32_isa_if = {
1972 ia32_get_n_reg_class,
1974 ia32_get_reg_class_for_mode,
1976 ia32_get_irn_handler,
1977 ia32_get_code_generator_if,
1978 ia32_get_list_sched_selector,
1979 ia32_get_reg_class_alignment,
1980 ia32_get_libfirm_params,
1981 ia32_get_allowed_execution_units,
1984 ia32_register_options