2 * This is the main ia32 firm backend driver.
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
41 #include "bearch_ia32_t.h"
43 #include "ia32_new_nodes.h" /* ia32 nodes interface */
44 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
45 #include "ia32_gen_decls.h" /* interface declaration emitter */
46 #include "ia32_transform.h"
47 #include "ia32_emitter.h"
48 #include "ia32_map_regs.h"
49 #include "ia32_optimize.h"
51 #include "ia32_dbg_stat.h"
53 #define DEBUG_MODULE "firm.be.ia32.isa"
56 static set *cur_reg_set = NULL;
59 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
61 /* Creates the unique per irg GP NoReg node. */
62 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
63 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
66 /* Creates the unique per irg FP NoReg node. */
67 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
68 return be_abi_get_callee_save_irn(cg->birg->abi,
69 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
72 /**************************************************
75 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
76 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
77 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
78 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
81 **************************************************/
83 static ir_node *my_skip_proj(const ir_node *n) {
91 * Return register requirements for an ia32 node.
92 * If the node returns a tuple (mode_T) then the proj's
93 * will be asked for this information.
95 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
96 const ia32_irn_ops_t *ops = self;
97 const ia32_register_req_t *irn_req;
98 long node_pos = pos == -1 ? 0 : pos;
99 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
100 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
102 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
103 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
107 if (mode == mode_T && pos < 0) {
108 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
112 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
116 node_pos = ia32_translate_proj_pos(irn);
122 irn = my_skip_proj(irn);
124 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
127 if (is_ia32_irn(irn)) {
129 irn_req = get_ia32_in_req(irn, pos);
132 irn_req = get_ia32_out_req(irn, node_pos);
135 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
137 memcpy(req, &(irn_req->req), sizeof(*req));
139 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
140 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
141 req->other_same = get_irn_n(irn, irn_req->same_pos);
144 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
145 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
146 req->other_different = get_irn_n(irn, irn_req->different_pos);
150 /* treat Unknowns like Const with default requirements */
151 if (is_Unknown(irn)) {
152 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
153 if (mode_is_float(mode)) {
154 if (USE_SSE2(ops->cg))
155 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
157 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
159 else if (mode_is_int(mode) || mode_is_reference(mode))
160 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
161 else if (mode == mode_T || mode == mode_M) {
162 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
166 assert(0 && "unsupported Unknown-Mode");
169 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
177 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
179 const ia32_irn_ops_t *ops = self;
181 if (get_irn_mode(irn) == mode_X) {
185 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
188 pos = ia32_translate_proj_pos(irn);
189 irn = my_skip_proj(irn);
192 if (is_ia32_irn(irn)) {
193 const arch_register_t **slots;
195 slots = get_ia32_slots(irn);
199 ia32_set_firm_reg(irn, reg, cur_reg_set);
203 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
205 const arch_register_t *reg = NULL;
209 if (get_irn_mode(irn) == mode_X) {
213 pos = ia32_translate_proj_pos(irn);
214 irn = my_skip_proj(irn);
217 if (is_ia32_irn(irn)) {
218 const arch_register_t **slots;
219 slots = get_ia32_slots(irn);
223 reg = ia32_get_firm_reg(irn, cur_reg_set);
229 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
230 irn = my_skip_proj(irn);
232 return arch_irn_class_branch;
233 else if (is_ia32_irn(irn))
234 return arch_irn_class_normal;
239 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
240 irn = my_skip_proj(irn);
241 if (is_ia32_irn(irn))
242 return get_ia32_flags(irn);
245 return arch_irn_flags_ignore;
250 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
251 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
254 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
256 const ia32_irn_ops_t *ops = self;
258 if (get_ia32_frame_ent(irn)) {
259 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
261 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
262 snprintf(buf, sizeof(buf), "%d", bias);
264 if (get_ia32_op_type(irn) == ia32_Normal) {
265 set_ia32_cnst(irn, buf);
268 add_ia32_am_offs(irn, buf);
270 set_ia32_am_flavour(irn, am_flav);
276 be_abi_call_flags_bits_t flags;
277 const arch_isa_t *isa;
278 const arch_env_t *aenv;
282 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
284 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
285 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
286 env->flags = fl.bits;
289 env->isa = aenv->isa;
293 static void ia32_abi_dont_save_regs(void *self, pset *s)
295 ia32_abi_env_t *env = self;
296 if(env->flags.try_omit_fp)
297 pset_insert_ptr(s, env->isa->bp);
301 * Generate the prologue.
302 * @param self The callback object.
303 * @param mem A pointer to the mem node. Update this if you define new memory.
304 * @param reg_map A mapping mapping all callee_save/ignore/parameter registers to their defining nodes.
305 * @return The register which shall be used as a stack frame base.
307 * All nodes which define registers in @p reg_map must keep @p reg_map current.
309 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
311 ia32_abi_env_t *env = self;
313 if (!env->flags.try_omit_fp) {
314 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
315 ir_node *bl = get_irg_start_block(env->irg);
316 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
317 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
321 push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem, mode_T);
322 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), 0);
323 *mem = new_r_Proj(env->irg, bl, push, mode_M, 1);
325 /* the push must have SP out register */
326 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
328 /* move esp to ebp */
329 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
330 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
331 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
332 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
334 /* beware: the copy must be done before any other sp use */
335 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
336 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
337 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
338 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
340 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
341 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
349 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
351 ia32_abi_env_t *env = self;
352 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
353 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
355 if (env->flags.try_omit_fp) {
356 /* simply remove the stack frame here */
357 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
361 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
362 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
364 /* copy ebp to esp */
365 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
368 pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem, mode_T);
369 set_ia32_flags(pop, arch_irn_flags_ignore);
370 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, 0);
371 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), 1);
372 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, 2);
373 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
374 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
377 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
378 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
382 * Produces the type which sits between the stack args and the locals on the stack.
383 * it will contain the return address and space to store the old base pointer.
384 * @return The Firm type modeling the ABI between type.
386 static ir_type *ia32_abi_get_between_type(void *self)
388 static ir_type *omit_fp_between_type = NULL;
389 static ir_type *between_type = NULL;
391 ia32_abi_env_t *env = self;
395 entity *ret_addr_ent;
396 entity *omit_fp_ret_addr_ent;
398 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
399 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
401 between_type = new_type_class(new_id_from_str("ia32_between_type"));
402 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
403 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
405 set_entity_offset_bytes(old_bp_ent, 0);
406 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
407 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
409 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
410 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
412 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
413 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
416 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
419 static const be_abi_callbacks_t ia32_abi_callbacks = {
422 ia32_abi_get_between_type,
423 ia32_abi_dont_save_regs,
428 /* fill register allocator interface */
430 static const arch_irn_ops_if_t ia32_irn_ops_if = {
431 ia32_get_irn_reg_req,
436 ia32_get_frame_entity,
440 ia32_irn_ops_t ia32_irn_ops = {
447 /**************************************************
450 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
451 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
452 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
453 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
456 **************************************************/
459 * Transforms the standard firm graph into
462 static void ia32_prepare_graph(void *self) {
463 ia32_code_gen_t *cg = self;
464 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
466 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
467 ia32_register_transformers();
468 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
469 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
471 if (cg->opt & IA32_OPT_DOAM) {
472 edges_deactivate(cg->irg);
473 //dead_node_elimination(cg->irg);
474 edges_activate(cg->irg);
476 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
478 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
479 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
482 DEBUG_ONLY(cg->mod = old_mod;)
487 * Insert copies for all ia32 nodes where the should_be_same requirement
489 * Transform Sub into Neg -- Add if IN2 == OUT
491 static void ia32_finish_node(ir_node *irn, void *env) {
492 ia32_code_gen_t *cg = env;
493 const ia32_register_req_t **reqs;
494 const arch_register_t *out_reg, *in_reg, *in2_reg;
496 ir_node *copy, *in_node, *block, *in2_node;
497 ia32_op_type_t op_tp;
499 if (is_ia32_irn(irn)) {
500 /* AM Dest nodes don't produce any values */
501 op_tp = get_ia32_op_type(irn);
502 if (op_tp == ia32_AddrModeD)
505 reqs = get_ia32_out_req_all(irn);
506 n_res = get_ia32_n_res(irn);
507 block = get_nodes_block(irn);
509 /* check all OUT requirements, if there is a should_be_same */
510 if (op_tp == ia32_Normal && ! is_ia32_Lea(irn) && ! is_ia32_Conv_I2I(irn) && ! is_ia32_Conv_I2I8Bit(irn)) {
511 for (i = 0; i < n_res; i++) {
512 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
513 /* get in and out register */
514 out_reg = get_ia32_out_reg(irn, i);
515 in_node = get_irn_n(irn, reqs[i]->same_pos);
516 in_reg = arch_get_irn_register(cg->arch_env, in_node);
518 /* don't copy ignore nodes */
519 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
522 /* check if in and out register are equal */
523 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
524 /* in case of a commutative op: just exchange the in's */
525 /* beware: the current op could be everything, so test for ia32 */
526 /* commutativity first before getting the second in */
527 if (is_ia32_commutative(irn)) {
528 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
529 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
531 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
532 set_irn_n(irn, reqs[i]->same_pos, in2_node);
533 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
540 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
541 /* create copy from in register */
542 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
544 DBG_OPT_2ADDRCPY(copy);
546 /* destination is the out register */
547 arch_set_irn_register(cg->arch_env, copy, out_reg);
549 /* insert copy before the node into the schedule */
550 sched_add_before(irn, copy);
553 set_irn_n(irn, reqs[i]->same_pos, copy);
560 /* If we have a CondJmp with immediate, we need to */
561 /* check if it's the right operand, otherwise we have */
562 /* to change it, as CMP doesn't support immediate as */
564 if (is_ia32_CondJmp(irn) && (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) && op_tp == ia32_AddrModeS) {
565 long pnc = get_negated_pnc(get_ia32_pncode(irn), get_ia32_res_mode(irn));
566 set_ia32_op_type(irn, ia32_AddrModeD);
567 set_ia32_pncode(irn, pnc);
570 /* check if there is a sub which need to be transformed */
571 ia32_transform_sub_to_neg_add(irn, cg);
573 /* transform a LEA into an Add if possible */
574 ia32_transform_lea_to_add(irn, cg);
578 /* check for peephole optimization */
579 ia32_peephole_optimization(irn, cg);
582 static void ia32_finish_irg_walker(ir_node *block, void *env) {
585 for (irn = sched_first(block); !sched_is_end(irn); irn = next) {
586 next = sched_next(irn);
587 ia32_finish_node(irn, env);
592 * Add Copy nodes for not fulfilled should_be_equal constraints
594 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
595 irg_block_walk_graph(irg, NULL, ia32_finish_irg_walker, cg);
601 * Dummy functions for hooks we don't need but which must be filled.
603 static void ia32_before_sched(void *self) {
607 * Called before the register allocator.
608 * Calculate a block schedule here. We need it for the x87
609 * simulator and the emitter.
611 static void ia32_before_ra(void *self) {
612 ia32_code_gen_t *cg = self;
614 cg->blk_sched = sched_create_block_schedule(cg->irg);
619 * Transforms a be node into a Load.
621 static void transform_to_Load(ia32_transform_env_t *env) {
622 ir_node *irn = env->irn;
623 entity *ent = be_get_frame_entity(irn);
624 ir_mode *mode = env->mode;
625 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
626 ir_node *nomem = new_rd_NoMem(env->irg);
627 ir_node *sched_point = NULL;
628 ir_node *ptr = get_irn_n(irn, 0);
629 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
630 ir_node *new_op, *proj;
631 const arch_register_t *reg;
633 if (sched_is_scheduled(irn)) {
634 sched_point = sched_prev(irn);
637 if (mode_is_float(mode)) {
638 if (USE_SSE2(env->cg))
639 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
641 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
644 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
647 set_ia32_am_support(new_op, ia32_am_Source);
648 set_ia32_op_type(new_op, ia32_AddrModeS);
649 set_ia32_am_flavour(new_op, ia32_B);
650 set_ia32_ls_mode(new_op, mode);
651 set_ia32_frame_ent(new_op, ent);
652 set_ia32_use_frame(new_op);
654 DBG_OPT_RELOAD2LD(irn, new_op);
656 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
659 sched_add_after(sched_point, new_op);
660 sched_add_after(new_op, proj);
665 /* copy the register from the old node to the new Load */
666 reg = arch_get_irn_register(env->cg->arch_env, irn);
667 arch_set_irn_register(env->cg->arch_env, new_op, reg);
669 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
675 * Transforms a be node into a Store.
677 static void transform_to_Store(ia32_transform_env_t *env) {
678 ir_node *irn = env->irn;
679 entity *ent = be_get_frame_entity(irn);
680 ir_mode *mode = env->mode;
681 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
682 ir_node *nomem = new_rd_NoMem(env->irg);
683 ir_node *ptr = get_irn_n(irn, 0);
684 ir_node *val = get_irn_n(irn, 1);
685 ir_node *new_op, *proj;
686 ir_node *sched_point = NULL;
688 if (sched_is_scheduled(irn)) {
689 sched_point = sched_prev(irn);
692 if (mode_is_float(mode)) {
693 if (USE_SSE2(env->cg))
694 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
696 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
698 else if (get_mode_size_bits(mode) == 8) {
699 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
702 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
705 set_ia32_am_support(new_op, ia32_am_Dest);
706 set_ia32_op_type(new_op, ia32_AddrModeD);
707 set_ia32_am_flavour(new_op, ia32_B);
708 set_ia32_ls_mode(new_op, mode);
709 set_ia32_frame_ent(new_op, ent);
710 set_ia32_use_frame(new_op);
712 DBG_OPT_SPILL2ST(irn, new_op);
714 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, 0);
717 sched_add_after(sched_point, new_op);
718 sched_add_after(new_op, proj);
723 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
729 * Fix the mode of Spill/Reload
731 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
733 if (mode_is_float(mode)) {
745 * Block-Walker: Calls the transform functions Spill and Reload.
747 static void ia32_after_ra_walker(ir_node *block, void *env) {
748 ir_node *node, *prev;
749 ia32_code_gen_t *cg = env;
750 ia32_transform_env_t tenv;
753 tenv.irg = current_ir_graph;
755 DEBUG_ONLY(tenv.mod = cg->mod;)
757 /* beware: the schedule is changed here */
758 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
759 prev = sched_prev(node);
760 if (be_is_Reload(node)) {
761 /* we always reload the whole register */
762 tenv.dbg = get_irn_dbg_info(node);
764 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
765 transform_to_Load(&tenv);
767 else if (be_is_Spill(node)) {
768 /* we always spill the whole register */
769 tenv.dbg = get_irn_dbg_info(node);
771 tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
772 transform_to_Store(&tenv);
778 * We transform Spill and Reload here. This needs to be done before
779 * stack biasing otherwise we would miss the corrected offset for these nodes.
781 * If x87 instruction should be emitted, run the x87 simulator and patch
782 * the virtual instructions. This must obviously be done after register allocation.
784 static void ia32_after_ra(void *self) {
785 ia32_code_gen_t *cg = self;
786 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
788 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
789 if (cg->used_fp == fp_x87) {
790 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
796 * Emits the code, closes the output file and frees
797 * the code generator interface.
799 static void ia32_codegen(void *self) {
800 ia32_code_gen_t *cg = self;
801 ir_graph *irg = cg->irg;
803 ia32_finish_irg(irg, cg);
804 be_dump(irg, "-finished", dump_ir_block_graph_sched);
805 ia32_gen_routine(cg->isa->out, irg, cg);
809 /* remove it from the isa */
812 /* de-allocate code generator */
813 del_set(cg->reg_set);
818 static void *ia32_cg_init(const be_irg_t *birg);
820 static const arch_code_generator_if_t ia32_code_gen_if = {
822 NULL, /* before abi introduce hook */
824 ia32_before_sched, /* before scheduling hook */
825 ia32_before_ra, /* before register allocation hook */
826 ia32_after_ra, /* after register allocation hook */
827 ia32_codegen /* emit && done */
831 * Initializes a IA32 code generator.
833 static void *ia32_cg_init(const be_irg_t *birg) {
834 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
835 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
837 cg->impl = &ia32_code_gen_if;
839 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
840 cg->arch_env = birg->main_env->arch_env;
843 cg->blk_sched = NULL;
846 cg->fp_kind = isa->fp_kind;
847 cg->used_fp = fp_none;
849 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
851 /* copy optimizations from isa for easier access */
858 if (isa->name_obst_size) {
859 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
860 isa->name_obst_size = 0;
861 obstack_free(isa->name_obst, NULL);
862 obstack_init(isa->name_obst);
866 cur_reg_set = cg->reg_set;
868 ia32_irn_ops.cg = cg;
870 return (arch_code_generator_t *)cg;
875 /*****************************************************************
876 * ____ _ _ _____ _____
877 * | _ \ | | | | |_ _|/ ____| /\
878 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
879 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
880 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
881 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
883 *****************************************************************/
886 * The template that generates a new ISA object.
887 * Note that this template can be changed by command line
890 static ia32_isa_t ia32_isa_template = {
892 &ia32_isa_if, /* isa interface implementation */
893 &ia32_gp_regs[REG_ESP], /* stack pointer register */
894 &ia32_gp_regs[REG_EBP], /* base pointer register */
895 -1, /* stack direction */
897 NULL, /* 16bit register names */
898 NULL, /* 8bit register names */
902 IA32_OPT_DOAM | /* optimize address mode default: on */
903 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
904 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
905 IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
906 arch_pentium_4, /* instruction architecture */
907 arch_pentium_4, /* optimize for architecture */
908 fp_sse2, /* use sse2 unit */
909 NULL, /* current code generator */
911 NULL, /* name obstack */
912 0 /* name obst size */
917 * Initializes the backend ISA.
919 static void *ia32_init(FILE *file_handle) {
920 static int inited = 0;
926 isa = xmalloc(sizeof(*isa));
927 memcpy(isa, &ia32_isa_template, sizeof(*isa));
929 ia32_register_init(isa);
930 ia32_create_opcodes();
931 ia32_register_copy_attr_func();
933 isa->regs_16bit = pmap_create();
934 isa->regs_8bit = pmap_create();
935 isa->types = pmap_create();
936 isa->tv_ent = pmap_create();
937 isa->out = file_handle;
939 ia32_build_16bit_reg_map(isa->regs_16bit);
940 ia32_build_8bit_reg_map(isa->regs_8bit);
942 /* patch register names of x87 registers */
944 ia32_st_regs[0].name = "st";
945 ia32_st_regs[1].name = "st(1)";
946 ia32_st_regs[2].name = "st(2)";
947 ia32_st_regs[3].name = "st(3)";
948 ia32_st_regs[4].name = "st(4)";
949 ia32_st_regs[5].name = "st(5)";
950 ia32_st_regs[6].name = "st(6)";
951 ia32_st_regs[7].name = "st(7)";
955 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
956 obstack_init(isa->name_obst);
957 isa->name_obst_size = 0;
960 fprintf(isa->out, "\t.intel_syntax\n");
970 * Closes the output file and frees the ISA structure.
972 static void ia32_done(void *self) {
973 ia32_isa_t *isa = self;
975 /* emit now all global declarations */
976 ia32_gen_decls(isa->out);
978 pmap_destroy(isa->regs_16bit);
979 pmap_destroy(isa->regs_8bit);
980 pmap_destroy(isa->tv_ent);
981 pmap_destroy(isa->types);
984 //printf("name obst size = %d bytes\n", isa->name_obst_size);
985 obstack_free(isa->name_obst, NULL);
993 * Return the number of register classes for this architecture.
994 * We report always these:
995 * - the general purpose registers
996 * - the floating point register set (depending on the unit used for FP)
997 * - MMX/SSE registers (currently not supported)
999 static int ia32_get_n_reg_class(const void *self) {
1004 * Return the register class for index i.
1006 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1007 const ia32_isa_t *isa = self;
1008 assert(i >= 0 && i < 2 && "Invalid ia32 register class requested.");
1010 return &ia32_reg_classes[CLASS_ia32_gp];
1011 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1015 * Get the register class which shall be used to store a value of a given mode.
1016 * @param self The this pointer.
1017 * @param mode The mode in question.
1018 * @return A register class which can hold values of the given mode.
1020 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1021 const ia32_isa_t *isa = self;
1022 if (mode_is_float(mode)) {
1023 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1026 return &ia32_reg_classes[CLASS_ia32_gp];
1030 * Get the ABI restrictions for procedure calls.
1031 * @param self The this pointer.
1032 * @param method_type The type of the method (procedure) in question.
1033 * @param abi The abi object to be modified
1035 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1036 const ia32_isa_t *isa = self;
1039 unsigned cc = get_method_calling_convention(method_type);
1040 int n = get_method_n_params(method_type);
1043 int i, ignore_1, ignore_2;
1045 const arch_register_t *reg;
1046 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1048 /* set abi flags for calls */
1049 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1050 call_flags.bits.store_args_sequential = 0; /* use stores instead of push */
1051 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1052 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1053 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1055 /* set stack parameter passing style */
1056 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1058 /* collect the mode for each type */
1059 modes = alloca(n * sizeof(modes[0]));
1061 for (i = 0; i < n; i++) {
1062 tp = get_method_param_type(method_type, i);
1063 modes[i] = get_type_mode(tp);
1066 /* set register parameters */
1067 if (cc & cc_reg_param) {
1068 /* determine the number of parameters passed via registers */
1069 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1071 /* loop over all parameters and set the register requirements */
1072 for (i = 0; i <= biggest_n; i++) {
1073 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1074 assert(reg && "kaputt");
1075 be_abi_call_param_reg(abi, i, reg);
1082 /* set stack parameters */
1083 for (i = stack_idx; i < n; i++) {
1084 be_abi_call_param_stack(abi, i, 1, 0, 0);
1088 /* set return registers */
1089 n = get_method_n_ress(method_type);
1091 assert(n <= 2 && "more than two results not supported");
1093 /* In case of 64bit returns, we will have two 32bit values */
1095 tp = get_method_res_type(method_type, 0);
1096 mode = get_type_mode(tp);
1098 assert(!mode_is_float(mode) && "two FP results not supported");
1100 tp = get_method_res_type(method_type, 1);
1101 mode = get_type_mode(tp);
1103 assert(!mode_is_float(mode) && "two FP results not supported");
1105 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1106 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1109 const arch_register_t *reg;
1111 tp = get_method_res_type(method_type, 0);
1112 assert(is_atomic_type(tp));
1113 mode = get_type_mode(tp);
1115 reg = mode_is_float(mode) ?
1116 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1117 &ia32_gp_regs[REG_EAX];
1119 be_abi_call_res_reg(abi, 0, reg);
1124 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1125 return &ia32_irn_ops;
1128 const arch_irn_handler_t ia32_irn_handler = {
1132 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1133 return &ia32_irn_handler;
1136 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1137 return is_ia32_irn(irn);
1141 * Initializes the code generator interface.
1143 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1144 return &ia32_code_gen_if;
1147 list_sched_selector_t ia32_sched_selector;
1150 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1152 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1153 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1154 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1155 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1156 return &ia32_sched_selector;
1160 * Returns the necessary byte alignment for storing a register of given class.
1162 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1163 ir_mode *mode = arch_register_class_mode(cls);
1164 int bytes = get_mode_size_bytes(mode);
1166 if (mode_is_float(mode) && bytes > 8)
1173 /* instruction set architectures. */
1174 static const lc_opt_enum_int_items_t arch_items[] = {
1175 { "386", arch_i386, },
1176 { "486", arch_i486, },
1177 { "pentium", arch_pentium, },
1178 { "586", arch_pentium, },
1179 { "pentiumpro", arch_pentium_pro, },
1180 { "686", arch_pentium_pro, },
1181 { "pentiummmx", arch_pentium_mmx, },
1182 { "pentium2", arch_pentium_2, },
1183 { "p2", arch_pentium_2, },
1184 { "pentium3", arch_pentium_3, },
1185 { "p3", arch_pentium_3, },
1186 { "pentium4", arch_pentium_4, },
1187 { "p4", arch_pentium_4, },
1188 { "pentiumm", arch_pentium_m, },
1189 { "pm", arch_pentium_m, },
1190 { "core", arch_core, },
1192 { "athlon", arch_athlon, },
1193 { "athlon64", arch_athlon_64, },
1194 { "opteron", arch_opteron, },
1198 static lc_opt_enum_int_var_t arch_var = {
1199 &ia32_isa_template.arch, arch_items
1202 static lc_opt_enum_int_var_t opt_arch_var = {
1203 &ia32_isa_template.opt_arch, arch_items
1206 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1208 { "sse2", fp_sse2 },
1212 static lc_opt_enum_int_var_t fp_unit_var = {
1213 &ia32_isa_template.fp_kind, fp_unit_items
1216 static const lc_opt_table_entry_t ia32_options[] = {
1217 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1218 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1219 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1220 LC_OPT_ENT_BIT("incdec", "optimize for inc/dec", &ia32_isa_template.opt, IA32_OPT_INCDEC),
1221 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1222 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1223 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1224 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1229 * Register command line options for the ia32 backend.
1233 * ia32-arch=arch create instruction for arch
1234 * ia32-opt=arch optimize for run on arch
1235 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1236 * ia32-incdec optimize for inc/dec
1237 * ia32-noaddrmode do not use address mode
1238 * ia32-noplacecnst do not place constants,
1239 * ia32-noimmop no operations with immediates
1240 * ia32-noextbb do not use extended basic block scheduling
1242 static void ia32_register_options(lc_opt_entry_t *ent)
1244 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1245 lc_opt_add_table(be_grp_ia32, ia32_options);
1247 #endif /* WITH_LIBCORE */
1249 const arch_isa_if_t ia32_isa_if = {
1252 ia32_get_n_reg_class,
1254 ia32_get_reg_class_for_mode,
1256 ia32_get_irn_handler,
1257 ia32_get_code_generator_if,
1258 ia32_get_list_sched_selector,
1259 ia32_get_reg_class_alignment,
1261 ia32_register_options