2 * This is the main ia32 firm backend driver.
17 #include "pseudo_irg.h"
21 #include "iredges_t.h"
29 #include "../beabi.h" /* the general register allocator interface */
30 #include "../benode_t.h"
31 #include "../belower.h"
32 #include "../besched_t.h"
34 #include "bearch_ia32_t.h"
36 #include "ia32_new_nodes.h" /* ia32 nodes interface */
37 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
38 #include "ia32_gen_decls.h" /* interface declaration emitter */
39 #include "ia32_transform.h"
40 #include "ia32_emitter.h"
41 #include "ia32_map_regs.h"
42 #include "ia32_optimize.h"
44 #define DEBUG_MODULE "firm.be.ia32.isa"
47 static set *cur_reg_set = NULL;
50 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
52 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
53 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
56 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
57 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
60 /**************************************************
63 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
64 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
65 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
66 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
69 **************************************************/
71 static ir_node *my_skip_proj(const ir_node *n) {
78 * Return register requirements for an ia32 node.
79 * If the node returns a tuple (mode_T) then the proj's
80 * will be asked for this information.
82 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
83 const ia32_register_req_t *irn_req;
84 long node_pos = pos == -1 ? 0 : pos;
85 ir_mode *mode = get_irn_mode(irn);
86 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
88 if (mode == mode_T || mode == mode_M) {
89 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
93 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
98 node_pos = ia32_translate_proj_pos(irn);
104 irn = my_skip_proj(irn);
106 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
109 if (is_ia32_irn(irn)) {
111 irn_req = get_ia32_in_req(irn, pos);
114 irn_req = get_ia32_out_req(irn, node_pos);
117 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
119 memcpy(req, &(irn_req->req), sizeof(*req));
121 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
122 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
123 req->other_same = get_irn_n(irn, irn_req->same_pos);
126 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
127 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
128 req->other_different = get_irn_n(irn, irn_req->different_pos);
132 /* treat Phi like Const with default requirements */
134 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
135 if (mode_is_float(mode))
136 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
137 else if (mode_is_int(mode) || mode_is_reference(mode))
138 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
139 else if (mode == mode_T || mode == mode_M) {
140 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
144 assert(0 && "unsupported Phi-Mode");
147 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
155 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
157 const ia32_irn_ops_t *ops = self;
159 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
162 pos = ia32_translate_proj_pos(irn);
163 irn = my_skip_proj(irn);
166 if (is_ia32_irn(irn)) {
167 const arch_register_t **slots;
169 slots = get_ia32_slots(irn);
173 ia32_set_firm_reg(irn, reg, cur_reg_set);
177 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
179 const arch_register_t *reg = NULL;
182 pos = ia32_translate_proj_pos(irn);
183 irn = my_skip_proj(irn);
186 if (is_ia32_irn(irn)) {
187 const arch_register_t **slots;
188 slots = get_ia32_slots(irn);
192 reg = ia32_get_firm_reg(irn, cur_reg_set);
198 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
199 irn = my_skip_proj(irn);
201 return arch_irn_class_branch;
202 else if (is_ia32_irn(irn))
203 return arch_irn_class_normal;
208 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
209 irn = my_skip_proj(irn);
210 if (is_ia32_irn(irn))
211 return get_ia32_flags(irn);
217 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
218 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
221 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
223 const ia32_irn_ops_t *ops = self;
225 if (is_ia32_use_frame(irn) && bias != 0) {
226 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
228 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
229 snprintf(buf, sizeof(buf), "%d", bias);
230 add_ia32_am_offs(irn, buf);
232 set_ia32_am_flavour(irn, am_flav);
237 be_abi_call_flags_bits_t flags;
238 const arch_isa_t *isa;
242 static void *ia32_abi_init(const be_abi_call_t *call, const arch_isa_t *isa, ir_graph *irg)
244 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
245 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
246 env->flags = fl.bits;
252 static void ia32_abi_dont_save_regs(void *self, pset *s)
254 ia32_abi_env_t *env = self;
255 if(env->flags.try_omit_fp)
256 pset_insert_ptr(s, env->isa->bp);
259 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
261 ia32_abi_env_t *env = self;
262 const arch_register_t *frame_reg = env->isa->sp;
264 if(!env->flags.try_omit_fp) {
265 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
266 ir_node *bl = get_irg_start_block(env->irg);
267 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
268 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
269 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
272 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_along);
273 store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
274 set_ia32_am_support(store_bp, ia32_am_Dest);
275 set_ia32_am_flavour(store_bp, ia32_B);
276 set_ia32_op_type(store_bp, ia32_AddrModeD);
277 *mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
278 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
279 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
280 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
282 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
283 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
289 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
291 ia32_abi_env_t *env = self;
292 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
293 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
294 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
296 if(env->flags.try_omit_fp) {
297 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_against);
302 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
304 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
305 load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
306 set_ia32_am_support(load_bp, ia32_am_Source);
307 set_ia32_am_flavour(load_bp, ia32_B);
308 set_ia32_op_type(load_bp, ia32_AddrModeS);
309 set_ia32_ls_mode(load_bp, mode_bp);
310 curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
311 *mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
314 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
315 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
319 * Produces the type which sits between the stack args and the locals on the stack.
320 * it will contain the return address and space to store the old base pointer.
321 * @return The Firm type modeling the ABI between type.
323 static ir_type *ia32_abi_get_between_type(void *self)
325 static ir_type *omit_fp_between_type = NULL;
326 static ir_type *between_type = NULL;
328 ia32_abi_env_t *env = self;
332 entity *ret_addr_ent;
333 entity *omit_fp_ret_addr_ent;
335 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
336 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
338 between_type = new_type_class(new_id_from_str("ia32_between_type"));
339 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
340 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
342 set_entity_offset_bytes(old_bp_ent, 0);
343 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
344 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
346 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
347 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
349 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
350 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
353 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
356 static const be_abi_callbacks_t ia32_abi_callbacks = {
359 ia32_abi_get_between_type,
360 ia32_abi_dont_save_regs,
365 /* fill register allocator interface */
367 static const arch_irn_ops_if_t ia32_irn_ops_if = {
368 ia32_get_irn_reg_req,
373 ia32_get_frame_entity,
377 ia32_irn_ops_t ia32_irn_ops = {
384 /**************************************************
387 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
388 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
389 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
390 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
393 **************************************************/
396 * Transforms the standard firm graph into
399 static void ia32_prepare_graph(void *self) {
400 ia32_code_gen_t *cg = self;
401 firm_dbg_module_t *old_mod = cg->mod;
403 cg->mod = firm_dbg_register("firm.be.ia32.transform");
404 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
405 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
407 edges_deactivate(cg->irg);
408 dead_node_elimination(cg->irg);
409 edges_activate(cg->irg);
414 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
415 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
421 * Insert copies for all ia32 nodes where the should_be_same requirement
423 * Transform Sub into Neg -- Add if IN2 == OUT
425 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
426 ia32_code_gen_t *cg = env;
427 const ia32_register_req_t **reqs;
428 const arch_register_t *out_reg, *in_reg;
430 ir_node *copy, *in_node, *block;
432 if (! is_ia32_irn(irn))
435 /* nodes with destination address mode don't produce values */
436 if (get_ia32_op_type(irn) == ia32_AddrModeD)
439 reqs = get_ia32_out_req_all(irn);
440 n_res = get_ia32_n_res(irn);
441 block = get_nodes_block(irn);
443 /* check all OUT requirements, if there is a should_be_same */
444 for (i = 0; i < n_res; i++) {
445 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
446 /* get in and out register */
447 out_reg = get_ia32_out_reg(irn, i);
448 in_node = get_irn_n(irn, reqs[i]->same_pos);
449 in_reg = arch_get_irn_register(cg->arch_env, in_node);
451 /* check if in and out register are equal */
452 if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
453 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
455 /* create copy from in register */
456 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
458 /* destination is the out register */
459 arch_set_irn_register(cg->arch_env, copy, out_reg);
461 /* insert copy before the node into the schedule */
462 sched_add_before(irn, copy);
465 set_irn_n(irn, reqs[i]->same_pos, copy);
470 /* check if there is a sub which need to be transformed */
471 ia32_transform_sub_to_neg_add(irn, cg);
475 * Add Copy nodes for not fulfilled should_be_equal constraints
477 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
478 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
484 * Dummy functions for hooks we don't need but which must be filled.
486 static void ia32_before_sched(void *self) {
489 static void ia32_before_ra(void *self) {
495 * Transforms a be node into a Load.
497 static void transform_to_Load(ia32_transform_env_t *env) {
498 ir_node *irn = env->irn;
499 entity *ent = be_get_frame_entity(irn);
500 ir_mode *mode = env->mode;
501 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
502 ir_node *nomem = new_rd_NoMem(env->irg);
503 ir_node *sched_point = NULL;
504 ir_node *ptr = get_irn_n(irn, 0);
505 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
506 ir_node *new_op, *proj;
507 const arch_register_t *reg;
509 if (sched_is_scheduled(irn)) {
510 sched_point = sched_prev(irn);
513 if (mode_is_float(mode)) {
514 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
517 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
520 set_ia32_am_support(new_op, ia32_am_Source);
521 set_ia32_op_type(new_op, ia32_AddrModeS);
522 set_ia32_am_flavour(new_op, ia32_B);
523 set_ia32_ls_mode(new_op, mode);
524 set_ia32_frame_ent(new_op, ent);
525 set_ia32_use_frame(new_op);
527 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
530 sched_add_after(sched_point, new_op);
531 sched_add_after(new_op, proj);
536 /* copy the register from the old node to the new Load */
537 reg = arch_get_irn_register(env->cg->arch_env, irn);
538 arch_set_irn_register(env->cg->arch_env, new_op, reg);
545 * Transforms a be node into a Store.
547 static void transform_to_Store(ia32_transform_env_t *env) {
548 ir_node *irn = env->irn;
549 entity *ent = be_get_frame_entity(irn);
550 ir_mode *mode = env->mode;
551 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
552 ir_node *nomem = new_rd_NoMem(env->irg);
553 ir_node *ptr = get_irn_n(irn, 0);
554 ir_node *val = get_irn_n(irn, 1);
555 ir_node *new_op, *proj;
556 ir_node *sched_point = NULL;
558 if (sched_is_scheduled(irn)) {
559 sched_point = sched_prev(irn);
562 if (mode_is_float(mode)) {
563 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
565 else if (get_mode_size_bits(mode) == 8) {
566 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
569 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
572 set_ia32_am_support(new_op, ia32_am_Dest);
573 set_ia32_op_type(new_op, ia32_AddrModeD);
574 set_ia32_am_flavour(new_op, ia32_B);
575 set_ia32_ls_mode(new_op, get_irn_mode(val));
576 set_ia32_frame_ent(new_op, ent);
577 set_ia32_use_frame(new_op);
579 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
582 sched_add_after(sched_point, new_op);
583 sched_add_after(new_op, proj);
593 * Calls the transform functions for StackParam, Spill and Reload.
595 static void ia32_after_ra_walker(ir_node *node, void *env) {
596 ia32_code_gen_t *cg = env;
597 ia32_transform_env_t tenv;
602 tenv.block = get_nodes_block(node);
603 tenv.dbg = get_irn_dbg_info(node);
604 tenv.irg = current_ir_graph;
607 tenv.mode = get_irn_mode(node);
610 /* be_is_StackParam(node) || */
611 if (be_is_Reload(node)) {
612 transform_to_Load(&tenv);
614 else if (be_is_Spill(node)) {
615 transform_to_Store(&tenv);
620 * We transform StackParam, Spill and Reload here. This needs to be done before
621 * stack biasing otherwise we would miss the corrected offset for these nodes.
623 static void ia32_after_ra(void *self) {
624 ia32_code_gen_t *cg = self;
625 irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
630 * Emits the code, closes the output file and frees
631 * the code generator interface.
633 static void ia32_codegen(void *self) {
634 ia32_code_gen_t *cg = self;
635 ir_graph *irg = cg->irg;
638 if (cg->emit_decls) {
639 ia32_gen_decls(cg->out);
643 ia32_finish_irg(irg, cg);
644 be_dump(irg, "-finished", dump_ir_block_graph_sched);
645 ia32_gen_routine(out, irg, cg);
649 pmap_destroy(cg->tv_ent);
650 pmap_destroy(cg->types);
652 /* de-allocate code generator */
653 del_set(cg->reg_set);
657 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
659 static const arch_code_generator_if_t ia32_code_gen_if = {
661 NULL, /* before abi introduce hook */
663 ia32_before_sched, /* before scheduling hook */
664 ia32_before_ra, /* before register allocation hook */
665 ia32_after_ra, /* after register allocation hook */
666 ia32_codegen /* emit && done */
670 * Initializes the code generator.
672 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
673 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
674 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
676 cg->impl = &ia32_code_gen_if;
678 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
679 cg->mod = firm_dbg_register("firm.be.ia32.cg");
681 cg->arch_env = birg->main_env->arch_env;
682 cg->types = pmap_create();
683 cg->tv_ent = pmap_create();
686 /* set optimizations */
689 cg->opt.placecnst = 1;
693 if (isa->name_obst_size) {
694 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
695 isa->name_obst_size = 0;
696 obstack_free(isa->name_obst, NULL);
697 obstack_init(isa->name_obst);
703 if (isa->num_codegens > 1)
708 cur_reg_set = cg->reg_set;
710 ia32_irn_ops.cg = cg;
712 return (arch_code_generator_t *)cg;
717 /*****************************************************************
718 * ____ _ _ _____ _____
719 * | _ \ | | | | |_ _|/ ____| /\
720 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
721 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
722 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
723 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
725 *****************************************************************/
727 static ia32_isa_t ia32_isa_template = {
728 &ia32_isa_if, /* isa interface implementation */
729 &ia32_gp_regs[REG_ESP], /* stack pointer register */
730 &ia32_gp_regs[REG_EBP], /* base pointer register */
731 -1, /* stack direction */
732 0, /* number of code generator objects so far */
733 NULL, /* 16bit register names */
734 NULL, /* 8bit register names */
736 NULL, /* name obstack */
737 0 /* name obst size */
742 * Initializes the backend ISA.
744 static void *ia32_init(void) {
745 static int inited = 0;
751 isa = xcalloc(1, sizeof(*isa));
752 memcpy(isa, &ia32_isa_template, sizeof(*isa));
754 ia32_register_init(isa);
755 ia32_create_opcodes();
757 isa->regs_16bit = pmap_create();
758 isa->regs_8bit = pmap_create();
760 ia32_build_16bit_reg_map(isa->regs_16bit);
761 ia32_build_8bit_reg_map(isa->regs_8bit);
764 isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
765 obstack_init(isa->name_obst);
766 isa->name_obst_size = 0;
777 * Closes the output file and frees the ISA structure.
779 static void ia32_done(void *self) {
780 ia32_isa_t *isa = self;
782 pmap_destroy(isa->regs_16bit);
783 pmap_destroy(isa->regs_8bit);
786 //printf("name obst size = %d bytes\n", isa->name_obst_size);
787 obstack_free(isa->name_obst, NULL);
795 static int ia32_get_n_reg_class(const void *self) {
799 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
800 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
801 return &ia32_reg_classes[i];
805 * Get the register class which shall be used to store a value of a given mode.
806 * @param self The this pointer.
807 * @param mode The mode in question.
808 * @return A register class which can hold values of the given mode.
810 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
811 if (mode_is_float(mode))
812 return &ia32_reg_classes[CLASS_ia32_fp];
814 return &ia32_reg_classes[CLASS_ia32_gp];
818 * Get the ABI restrictions for procedure calls.
819 * @param self The this pointer.
820 * @param method_type The type of the method (procedure) in question.
821 * @param abi The abi object to be modified
823 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
826 unsigned cc = get_method_calling_convention(method_type);
827 int n = get_method_n_params(method_type);
830 int i, ignore_1, ignore_2;
832 const arch_register_t *reg;
833 be_abi_call_flags_t call_flags;
835 /* set abi flags for calls */
836 call_flags.bits.left_to_right = 0;
837 call_flags.bits.store_args_sequential = 0;
838 call_flags.bits.try_omit_fp = 1;
839 call_flags.bits.fp_free = 0;
840 call_flags.bits.call_has_imm = 1;
842 /* set stack parameter passing style */
843 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
845 /* collect the mode for each type */
846 modes = alloca(n * sizeof(modes[0]));
848 for (i = 0; i < n; i++) {
849 tp = get_method_param_type(method_type, i);
850 modes[i] = get_type_mode(tp);
853 /* set register parameters */
854 if (cc & cc_reg_param) {
856 /* determine the number of parameters passed via registers */
857 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
859 /* loop over all parameters and set the register requirements */
860 for (i = 0; i <= biggest_n; i++) {
861 reg = ia32_get_RegParam_reg(n, modes, i, cc);
862 assert(reg && "kaputt");
863 be_abi_call_param_reg(abi, i, reg);
870 /* set stack parameters */
871 for (i = stack_idx; i < n; i++) {
872 be_abi_call_param_stack(abi, i);
876 /* set return registers */
877 n = get_method_n_ress(method_type);
879 assert(n <= 2 && "more than two results not supported");
881 /* In case of 64bit returns, we will have two 32bit values */
883 tp = get_method_res_type(method_type, 0);
884 mode = get_type_mode(tp);
886 assert(!mode_is_float(mode) && "two FP results not supported");
888 tp = get_method_res_type(method_type, 1);
889 mode = get_type_mode(tp);
891 assert(!mode_is_float(mode) && "two FP results not supported");
893 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
894 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
897 tp = get_method_res_type(method_type, 0);
898 assert(is_atomic_type(tp));
899 mode = get_type_mode(tp);
901 be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
906 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
907 return &ia32_irn_ops;
910 const arch_irn_handler_t ia32_irn_handler = {
914 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
915 return &ia32_irn_handler;
918 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
919 return is_ia32_irn(irn);
923 * Initializes the code generator interface.
925 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
926 return &ia32_code_gen_if;
929 list_sched_selector_t ia32_sched_selector;
932 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
934 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
935 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
936 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
937 return &ia32_sched_selector;
941 static void ia32_register_options(lc_opt_entry_t *ent)
944 #endif /* WITH_LIBCORE */
946 const arch_isa_if_t ia32_isa_if = {
948 ia32_register_options,
952 ia32_get_n_reg_class,
954 ia32_get_reg_class_for_mode,
956 ia32_get_irn_handler,
957 ia32_get_code_generator_if,
958 ia32_get_list_sched_selector