2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
31 #include "lc_opts_enum.h"
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
53 #include "iroptimize.h"
54 #include "instrument.h"
57 #include "../beirg_t.h"
58 #include "../benode_t.h"
59 #include "../belower.h"
60 #include "../besched_t.h"
63 #include "../beirgmod.h"
64 #include "../be_dbgout.h"
65 #include "../beblocksched.h"
66 #include "../bemachine.h"
67 #include "../beilpsched.h"
68 #include "../bespillslots.h"
69 #include "../bemodule.h"
70 #include "../begnuas.h"
71 #include "../bestate.h"
72 #include "../beflags.h"
74 #include "bearch_ia32_t.h"
76 #include "ia32_new_nodes.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "gen_ia32_machine.h"
79 #include "ia32_common_transform.h"
80 #include "ia32_transform.h"
81 #include "ia32_emitter.h"
82 #include "ia32_map_regs.h"
83 #include "ia32_optimize.h"
85 #include "ia32_dbg_stat.h"
86 #include "ia32_finish.h"
87 #include "ia32_util.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
95 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
98 static set *cur_reg_set = NULL;
100 ir_mode *mode_fpcw = NULL;
101 ia32_code_gen_t *ia32_current_cg = NULL;
104 * The environment for the intrinsic mapping.
106 static ia32_intrinsic_env_t intrinsic_env = {
108 NULL, /* the irg, these entities belong to */
109 NULL, /* entity for first div operand (move into FPU) */
110 NULL, /* entity for second div operand (move into FPU) */
111 NULL, /* entity for converts ll -> d */
112 NULL, /* entity for converts d -> ll */
113 NULL, /* entity for __divdi3 library call */
114 NULL, /* entity for __moddi3 library call */
115 NULL, /* entity for __udivdi3 library call */
116 NULL, /* entity for __umoddi3 library call */
117 NULL, /* bias value for conversion from float to unsigned 64 */
121 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
123 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
124 create_const_node_func func,
125 const arch_register_t* reg)
127 ir_node *block, *res;
132 block = get_irg_start_block(cg->irg);
133 res = func(NULL, cg->irg, block);
134 arch_set_irn_register(cg->arch_env, res, reg);
137 add_irn_dep(get_irg_end(cg->irg), res);
138 /* add_irn_dep(get_irg_start(cg->irg), res); */
143 /* Creates the unique per irg GP NoReg node. */
144 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
145 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
146 &ia32_gp_regs[REG_GP_NOREG]);
149 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
150 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
151 &ia32_vfp_regs[REG_VFP_NOREG]);
154 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
155 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
156 &ia32_xmm_regs[REG_XMM_NOREG]);
159 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
160 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
161 &ia32_gp_regs[REG_GP_UKNWN]);
164 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
165 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
166 &ia32_vfp_regs[REG_VFP_UKNWN]);
169 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
170 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
171 &ia32_xmm_regs[REG_XMM_UKNWN]);
174 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
175 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
176 &ia32_fp_cw_regs[REG_FPCW]);
181 * Returns the admissible noreg register node for input register pos of node irn.
183 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
184 const arch_register_req_t *req;
186 req = arch_get_register_req(cg->arch_env, irn, pos);
187 assert(req != NULL && "Missing register requirements");
188 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
189 return ia32_new_NoReg_gp(cg);
191 if (ia32_cg_config.use_sse2) {
192 return ia32_new_NoReg_xmm(cg);
194 return ia32_new_NoReg_vfp(cg);
198 /**************************************************
201 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
202 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
203 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
204 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
207 **************************************************/
210 * Return register requirements for an ia32 node.
211 * If the node returns a tuple (mode_T) then the proj's
212 * will be asked for this information.
214 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
217 ir_mode *mode = get_irn_mode(node);
220 if (mode == mode_X || is_Block(node)) {
221 return arch_no_register_req;
224 if (mode == mode_T && pos < 0) {
225 return arch_no_register_req;
228 node_pos = pos == -1 ? 0 : pos;
230 if (mode == mode_M || pos >= 0) {
231 return arch_no_register_req;
234 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
235 node = skip_Proj_const(node);
238 if (is_ia32_irn(node)) {
239 const arch_register_req_t *req;
241 req = get_ia32_in_req(node, pos);
243 req = get_ia32_out_req(node, node_pos);
250 /* unknowns should be transformed already */
251 assert(!is_Unknown(node));
252 return arch_no_register_req;
255 static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
259 if (get_irn_mode(irn) == mode_X) {
264 pos = get_Proj_proj(irn);
265 irn = skip_Proj(irn);
268 if (is_ia32_irn(irn)) {
269 const arch_register_t **slots;
271 slots = get_ia32_slots(irn);
274 ia32_set_firm_reg(irn, reg, cur_reg_set);
278 static const arch_register_t *ia32_get_irn_reg(const ir_node *irn)
281 const arch_register_t *reg = NULL;
285 if (get_irn_mode(irn) == mode_X) {
289 pos = get_Proj_proj(irn);
290 irn = skip_Proj_const(irn);
293 if (is_ia32_irn(irn)) {
294 const arch_register_t **slots;
295 slots = get_ia32_slots(irn);
296 assert(pos < get_ia32_n_res(irn));
299 reg = ia32_get_firm_reg(irn, cur_reg_set);
305 static arch_irn_class_t ia32_classify(const ir_node *irn) {
306 arch_irn_class_t classification = arch_irn_class_normal;
308 irn = skip_Proj_const(irn);
311 classification |= arch_irn_class_branch;
313 if (! is_ia32_irn(irn))
314 return classification & ~arch_irn_class_normal;
317 classification |= arch_irn_class_load;
320 classification |= arch_irn_class_store;
322 if (is_ia32_need_stackent(irn))
323 classification |= arch_irn_class_reload;
325 return classification;
328 static arch_irn_flags_t ia32_get_flags(const ir_node *irn) {
329 arch_irn_flags_t flags = arch_irn_flags_none;
332 return arch_irn_flags_ignore;
334 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
335 ir_node *pred = get_Proj_pred(irn);
337 if(is_ia32_irn(pred)) {
338 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
344 if (is_ia32_irn(irn)) {
345 flags |= get_ia32_flags(irn);
352 * The IA32 ABI callback object.
355 be_abi_call_flags_bits_t flags; /**< The call flags. */
356 const arch_env_t *aenv; /**< The architecture environment. */
357 ir_graph *irg; /**< The associated graph. */
360 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
361 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
364 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
365 set_ia32_frame_ent(irn, ent);
368 static void ia32_set_frame_offset(ir_node *irn, int bias)
370 if (get_ia32_frame_ent(irn) == NULL)
373 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
374 ia32_code_gen_t *cg = ia32_current_cg;
375 int omit_fp = be_abi_omit_fp(cg->birg->abi);
377 /* Pop nodes modify the stack pointer before calculating the
378 * destination address, so fix this here
383 add_ia32_am_offs_int(irn, bias);
386 static int ia32_get_sp_bias(const ir_node *node)
388 if (is_ia32_Push(node))
391 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
398 * Put all registers which are saved by the prologue/epilogue in a set.
400 * @param self The callback object.
401 * @param s The result set.
403 static void ia32_abi_dont_save_regs(void *self, pset *s)
405 ia32_abi_env_t *env = self;
406 if(env->flags.try_omit_fp)
407 pset_insert_ptr(s, env->aenv->bp);
411 * Generate the routine prologue.
413 * @param self The callback object.
414 * @param mem A pointer to the mem node. Update this if you define new memory.
415 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
417 * @return The register which shall be used as a stack frame base.
419 * All nodes which define registers in @p reg_map must keep @p reg_map current.
421 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
423 ia32_abi_env_t *env = self;
424 ia32_code_gen_t *cg = ia32_current_cg;
425 const arch_env_t *arch_env = env->aenv;
427 if (! env->flags.try_omit_fp) {
428 ir_graph *irg =env->irg;
429 ir_node *bl = get_irg_start_block(irg);
430 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
431 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
432 ir_node *noreg = ia32_new_NoReg_gp(cg);
435 /* ALL nodes representing bp must be set to ignore. */
436 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
439 push = new_rd_ia32_Push(NULL, irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
440 curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
441 *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
443 /* the push must have SP out register */
444 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
445 set_ia32_flags(push, arch_irn_flags_ignore);
447 /* move esp to ebp */
448 curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
449 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
450 arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
451 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
453 /* beware: the copy must be done before any other sp use */
454 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
455 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp);
456 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
457 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
459 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
460 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
469 * Generate the routine epilogue.
470 * @param self The callback object.
471 * @param bl The block for the epilog
472 * @param mem A pointer to the mem node. Update this if you define new memory.
473 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
474 * @return The register which shall be used as a stack frame base.
476 * All nodes which define registers in @p reg_map must keep @p reg_map current.
478 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
480 ia32_abi_env_t *env = self;
481 const arch_env_t *arch_env = env->aenv;
482 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
483 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
484 ir_graph *irg = env->irg;
486 if (env->flags.try_omit_fp) {
487 /* simply remove the stack frame here */
488 curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
489 add_irn_dep(curr_sp, *mem);
491 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
493 if (ia32_cg_config.use_leave) {
497 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
498 set_ia32_flags(leave, arch_irn_flags_ignore);
499 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
500 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
504 /* the old SP is not needed anymore (kill the proj) */
505 assert(is_Proj(curr_sp));
508 /* copy ebp to esp */
509 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
510 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
511 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
514 pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
515 set_ia32_flags(pop, arch_irn_flags_ignore);
516 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
517 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
519 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
521 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
522 arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
525 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
526 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
530 * Initialize the callback object.
531 * @param call The call object.
532 * @param aenv The architecture environment.
533 * @param irg The graph with the method.
534 * @return Some pointer. This pointer is passed to all other callback functions as self object.
536 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
538 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
539 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
540 env->flags = fl.bits;
547 * Destroy the callback object.
548 * @param self The callback object.
550 static void ia32_abi_done(void *self) {
555 * Produces the type which sits between the stack args and the locals on the stack.
556 * it will contain the return address and space to store the old base pointer.
557 * @return The Firm type modeling the ABI between type.
559 static ir_type *ia32_abi_get_between_type(void *self)
561 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
562 static ir_type *omit_fp_between_type = NULL;
563 static ir_type *between_type = NULL;
565 ia32_abi_env_t *env = self;
567 if (! between_type) {
568 ir_entity *old_bp_ent;
569 ir_entity *ret_addr_ent;
570 ir_entity *omit_fp_ret_addr_ent;
572 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
573 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
575 between_type = new_type_struct(IDENT("ia32_between_type"));
576 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
577 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
579 set_entity_offset(old_bp_ent, 0);
580 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
581 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
582 set_type_state(between_type, layout_fixed);
584 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
585 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
587 set_entity_offset(omit_fp_ret_addr_ent, 0);
588 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
589 set_type_state(omit_fp_between_type, layout_fixed);
592 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
597 * Get the estimated cycle count for @p irn.
599 * @param self The this pointer.
600 * @param irn The node.
602 * @return The estimated cycle count for this operation
604 static int ia32_get_op_estimated_cost(const ir_node *irn)
607 ia32_op_type_t op_tp;
611 if (!is_ia32_irn(irn))
614 assert(is_ia32_irn(irn));
616 cost = get_ia32_latency(irn);
617 op_tp = get_ia32_op_type(irn);
619 if (is_ia32_CopyB(irn)) {
622 else if (is_ia32_CopyB_i(irn)) {
623 int size = get_ia32_copyb_size(irn);
624 cost = 20 + (int)ceil((4/3) * size);
626 /* in case of address mode operations add additional cycles */
627 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
629 In case of stack access and access to fixed addresses add 5 cycles
630 (we assume they are in cache), other memory operations cost 20
633 if(is_ia32_use_frame(irn) ||
634 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
635 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
646 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
648 * @param irn The original operation
649 * @param i Index of the argument we want the inverse operation to yield
650 * @param inverse struct to be filled with the resulting inverse op
651 * @param obstack The obstack to use for allocation of the returned nodes array
652 * @return The inverse operation or NULL if operation invertible
654 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
658 ir_node *block, *noreg, *nomem;
661 /* we cannot invert non-ia32 irns */
662 if (! is_ia32_irn(irn))
665 /* operand must always be a real operand (not base, index or mem) */
666 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
669 /* we don't invert address mode operations */
670 if (get_ia32_op_type(irn) != ia32_Normal)
673 /* TODO: adjust for new immediates... */
674 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
678 irg = get_irn_irg(irn);
679 block = get_nodes_block(irn);
680 mode = get_irn_mode(irn);
681 irn_mode = get_irn_mode(irn);
682 noreg = get_irn_n(irn, 0);
683 nomem = new_r_NoMem(irg);
684 dbg = get_irn_dbg_info(irn);
686 /* initialize structure */
687 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
691 switch (get_ia32_irn_opcode(irn)) {
694 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
695 /* we have an add with a const here */
696 /* invers == add with negated const */
697 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
699 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
700 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
701 set_ia32_commutative(inverse->nodes[0]);
703 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
704 /* we have an add with a symconst here */
705 /* invers == sub with const */
706 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
708 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
711 /* normal add: inverse == sub */
712 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
719 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
720 /* we have a sub with a const/symconst here */
721 /* invers == add with this const */
722 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
723 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
724 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
728 if (i == n_ia32_binary_left) {
729 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
732 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
740 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
741 /* xor with const: inverse = xor */
742 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
743 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
744 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
748 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
754 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
759 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
764 /* inverse operation not supported */
771 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
773 if(mode_is_float(mode))
780 * Get the mode that should be used for spilling value node
782 static ir_mode *get_spill_mode(const ir_node *node)
784 ir_mode *mode = get_irn_mode(node);
785 return get_spill_mode_mode(mode);
789 * Checks whether an addressmode reload for a node with mode mode is compatible
790 * with a spillslot of mode spill_mode
792 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
794 if(mode_is_float(mode)) {
795 return mode == spillmode;
802 * Check if irn can load its operand at position i from memory (source addressmode).
803 * @param self Pointer to irn ops itself
804 * @param irn The irn to be checked
805 * @param i The operands position
806 * @return Non-Zero if operand can be loaded
808 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) {
809 ir_node *op = get_irn_n(irn, i);
810 const ir_mode *mode = get_irn_mode(op);
811 const ir_mode *spillmode = get_spill_mode(op);
814 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
815 ! is_ia32_irn(irn) || /* must be an ia32 irn */
816 get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
817 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
818 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
819 ! ia32_is_spillmode_compatible(mode, spillmode) ||
820 is_ia32_use_frame(irn)) /* must not already use frame */
823 if (i == n_ia32_binary_left) {
824 const arch_register_req_t *req;
825 if(!is_ia32_commutative(irn))
827 /* we can't swap left/right for limited registers
828 * (As this (currently) breaks constraint handling copies)
830 req = get_ia32_in_req(irn, n_ia32_binary_left);
831 if (req->type & arch_register_req_type_limited) {
839 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
842 ia32_code_gen_t *cg = ia32_current_cg;
844 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
846 if (i == n_ia32_binary_left) {
847 ia32_swap_left_right(irn);
850 set_ia32_op_type(irn, ia32_AddrModeS);
851 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
852 set_ia32_use_frame(irn);
853 set_ia32_need_stackent(irn);
855 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
856 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
857 set_irn_n(irn, n_ia32_mem, spill);
859 /* immediates are only allowed on the right side */
860 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
861 ia32_swap_left_right(irn);
865 static const be_abi_callbacks_t ia32_abi_callbacks = {
868 ia32_abi_get_between_type,
869 ia32_abi_dont_save_regs,
874 /* fill register allocator interface */
876 static const arch_irn_ops_t ia32_irn_ops = {
877 ia32_get_irn_reg_req,
882 ia32_get_frame_entity,
883 ia32_set_frame_entity,
884 ia32_set_frame_offset,
887 ia32_get_op_estimated_cost,
888 ia32_possible_memory_operand,
889 ia32_perform_memory_operand,
892 /**************************************************
895 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
896 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
897 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
898 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
901 **************************************************/
903 static ir_entity *mcount = NULL;
905 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
907 static void ia32_before_abi(void *self) {
908 lower_mode_b_config_t lower_mode_b_config = {
909 mode_Iu, /* lowered mode */
910 mode_Bu, /* prefered mode for set */
911 0, /* don't lower direct compares */
913 ia32_code_gen_t *cg = self;
915 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
917 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
919 if (mcount == NULL) {
920 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
921 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
922 /* FIXME: enter the right ld_ident here */
923 set_entity_ld_ident(mcount, get_entity_ident(mcount));
924 set_entity_visibility(mcount, visibility_external_allocated);
926 instrument_initcall(cg->irg, mcount);
930 typedef enum transformer_t {
937 static transformer_t be_transformer = TRANSFORMER_DEFAULT;
940 * Transforms the standard firm graph into
943 static void ia32_prepare_graph(void *self) {
944 ia32_code_gen_t *cg = self;
946 /* do local optimizations */
947 optimize_graph_df(cg->irg);
949 /* TODO: we often have dead code reachable through out-edges here. So for
950 * now we rebuild edges (as we need correct user count for code selection)
953 edges_deactivate(cg->irg);
954 edges_activate(cg->irg);
958 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
960 switch (be_transformer) {
961 case TRANSFORMER_DEFAULT:
962 /* transform remaining nodes into assembler instructions */
963 ia32_transform_graph(cg);
967 case TRANSFORMER_PBQP:
968 // disable CSE, because of two-step node-construction
971 /* transform nodes into assembler instructions by PBQP magic */
972 ia32_transform_graph_by_pbqp(cg);
975 be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched);
980 default: panic("Invalid transformer");
983 /* do local optimizations (mainly CSE) */
984 optimize_graph_df(cg->irg);
987 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
989 /* optimize address mode */
990 ia32_optimize_graph(cg);
993 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
995 /* do code placement, to optimize the position of constants */
999 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
1003 * Dummy functions for hooks we don't need but which must be filled.
1005 static void ia32_before_sched(void *self) {
1009 static void turn_back_am(ir_node *node)
1011 ir_graph *irg = current_ir_graph;
1012 dbg_info *dbgi = get_irn_dbg_info(node);
1013 ir_node *block = get_nodes_block(node);
1014 ir_node *base = get_irn_n(node, n_ia32_base);
1015 ir_node *index = get_irn_n(node, n_ia32_index);
1016 ir_node *mem = get_irn_n(node, n_ia32_mem);
1017 ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
1021 const ir_edge_t *edge;
1023 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1024 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1026 ia32_copy_am_attrs(load, node);
1027 set_irn_n(node, n_ia32_mem, new_NoMem());
1029 switch (get_ia32_am_arity(node)) {
1031 set_irn_n(node, n_ia32_unary_op, load_res);
1034 case ia32_am_binary:
1035 if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
1036 assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
1037 is_ia32_Test(node) || is_ia32_Test8Bit(node));
1038 set_irn_n(node, n_ia32_binary_left, load_res);
1040 set_irn_n(node, n_ia32_binary_right, load_res);
1044 case ia32_am_ternary:
1045 set_irn_n(node, n_ia32_binary_right, load_res);
1050 set_irn_n(node, n_ia32_base, noreg);
1051 set_irn_n(node, n_ia32_index, noreg);
1052 set_ia32_am_offs_int(node, 0);
1053 set_ia32_am_sc(node, NULL);
1054 set_ia32_am_scale(node, 0);
1055 clear_ia32_am_sc_sign(node);
1057 /* rewire mem-proj */
1058 if (get_irn_mode(node) == mode_T) {
1060 foreach_out_edge(node, edge) {
1061 ir_node *out = get_edge_src_irn(edge);
1062 if(get_irn_mode(out) == mode_M) {
1063 assert(mem_proj == NULL);
1068 if(mem_proj != NULL) {
1069 set_Proj_pred(mem_proj, load);
1070 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1074 set_ia32_op_type(node, ia32_Normal);
1075 if (sched_is_scheduled(node))
1076 sched_add_before(node, load);
1079 static ir_node *flags_remat(ir_node *node, ir_node *after)
1081 /* we should turn back source address mode when rematerializing nodes */
1082 ia32_op_type_t type;
1086 if (is_Block(after)) {
1089 block = get_nodes_block(after);
1092 type = get_ia32_op_type(node);
1094 case ia32_AddrModeS:
1098 case ia32_AddrModeD:
1099 /* TODO implement this later... */
1100 panic("found DestAM with flag user %+F this should not happen", node);
1103 default: assert(type == ia32_Normal); break;
1106 copy = exact_copy(node);
1107 set_nodes_block(copy, block);
1108 sched_add_after(after, copy);
1114 * Called before the register allocator.
1115 * Calculate a block schedule here. We need it for the x87
1116 * simulator and the emitter.
1118 static void ia32_before_ra(void *self) {
1119 ia32_code_gen_t *cg = self;
1121 /* setup fpu rounding modes */
1122 ia32_setup_fpu_mode(cg);
1125 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1128 ia32_add_missing_keeps(cg);
1133 * Transforms a be_Reload into a ia32 Load.
1135 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1136 ir_graph *irg = get_irn_irg(node);
1137 dbg_info *dbg = get_irn_dbg_info(node);
1138 ir_node *block = get_nodes_block(node);
1139 ir_entity *ent = be_get_frame_entity(node);
1140 ir_mode *mode = get_irn_mode(node);
1141 ir_mode *spillmode = get_spill_mode(node);
1142 ir_node *noreg = ia32_new_NoReg_gp(cg);
1143 ir_node *sched_point = NULL;
1144 ir_node *ptr = get_irg_frame(irg);
1145 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1146 ir_node *new_op, *proj;
1147 const arch_register_t *reg;
1149 if (sched_is_scheduled(node)) {
1150 sched_point = sched_prev(node);
1153 if (mode_is_float(spillmode)) {
1154 if (ia32_cg_config.use_sse2)
1155 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1157 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1159 else if (get_mode_size_bits(spillmode) == 128) {
1160 /* Reload 128 bit SSE registers */
1161 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1164 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1166 set_ia32_op_type(new_op, ia32_AddrModeS);
1167 set_ia32_ls_mode(new_op, spillmode);
1168 set_ia32_frame_ent(new_op, ent);
1169 set_ia32_use_frame(new_op);
1171 DBG_OPT_RELOAD2LD(node, new_op);
1173 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1176 sched_add_after(sched_point, new_op);
1180 /* copy the register from the old node to the new Load */
1181 reg = arch_get_irn_register(cg->arch_env, node);
1182 arch_set_irn_register(cg->arch_env, new_op, reg);
1184 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1186 exchange(node, proj);
1190 * Transforms a be_Spill node into a ia32 Store.
1192 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1193 ir_graph *irg = get_irn_irg(node);
1194 dbg_info *dbg = get_irn_dbg_info(node);
1195 ir_node *block = get_nodes_block(node);
1196 ir_entity *ent = be_get_frame_entity(node);
1197 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1198 ir_mode *mode = get_spill_mode(spillval);
1199 ir_node *noreg = ia32_new_NoReg_gp(cg);
1200 ir_node *nomem = new_rd_NoMem(irg);
1201 ir_node *ptr = get_irg_frame(irg);
1202 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1204 ir_node *sched_point = NULL;
1206 if (sched_is_scheduled(node)) {
1207 sched_point = sched_prev(node);
1210 /* No need to spill unknown values... */
1211 if(is_ia32_Unknown_GP(val) ||
1212 is_ia32_Unknown_VFP(val) ||
1213 is_ia32_Unknown_XMM(val)) {
1218 exchange(node, store);
1222 if (mode_is_float(mode)) {
1223 if (ia32_cg_config.use_sse2)
1224 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1226 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1227 } else if (get_mode_size_bits(mode) == 128) {
1228 /* Spill 128 bit SSE registers */
1229 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1230 } else if (get_mode_size_bits(mode) == 8) {
1231 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1233 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1236 set_ia32_op_type(store, ia32_AddrModeD);
1237 set_ia32_ls_mode(store, mode);
1238 set_ia32_frame_ent(store, ent);
1239 set_ia32_use_frame(store);
1240 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1241 DBG_OPT_SPILL2ST(node, store);
1244 sched_add_after(sched_point, store);
1248 exchange(node, store);
1251 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1252 ir_graph *irg = get_irn_irg(node);
1253 dbg_info *dbg = get_irn_dbg_info(node);
1254 ir_node *block = get_nodes_block(node);
1255 ir_node *noreg = ia32_new_NoReg_gp(cg);
1256 ir_node *frame = get_irg_frame(irg);
1258 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
1260 set_ia32_frame_ent(push, ent);
1261 set_ia32_use_frame(push);
1262 set_ia32_op_type(push, ia32_AddrModeS);
1263 set_ia32_ls_mode(push, mode_Is);
1265 sched_add_before(schedpoint, push);
1269 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1270 ir_graph *irg = get_irn_irg(node);
1271 dbg_info *dbg = get_irn_dbg_info(node);
1272 ir_node *block = get_nodes_block(node);
1273 ir_node *noreg = ia32_new_NoReg_gp(cg);
1274 ir_node *frame = get_irg_frame(irg);
1276 ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1278 set_ia32_frame_ent(pop, ent);
1279 set_ia32_use_frame(pop);
1280 set_ia32_op_type(pop, ia32_AddrModeD);
1281 set_ia32_ls_mode(pop, mode_Is);
1283 sched_add_before(schedpoint, pop);
1288 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1289 ir_graph *irg = get_irn_irg(node);
1290 dbg_info *dbg = get_irn_dbg_info(node);
1291 ir_node *block = get_nodes_block(node);
1292 ir_mode *spmode = mode_Iu;
1293 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1296 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1297 arch_set_irn_register(cg->arch_env, sp, spreg);
1303 * Transform MemPerm, currently we do this the ugly way and produce
1304 * push/pop into/from memory cascades. This is possible without using
1307 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1308 ir_graph *irg = get_irn_irg(node);
1309 ir_node *block = get_nodes_block(node);
1313 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1314 const ir_edge_t *edge;
1315 const ir_edge_t *next;
1318 arity = be_get_MemPerm_entity_arity(node);
1319 pops = alloca(arity * sizeof(pops[0]));
1322 for(i = 0; i < arity; ++i) {
1323 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1324 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1325 ir_type *enttype = get_entity_type(inent);
1326 unsigned entsize = get_type_size_bytes(enttype);
1327 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1328 ir_node *mem = get_irn_n(node, i + 1);
1331 /* work around cases where entities have different sizes */
1332 if(entsize2 < entsize)
1334 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1336 push = create_push(cg, node, node, sp, mem, inent);
1337 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1339 /* add another push after the first one */
1340 push = create_push(cg, node, node, sp, mem, inent);
1341 add_ia32_am_offs_int(push, 4);
1342 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1345 set_irn_n(node, i, new_Bad());
1349 for(i = arity - 1; i >= 0; --i) {
1350 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1351 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1352 ir_type *enttype = get_entity_type(outent);
1353 unsigned entsize = get_type_size_bytes(enttype);
1354 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1357 /* work around cases where entities have different sizes */
1358 if(entsize2 < entsize)
1360 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1362 pop = create_pop(cg, node, node, sp, outent);
1363 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1365 add_ia32_am_offs_int(pop, 4);
1367 /* add another pop after the first one */
1368 pop = create_pop(cg, node, node, sp, outent);
1369 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1376 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1377 sched_add_before(node, keep);
1379 /* exchange memprojs */
1380 foreach_out_edge_safe(node, edge, next) {
1381 ir_node *proj = get_edge_src_irn(edge);
1382 int p = get_Proj_proj(proj);
1386 set_Proj_pred(proj, pops[p]);
1387 set_Proj_proj(proj, pn_ia32_Pop_M);
1390 /* remove memperm */
1391 arity = get_irn_arity(node);
1392 for(i = 0; i < arity; ++i) {
1393 set_irn_n(node, i, new_Bad());
1399 * Block-Walker: Calls the transform functions Spill and Reload.
1401 static void ia32_after_ra_walker(ir_node *block, void *env) {
1402 ir_node *node, *prev;
1403 ia32_code_gen_t *cg = env;
1405 /* beware: the schedule is changed here */
1406 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1407 prev = sched_prev(node);
1409 if (be_is_Reload(node)) {
1410 transform_to_Load(cg, node);
1411 } else if (be_is_Spill(node)) {
1412 transform_to_Store(cg, node);
1413 } else if (be_is_MemPerm(node)) {
1414 transform_MemPerm(cg, node);
1420 * Collects nodes that need frame entities assigned.
1422 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1424 be_fec_env_t *env = data;
1426 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1427 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1428 int align = get_mode_size_bytes(mode);
1429 be_node_needs_frame_entity(env, node, mode, align);
1430 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1431 && is_ia32_use_frame(node)) {
1432 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1433 const ir_mode *mode = get_ia32_ls_mode(node);
1434 const ia32_attr_t *attr = get_ia32_attr_const(node);
1435 int align = get_mode_size_bytes(mode);
1437 if(attr->data.need_64bit_stackent) {
1440 if(attr->data.need_32bit_stackent) {
1443 be_node_needs_frame_entity(env, node, mode, align);
1444 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1445 || is_ia32_vfld(node)) {
1446 const ir_mode *mode = get_ia32_ls_mode(node);
1448 be_node_needs_frame_entity(env, node, mode, align);
1449 } else if(is_ia32_FldCW(node)) {
1450 /* although 2 byte would be enough 4 byte performs best */
1451 const ir_mode *mode = mode_Iu;
1453 be_node_needs_frame_entity(env, node, mode, align);
1456 assert(is_ia32_St(node) ||
1457 is_ia32_xStoreSimple(node) ||
1458 is_ia32_vfst(node) ||
1459 is_ia32_vfist(node) ||
1460 is_ia32_vfisttp(node) ||
1461 is_ia32_FnstCW(node));
1468 * We transform Spill and Reload here. This needs to be done before
1469 * stack biasing otherwise we would miss the corrected offset for these nodes.
1471 static void ia32_after_ra(void *self) {
1472 ia32_code_gen_t *cg = self;
1473 ir_graph *irg = cg->irg;
1474 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1476 /* create and coalesce frame entities */
1477 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1478 be_assign_entities(fec_env);
1479 be_free_frame_entity_coalescer(fec_env);
1481 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1485 * Last touchups for the graph before emit: x87 simulation to replace the
1486 * virtual with real x87 instructions, creating a block schedule and peephole
1489 static void ia32_finish(void *self) {
1490 ia32_code_gen_t *cg = self;
1491 ir_graph *irg = cg->irg;
1493 ia32_finish_irg(irg, cg);
1495 /* we might have to rewrite x87 virtual registers */
1496 if (cg->do_x87_sim) {
1497 x87_simulate_graph(cg->arch_env, cg->birg);
1500 /* do peephole optimisations */
1501 ia32_peephole_optimization(cg);
1503 /* create block schedule, this also removes empty blocks which might
1504 * produce critical edges */
1505 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1509 * Emits the code, closes the output file and frees
1510 * the code generator interface.
1512 static void ia32_codegen(void *self) {
1513 ia32_code_gen_t *cg = self;
1514 ir_graph *irg = cg->irg;
1516 ia32_gen_routine(cg, irg);
1520 /* remove it from the isa */
1523 assert(ia32_current_cg == cg);
1524 ia32_current_cg = NULL;
1526 /* de-allocate code generator */
1527 del_set(cg->reg_set);
1532 * Returns the node representing the PIC base.
1534 static ir_node *ia32_get_pic_base(void *self) {
1536 ia32_code_gen_t *cg = self;
1537 ir_node *get_eip = cg->get_eip;
1538 if (get_eip != NULL)
1541 block = get_irg_start_block(cg->irg);
1542 get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
1543 cg->get_eip = get_eip;
1545 add_irn_dep(get_eip, get_irg_frame(cg->irg));
1550 static void *ia32_cg_init(be_irg_t *birg);
1552 static const arch_code_generator_if_t ia32_code_gen_if = {
1554 ia32_get_pic_base, /* return node used as base in pic code addresses */
1555 ia32_before_abi, /* before abi introduce hook */
1558 ia32_before_sched, /* before scheduling hook */
1559 ia32_before_ra, /* before register allocation hook */
1560 ia32_after_ra, /* after register allocation hook */
1561 ia32_finish, /* called before codegen */
1562 ia32_codegen /* emit && done */
1566 * Initializes a IA32 code generator.
1568 static void *ia32_cg_init(be_irg_t *birg) {
1569 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1570 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1572 cg->impl = &ia32_code_gen_if;
1573 cg->irg = birg->irg;
1574 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1576 cg->arch_env = birg->main_env->arch_env;
1578 cg->blk_sched = NULL;
1579 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1580 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1583 /* Linux gprof implementation needs base pointer */
1584 birg->main_env->options->omit_fp = 0;
1591 if (isa->name_obst) {
1592 obstack_free(isa->name_obst, NULL);
1593 obstack_init(isa->name_obst);
1597 cur_reg_set = cg->reg_set;
1599 assert(ia32_current_cg == NULL);
1600 ia32_current_cg = cg;
1602 return (arch_code_generator_t *)cg;
1607 /*****************************************************************
1608 * ____ _ _ _____ _____
1609 * | _ \ | | | | |_ _|/ ____| /\
1610 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1611 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1612 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1613 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1615 *****************************************************************/
1618 * Set output modes for GCC
1620 static const tarval_mode_info mo_integer = {
1627 * set the tarval output mode of all integer modes to decimal
1629 static void set_tarval_output_modes(void)
1633 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1634 ir_mode *mode = get_irp_mode(i);
1636 if (mode_is_int(mode))
1637 set_tarval_mode_output_option(mode, &mo_integer);
1641 const arch_isa_if_t ia32_isa_if;
1644 * The template that generates a new ISA object.
1645 * Note that this template can be changed by command line
1648 static ia32_isa_t ia32_isa_template = {
1650 &ia32_isa_if, /* isa interface implementation */
1651 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1652 &ia32_gp_regs[REG_EBP], /* base pointer register */
1653 -1, /* stack direction */
1654 4, /* power of two stack alignment, 2^4 == 16 */
1655 NULL, /* main environment */
1656 7, /* costs for a spill instruction */
1657 5, /* costs for a reload instruction */
1659 NULL, /* 16bit register names */
1660 NULL, /* 8bit register names */
1661 NULL, /* 8bit register names high */
1664 NULL, /* current code generator */
1665 NULL, /* abstract machine */
1667 NULL, /* name obstack */
1671 static void init_asm_constraints(void)
1673 be_init_default_asm_constraint_flags();
1675 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1676 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1677 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1678 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1679 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1680 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1681 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1682 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1683 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1684 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1685 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1686 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1687 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1688 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1689 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1690 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1691 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1692 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1693 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1694 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1696 /* no support for autodecrement/autoincrement */
1697 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1698 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1699 /* no float consts */
1700 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1701 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1702 /* makes no sense on x86 */
1703 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1704 /* no support for sse consts yet */
1705 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1706 /* no support for x87 consts yet */
1707 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1708 /* no support for mmx registers yet */
1709 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1710 /* not available in 32bit mode */
1711 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1712 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1714 /* no code yet to determine register class needed... */
1715 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1719 * Initializes the backend ISA.
1721 static arch_env_t *ia32_init(FILE *file_handle) {
1722 static int inited = 0;
1730 set_tarval_output_modes();
1732 isa = xmalloc(sizeof(*isa));
1733 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1735 if(mode_fpcw == NULL) {
1736 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1739 ia32_register_init();
1740 ia32_create_opcodes(&ia32_irn_ops);
1742 be_emit_init(file_handle);
1743 isa->regs_16bit = pmap_create();
1744 isa->regs_8bit = pmap_create();
1745 isa->regs_8bit_high = pmap_create();
1746 isa->types = pmap_create();
1747 isa->tv_ent = pmap_create();
1748 isa->cpu = ia32_init_machine_description();
1750 ia32_build_16bit_reg_map(isa->regs_16bit);
1751 ia32_build_8bit_reg_map(isa->regs_8bit);
1752 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1755 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1756 obstack_init(isa->name_obst);
1759 /* enter the ISA object into the intrinsic environment */
1760 intrinsic_env.isa = isa;
1761 ia32_handle_intrinsics();
1763 /* emit asm includes */
1764 n = get_irp_n_asms();
1765 for (i = 0; i < n; ++i) {
1766 be_emit_cstring("#APP\n");
1767 be_emit_ident(get_irp_asm(i));
1768 be_emit_cstring("\n#NO_APP\n");
1771 /* needed for the debug support */
1772 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1773 be_emit_cstring(".Ltext0:\n");
1774 be_emit_write_line();
1776 /* we mark referenced global entities, so we can only emit those which
1777 * are actually referenced. (Note: you mustn't use the type visited flag
1778 * elsewhere in the backend)
1780 inc_master_type_visited();
1782 return &isa->arch_env;
1788 * Closes the output file and frees the ISA structure.
1790 static void ia32_done(void *self) {
1791 ia32_isa_t *isa = self;
1793 /* emit now all global declarations */
1794 be_gas_emit_decls(isa->arch_env.main_env, 1);
1796 pmap_destroy(isa->regs_16bit);
1797 pmap_destroy(isa->regs_8bit);
1798 pmap_destroy(isa->regs_8bit_high);
1799 pmap_destroy(isa->tv_ent);
1800 pmap_destroy(isa->types);
1803 obstack_free(isa->name_obst, NULL);
1813 * Return the number of register classes for this architecture.
1814 * We report always these:
1815 * - the general purpose registers
1816 * - the SSE floating point register set
1817 * - the virtual floating point registers
1818 * - the SSE vector register set
1820 static unsigned ia32_get_n_reg_class(const void *self) {
1826 * Return the register class for index i.
1828 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1832 assert(i < N_CLASSES);
1833 return &ia32_reg_classes[i];
1837 * Get the register class which shall be used to store a value of a given mode.
1838 * @param self The this pointer.
1839 * @param mode The mode in question.
1840 * @return A register class which can hold values of the given mode.
1842 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1843 const ir_mode *mode)
1847 if (mode_is_float(mode)) {
1848 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1851 return &ia32_reg_classes[CLASS_ia32_gp];
1855 * Get the ABI restrictions for procedure calls.
1856 * @param self The this pointer.
1857 * @param method_type The type of the method (procedure) in question.
1858 * @param abi The abi object to be modified
1860 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1867 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1870 /* set abi flags for calls */
1871 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1872 call_flags.bits.store_args_sequential = 0;
1873 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1874 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1875 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1877 /* set parameter passing style */
1878 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1880 if (get_method_variadicity(method_type) == variadicity_variadic) {
1881 /* pass all parameters of a variadic function on the stack */
1884 cc = get_method_calling_convention(method_type);
1885 if (get_method_additional_properties(method_type) & mtp_property_private
1886 && (ia32_cg_config.optimize_cc)) {
1887 /* set the calling conventions to register parameter */
1888 cc = (cc & ~cc_bits) | cc_reg_param;
1892 /* we have to pop the shadow parameter ourself for compound calls */
1893 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1894 && !(cc & cc_reg_param)) {
1895 be_abi_call_set_pop(abi, get_mode_size_bytes(mode_P_data));
1898 n = get_method_n_params(method_type);
1899 for (i = regnum = 0; i < n; i++) {
1901 const arch_register_t *reg = NULL;
1903 tp = get_method_param_type(method_type, i);
1904 mode = get_type_mode(tp);
1906 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1909 be_abi_call_param_reg(abi, i, reg);
1912 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1913 * movl has a shorter opcode than mov[sz][bw]l */
1914 ir_mode *load_mode = mode;
1915 if (mode != NULL && get_mode_size_bytes(mode) < 4) load_mode = mode_Iu;
1916 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1920 /* set return registers */
1921 n = get_method_n_ress(method_type);
1923 assert(n <= 2 && "more than two results not supported");
1925 /* In case of 64bit returns, we will have two 32bit values */
1927 tp = get_method_res_type(method_type, 0);
1928 mode = get_type_mode(tp);
1930 assert(!mode_is_float(mode) && "two FP results not supported");
1932 tp = get_method_res_type(method_type, 1);
1933 mode = get_type_mode(tp);
1935 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1937 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1938 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1941 const arch_register_t *reg;
1943 tp = get_method_res_type(method_type, 0);
1944 assert(is_atomic_type(tp));
1945 mode = get_type_mode(tp);
1947 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1949 be_abi_call_res_reg(abi, 0, reg);
1953 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1957 if(!is_ia32_irn(irn)) {
1961 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1962 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1963 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1964 || is_ia32_Immediate(irn))
1971 * Initializes the code generator interface.
1973 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1976 return &ia32_code_gen_if;
1980 * Returns the estimated execution time of an ia32 irn.
1982 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1984 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1987 list_sched_selector_t ia32_sched_selector;
1990 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1992 static const list_sched_selector_t *ia32_get_list_sched_selector(
1993 const void *self, list_sched_selector_t *selector)
1996 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1997 ia32_sched_selector.exectime = ia32_sched_exectime;
1998 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1999 return &ia32_sched_selector;
2002 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
2009 * Returns the necessary byte alignment for storing a register of given class.
2011 static int ia32_get_reg_class_alignment(const void *self,
2012 const arch_register_class_t *cls)
2014 ir_mode *mode = arch_register_class_mode(cls);
2015 int bytes = get_mode_size_bytes(mode);
2018 if (mode_is_float(mode) && bytes > 8)
2023 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
2024 const void *self, const ir_node *irn)
2026 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
2027 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
2028 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2031 static const be_execution_unit_t *_allowed_units_GP[] = {
2032 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2033 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2034 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2035 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2036 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2037 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2038 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2041 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2042 &be_machine_execution_units_DUMMY[0],
2045 static const be_execution_unit_t **_units_callret[] = {
2046 _allowed_units_BRANCH,
2049 static const be_execution_unit_t **_units_other[] = {
2053 static const be_execution_unit_t **_units_dummy[] = {
2054 _allowed_units_DUMMY,
2057 const be_execution_unit_t ***ret;
2060 if (is_ia32_irn(irn)) {
2061 ret = get_ia32_exec_units(irn);
2063 else if (is_be_node(irn)) {
2064 if (be_is_Call(irn) || be_is_Return(irn)) {
2065 ret = _units_callret;
2067 else if (be_is_Barrier(irn)) {
2082 * Return the abstract ia32 machine.
2084 static const be_machine_t *ia32_get_machine(const void *self) {
2085 const ia32_isa_t *isa = self;
2090 * Return irp irgs in the desired order.
2092 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2100 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2101 * @return 1 if allowed, 0 otherwise
2103 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2106 ir_node *cmp = NULL;
2108 /* we can't handle psis with 64bit compares yet */
2110 cmp = get_Proj_pred(sel);
2112 ir_node *left = get_Cmp_left(cmp);
2113 ir_mode *cmp_mode = get_irn_mode(left);
2114 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2121 if (ia32_cg_config.use_cmov) {
2122 if (ia32_cg_config.use_sse2 && cmp != NULL) {
2123 pn_Cmp pn = get_Proj_proj(sel);
2124 ir_node *cl = get_Cmp_left(cmp);
2125 ir_node *cr = get_Cmp_right(cmp);
2127 /* check the Phi nodes: no 64bit and no floating point cmov */
2128 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2129 ir_mode *mode = get_irn_mode(phi);
2131 if (mode_is_float(mode)) {
2132 /* check for Min, Max */
2133 ir_node *t = get_Phi_pred(phi, i);
2134 ir_node *f = get_Phi_pred(phi, j);
2137 /* SSE2 supports Min & Max */
2138 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2139 if (cl == t && cr == f) {
2140 /* Psi(a <=/>= b, a, b) => MIN, MAX */
2142 } else if (cl == f && cr == t) {
2143 /* Psi(a <=/>= b, b, a) => MAX, MIN */
2150 } else if (get_mode_size_bits(mode) > 32)
2154 /* check the Phi nodes: no 64bit and no floating point cmov */
2155 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2156 ir_mode *mode = get_irn_mode(phi);
2158 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2168 /* No cmov, only some special cases */
2172 /* Now some supported cases here */
2173 pn = get_Proj_proj(sel);
2174 cl = get_Cmp_left(cmp);
2175 cr = get_Cmp_right(cmp);
2177 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2178 ir_mode *mode = get_irn_mode(phi);
2182 t = get_Phi_pred(phi, i);
2183 f = get_Phi_pred(phi, j);
2185 /* no floating point and no 64bit yet */
2186 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2189 if (is_Const(t) && is_Const(f)) {
2190 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2191 /* always support Psi(x, C1, C2) */
2194 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2197 } else if (cl == t && cr == f) {
2198 /* Psi(a <=/>= b, a, b) => Min, Max */
2200 } else if (cl == f && cr == t) {
2201 /* Psi(a <=/>= b, b, a) => Max, Min */
2204 } else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2205 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2206 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2207 /* Psi(a >=u b, a - b, 0) unsigned Doz */
2209 } else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2210 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2211 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2212 /* Psi(a <=u b, 0, a - b) unsigned Doz */
2214 } else if (is_Const(cr) && is_Const_null(cr)) {
2215 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2216 /* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
2218 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2219 /* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
2227 /* all checks passed */
2233 static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
2238 /* we already added all our simple flags to the flags modifier list in
2239 * init, so this flag we don't know. */
2240 return ASM_CONSTRAINT_FLAG_INVALID;
2243 static int ia32_is_valid_clobber(const void *self, const char *clobber)
2247 return ia32_get_clobber_register(clobber) != NULL;
2251 * Returns the libFirm configuration parameter for this backend.
2253 static const backend_params *ia32_get_libfirm_params(void) {
2254 static const ir_settings_if_conv_t ifconv = {
2255 4, /* maxdepth, doesn't matter for Psi-conversion */
2256 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2258 static const ir_settings_arch_dep_t ad = {
2259 1, /* also use subs */
2260 4, /* maximum shifts */
2261 31, /* maximum shift amount */
2262 ia32_evaluate_insn, /* evaluate the instruction sequence */
2264 1, /* allow Mulhs */
2265 1, /* allow Mulus */
2266 32 /* Mulh allowed up to 32 bit */
2268 static backend_params p = {
2269 1, /* need dword lowering */
2270 1, /* support inline assembly */
2271 0, /* no immediate floating point mode. */
2272 NULL, /* no additional opcodes */
2273 NULL, /* will be set later */
2274 ia32_create_intrinsic_fkt,
2275 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2276 NULL, /* will be set below */
2277 NULL /* will be set below */
2280 ia32_setup_cg_config();
2282 /* doesn't really belong here, but this is the earliest place the backend
2284 init_asm_constraints();
2287 p.if_conv_info = &ifconv;
2291 static const lc_opt_enum_int_items_t gas_items[] = {
2292 { "elf", GAS_FLAVOUR_ELF },
2293 { "mingw", GAS_FLAVOUR_MINGW },
2294 { "yasm", GAS_FLAVOUR_YASM },
2295 { "macho", GAS_FLAVOUR_MACH_O },
2299 static lc_opt_enum_int_var_t gas_var = {
2300 (int*) &be_gas_flavour, gas_items
2303 static const lc_opt_enum_int_items_t transformer_items[] = {
2304 { "default", TRANSFORMER_DEFAULT },
2305 #ifdef FIRM_GRGEN_BE
2306 { "pbqp", TRANSFORMER_PBQP },
2311 static lc_opt_enum_int_var_t transformer_var = {
2312 (int*)&be_transformer, transformer_items
2315 static const lc_opt_table_entry_t ia32_options[] = {
2316 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2317 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2318 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2319 &ia32_isa_template.arch_env.stack_alignment),
2323 const arch_isa_if_t ia32_isa_if = {
2326 ia32_get_n_reg_class,
2328 ia32_get_reg_class_for_mode,
2330 ia32_get_code_generator_if,
2331 ia32_get_list_sched_selector,
2332 ia32_get_ilp_sched_selector,
2333 ia32_get_reg_class_alignment,
2334 ia32_get_libfirm_params,
2335 ia32_get_allowed_execution_units,
2338 ia32_parse_asm_constraint,
2339 ia32_is_valid_clobber
2342 void ia32_init_emitter(void);
2343 void ia32_init_finish(void);
2344 void ia32_init_optimize(void);
2345 void ia32_init_transform(void);
2346 void ia32_init_x87(void);
2348 void be_init_arch_ia32(void)
2350 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2351 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2353 lc_opt_add_table(ia32_grp, ia32_options);
2354 be_register_isa_if("ia32", &ia32_isa_if);
2356 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2358 ia32_init_emitter();
2360 ia32_init_optimize();
2361 ia32_init_transform();
2363 ia32_init_architecture();
2366 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);