2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
37 #include "../beabi.h" /* the general register allocator interface */
38 #include "../benode_t.h"
39 #include "../belower.h"
40 #include "../besched_t.h"
42 #include "bearch_ia32_t.h"
44 #include "ia32_new_nodes.h" /* ia32 nodes interface */
45 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
46 #include "ia32_gen_decls.h" /* interface declaration emitter */
47 #include "ia32_transform.h"
48 #include "ia32_emitter.h"
49 #include "ia32_map_regs.h"
50 #include "ia32_optimize.h"
52 #include "ia32_dbg_stat.h"
54 #define DEBUG_MODULE "firm.be.ia32.isa"
57 static set *cur_reg_set = NULL;
60 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
62 /* Creates the unique per irg GP NoReg node. */
63 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
64 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
67 /* Creates the unique per irg FP NoReg node. */
68 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
69 return be_abi_get_callee_save_irn(cg->birg->abi,
70 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
73 /**************************************************
76 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
77 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
78 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
79 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
82 **************************************************/
84 static ir_node *my_skip_proj(const ir_node *n) {
92 * Return register requirements for an ia32 node.
93 * If the node returns a tuple (mode_T) then the proj's
94 * will be asked for this information.
96 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
97 const ia32_irn_ops_t *ops = self;
98 const ia32_register_req_t *irn_req;
99 long node_pos = pos == -1 ? 0 : pos;
100 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
101 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
103 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
104 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
108 if (mode == mode_T && pos < 0) {
109 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
113 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
117 node_pos = ia32_translate_proj_pos(irn);
123 irn = my_skip_proj(irn);
125 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
128 if (is_ia32_irn(irn)) {
130 irn_req = get_ia32_in_req(irn, pos);
133 irn_req = get_ia32_out_req(irn, node_pos);
136 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
138 memcpy(req, &(irn_req->req), sizeof(*req));
140 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
141 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
142 req->other_same = get_irn_n(irn, irn_req->same_pos);
145 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
146 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
147 req->other_different = get_irn_n(irn, irn_req->different_pos);
151 /* treat Unknowns like Const with default requirements */
152 if (is_Unknown(irn)) {
153 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
154 if (mode_is_float(mode)) {
155 if (USE_SSE2(ops->cg))
156 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
158 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
160 else if (mode_is_int(mode) || mode_is_reference(mode))
161 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
162 else if (mode == mode_T || mode == mode_M) {
163 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
167 assert(0 && "unsupported Unknown-Mode");
170 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
178 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
180 const ia32_irn_ops_t *ops = self;
182 if (get_irn_mode(irn) == mode_X) {
186 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
189 pos = ia32_translate_proj_pos(irn);
190 irn = my_skip_proj(irn);
193 if (is_ia32_irn(irn)) {
194 const arch_register_t **slots;
196 slots = get_ia32_slots(irn);
200 ia32_set_firm_reg(irn, reg, cur_reg_set);
204 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
206 const arch_register_t *reg = NULL;
210 if (get_irn_mode(irn) == mode_X) {
214 pos = ia32_translate_proj_pos(irn);
215 irn = my_skip_proj(irn);
218 if (is_ia32_irn(irn)) {
219 const arch_register_t **slots;
220 slots = get_ia32_slots(irn);
224 reg = ia32_get_firm_reg(irn, cur_reg_set);
230 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
231 irn = my_skip_proj(irn);
233 return arch_irn_class_branch;
234 else if (is_ia32_Cnst(irn))
235 return arch_irn_class_const;
236 else if (is_ia32_Ld(irn))
237 return arch_irn_class_load;
238 else if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
239 return arch_irn_class_store;
240 else if (is_ia32_irn(irn))
241 return arch_irn_class_normal;
246 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
247 irn = my_skip_proj(irn);
248 if (is_ia32_irn(irn))
249 return get_ia32_flags(irn);
252 return arch_irn_flags_ignore;
257 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
258 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
261 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
263 const ia32_irn_ops_t *ops = self;
265 if (get_ia32_frame_ent(irn)) {
266 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
268 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
269 snprintf(buf, sizeof(buf), "%d", bias);
271 if (get_ia32_op_type(irn) == ia32_Normal) {
272 set_ia32_cnst(irn, buf);
275 add_ia32_am_offs(irn, buf);
277 set_ia32_am_flavour(irn, am_flav);
283 be_abi_call_flags_bits_t flags;
284 const arch_isa_t *isa;
285 const arch_env_t *aenv;
289 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
291 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
292 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
293 env->flags = fl.bits;
296 env->isa = aenv->isa;
301 * Put all registers which are saved by the prologue/epilogue in a set.
303 * @param self The callback object.
304 * @param s The result set.
306 static void ia32_abi_dont_save_regs(void *self, pset *s)
308 ia32_abi_env_t *env = self;
309 if(env->flags.try_omit_fp)
310 pset_insert_ptr(s, env->isa->bp);
314 * Generate the routine prologue.
316 * @param self The callback object.
317 * @param mem A pointer to the mem node. Update this if you define new memory.
318 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
320 * @return The register which shall be used as a stack frame base.
322 * All nodes which define registers in @p reg_map must keep @p reg_map current.
324 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
326 ia32_abi_env_t *env = self;
328 if (!env->flags.try_omit_fp) {
329 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
330 ir_node *bl = get_irg_start_block(env->irg);
331 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
332 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
336 push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
337 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
338 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
340 /* the push must have SP out register */
341 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
342 set_ia32_flags(push, arch_irn_flags_ignore);
344 /* move esp to ebp */
345 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
346 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
347 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
348 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
350 /* beware: the copy must be done before any other sp use */
351 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
352 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
353 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
354 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
356 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
357 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
366 * Generate the routine epilogue.
367 * @param self The callback object.
368 * @param bl The block for the epilog
369 * @param mem A pointer to the mem node. Update this if you define new memory.
370 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
371 * @return The register which shall be used as a stack frame base.
373 * All nodes which define registers in @p reg_map must keep @p reg_map current.
375 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
377 ia32_abi_env_t *env = self;
378 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
379 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
381 if (env->flags.try_omit_fp) {
382 /* simply remove the stack frame here */
383 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
386 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
387 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
388 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
390 /* gcc always emits a leave at the end of a routine */
391 if (1 || ARCH_AMD(isa->opt_arch)) {
395 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
396 set_ia32_flags(leave, arch_irn_flags_ignore);
397 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
398 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
399 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
404 /* copy ebp to esp */
405 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
408 pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
409 set_ia32_flags(pop, arch_irn_flags_ignore);
410 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
411 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
412 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
414 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
415 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
418 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
419 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
423 * Produces the type which sits between the stack args and the locals on the stack.
424 * it will contain the return address and space to store the old base pointer.
425 * @return The Firm type modeling the ABI between type.
427 static ir_type *ia32_abi_get_between_type(void *self)
429 static ir_type *omit_fp_between_type = NULL;
430 static ir_type *between_type = NULL;
432 ia32_abi_env_t *env = self;
436 entity *ret_addr_ent;
437 entity *omit_fp_ret_addr_ent;
439 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
440 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
442 between_type = new_type_class(new_id_from_str("ia32_between_type"));
443 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
444 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
446 set_entity_offset_bytes(old_bp_ent, 0);
447 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
448 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
450 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
451 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
453 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
454 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
457 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
461 * Get the estimated cycle count for @p irn.
463 * @param self The this pointer.
464 * @param irn The node.
466 * @return The estimated cycle count for this operation
468 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
471 switch (get_ia32_irn_opcode(irn)) {
473 case iro_ia32_DivMod:
478 case iro_ia32_l_Load:
485 case iro_ia32_xStore:
486 case iro_ia32_l_Store:
488 case iro_ia32_Store8Bit:
496 case iro_ia32_l_MulS:
509 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
511 * @param irn The original operation
512 * @param i Index of the argument we want the inverse operation to yield
513 * @param inverse struct to be filled with the resulting inverse op
514 * @param obstack The obstack to use for allocation of the returned nodes array
515 * @return The inverse operation or NULL if operation invertible
517 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
520 ir_node *block, *noreg, *nomem;
523 /* we cannot invert non-ia32 irns */
524 if (! is_ia32_irn(irn))
527 /* operand must always be a real operand (not base, index or mem) */
528 if (i != 2 && i != 3)
531 /* we don't invert address mode operations */
532 if (get_ia32_op_type(irn) != ia32_Normal)
535 irg = get_irn_irg(irn);
536 block = get_nodes_block(irn);
537 mode = get_ia32_res_mode(irn);
538 noreg = get_irn_n(irn, 0);
539 nomem = new_r_NoMem(irg);
541 /* initialize structure */
542 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
546 switch (get_ia32_irn_opcode(irn)) {
548 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
549 /* we have an add with a const here */
550 /* invers == add with negated const */
551 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
552 pnc = pn_ia32_Add_res;
554 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
555 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
556 set_ia32_commutative(inverse->nodes[0]);
558 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
559 /* we have an add with a symconst here */
560 /* invers == sub with const */
561 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
562 pnc = pn_ia32_Sub_res;
564 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
567 /* normal add: inverse == sub */
568 ir_node *proj = get_irn_out_edge_first(irn)->src;
569 assert(proj && is_Proj(proj));
571 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
572 pnc = pn_ia32_Sub_res;
577 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
578 /* we have a sub with a const/symconst here */
579 /* invers == add with this const */
580 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
581 pnc = pn_ia32_Add_res;
582 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
583 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
587 ir_node *proj = get_irn_out_edge_first(irn)->src;
588 assert(proj && is_Proj(proj));
591 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
594 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
596 pnc = pn_ia32_Sub_res;
601 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
602 /* xor with const: inverse = xor */
603 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
604 pnc = pn_ia32_Eor_res;
605 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
606 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
610 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
611 pnc = pn_ia32_Eor_res;
616 inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), nomem);
617 pnc = pn_ia32_Not_res;
621 inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), nomem);
622 pnc = pn_ia32_Minus_res;
626 /* inverse operation not supported */
630 set_ia32_res_mode(inverse->nodes[0], mode);
631 inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
636 static const be_abi_callbacks_t ia32_abi_callbacks = {
639 ia32_abi_get_between_type,
640 ia32_abi_dont_save_regs,
645 /* fill register allocator interface */
647 static const arch_irn_ops_if_t ia32_irn_ops_if = {
648 ia32_get_irn_reg_req,
653 ia32_get_frame_entity,
656 ia32_get_op_estimated_cost
659 ia32_irn_ops_t ia32_irn_ops = {
666 /**************************************************
669 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
670 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
671 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
672 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
675 **************************************************/
678 * Transforms the standard firm graph into
681 static void ia32_prepare_graph(void *self) {
682 ia32_code_gen_t *cg = self;
683 dom_front_info_t *dom;
684 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
686 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
688 /* 1st: transform constants and psi condition trees */
689 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_psi_cond_tree, cg);
691 /* 2nd: transform all remaining nodes */
692 ia32_register_transformers();
693 dom = be_compute_dominance_frontiers(cg->irg);
694 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
695 be_free_dominance_frontiers(dom);
696 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
698 /* 3rd: optimize address mode */
699 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
700 ia32_optimize_addressmode(cg);
701 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
702 DEBUG_ONLY(cg->mod = old_mod;)
705 static INLINE int need_constraint_copy(ir_node *irn) {
707 ! is_ia32_Lea(irn) && \
708 ! is_ia32_Conv_I2I(irn) && \
709 ! is_ia32_Conv_I2I8Bit(irn) && \
710 ! is_ia32_CmpCMov(irn) && \
711 ! is_ia32_CmpSet(irn);
715 * Insert copies for all ia32 nodes where the should_be_same requirement
717 * Transform Sub into Neg -- Add if IN2 == OUT
719 static void ia32_finish_node(ir_node *irn, void *env) {
720 ia32_code_gen_t *cg = env;
721 const ia32_register_req_t **reqs;
722 const arch_register_t *out_reg, *in_reg, *in2_reg;
724 ir_node *copy, *in_node, *block, *in2_node;
725 ia32_op_type_t op_tp;
727 if (is_ia32_irn(irn)) {
728 /* AM Dest nodes don't produce any values */
729 op_tp = get_ia32_op_type(irn);
730 if (op_tp == ia32_AddrModeD)
733 reqs = get_ia32_out_req_all(irn);
734 n_res = get_ia32_n_res(irn);
735 block = get_nodes_block(irn);
737 /* check all OUT requirements, if there is a should_be_same */
738 if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
740 for (i = 0; i < n_res; i++) {
741 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
742 /* get in and out register */
743 out_reg = get_ia32_out_reg(irn, i);
744 in_node = get_irn_n(irn, reqs[i]->same_pos);
745 in_reg = arch_get_irn_register(cg->arch_env, in_node);
747 /* don't copy ignore nodes */
748 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
751 /* check if in and out register are equal */
752 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
753 /* in case of a commutative op: just exchange the in's */
754 /* beware: the current op could be everything, so test for ia32 */
755 /* commutativity first before getting the second in */
756 if (is_ia32_commutative(irn)) {
757 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
758 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
760 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
761 set_irn_n(irn, reqs[i]->same_pos, in2_node);
762 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
769 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
770 /* create copy from in register */
771 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
773 DBG_OPT_2ADDRCPY(copy);
775 /* destination is the out register */
776 arch_set_irn_register(cg->arch_env, copy, out_reg);
778 /* insert copy before the node into the schedule */
779 sched_add_before(irn, copy);
782 set_irn_n(irn, reqs[i]->same_pos, copy);
789 /* If we have a CondJmp/CmpSet/xCmpSet with immediate, we need to */
790 /* check if it's the right operand, otherwise we have */
791 /* to change it, as CMP doesn't support immediate as */
793 if ((is_ia32_CondJmp(irn) || is_ia32_CmpSet(irn) || is_ia32_xCmpSet(irn)) &&
794 (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) &&
795 op_tp == ia32_AddrModeS)
797 set_ia32_op_type(irn, ia32_AddrModeD);
798 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
801 /* check if there is a sub which need to be transformed */
802 ia32_transform_sub_to_neg_add(irn, cg);
804 /* transform a LEA into an Add if possible */
805 ia32_transform_lea_to_add(irn, cg);
809 /* check for peephole optimization */
810 ia32_peephole_optimization(irn, cg);
813 static void ia32_finish_irg_walker(ir_node *block, void *env) {
816 for (irn = sched_first(block); !sched_is_end(irn); irn = next) {
817 next = sched_next(irn);
818 ia32_finish_node(irn, env);
822 static void ia32_push_on_queue_walker(ir_node *block, void *env) {
824 waitq_put(wq, block);
829 * Add Copy nodes for not fulfilled should_be_equal constraints
831 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
832 waitq *wq = new_waitq();
834 /* Push the blocks on the waitq because ia32_finish_irg_walker starts more walks ... */
835 irg_block_walk_graph(irg, NULL, ia32_push_on_queue_walker, wq);
837 while (! waitq_empty(wq)) {
838 ir_node *block = waitq_get(wq);
839 ia32_finish_irg_walker(block, cg);
847 * Dummy functions for hooks we don't need but which must be filled.
849 static void ia32_before_sched(void *self) {
853 * Called before the register allocator.
854 * Calculate a block schedule here. We need it for the x87
855 * simulator and the emitter.
857 static void ia32_before_ra(void *self) {
858 ia32_code_gen_t *cg = self;
860 cg->blk_sched = sched_create_block_schedule(cg->irg);
865 * Transforms a be node into a Load.
867 static void transform_to_Load(ia32_transform_env_t *env) {
868 ir_node *irn = env->irn;
869 entity *ent = be_get_frame_entity(irn);
870 ir_mode *mode = env->mode;
871 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
872 ir_node *nomem = new_rd_NoMem(env->irg);
873 ir_node *sched_point = NULL;
874 ir_node *ptr = get_irn_n(irn, 0);
875 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
876 ir_node *new_op, *proj;
877 const arch_register_t *reg;
879 if (sched_is_scheduled(irn)) {
880 sched_point = sched_prev(irn);
883 if (mode_is_float(mode)) {
884 if (USE_SSE2(env->cg))
885 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
887 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
890 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
893 set_ia32_am_support(new_op, ia32_am_Source);
894 set_ia32_op_type(new_op, ia32_AddrModeS);
895 set_ia32_am_flavour(new_op, ia32_B);
896 set_ia32_ls_mode(new_op, mode);
897 set_ia32_frame_ent(new_op, ent);
898 set_ia32_use_frame(new_op);
900 DBG_OPT_RELOAD2LD(irn, new_op);
902 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
905 sched_add_after(sched_point, new_op);
906 sched_add_after(new_op, proj);
911 /* copy the register from the old node to the new Load */
912 reg = arch_get_irn_register(env->cg->arch_env, irn);
913 arch_set_irn_register(env->cg->arch_env, new_op, reg);
915 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
921 * Transforms a be node into a Store.
923 static void transform_to_Store(ia32_transform_env_t *env) {
924 ir_node *irn = env->irn;
925 entity *ent = be_get_frame_entity(irn);
926 ir_mode *mode = env->mode;
927 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
928 ir_node *nomem = new_rd_NoMem(env->irg);
929 ir_node *ptr = get_irn_n(irn, 0);
930 ir_node *val = get_irn_n(irn, 1);
931 ir_node *new_op, *proj;
932 ir_node *sched_point = NULL;
934 if (sched_is_scheduled(irn)) {
935 sched_point = sched_prev(irn);
938 if (mode_is_float(mode)) {
939 if (USE_SSE2(env->cg))
940 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
942 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
944 else if (get_mode_size_bits(mode) == 8) {
945 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
948 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
951 set_ia32_am_support(new_op, ia32_am_Dest);
952 set_ia32_op_type(new_op, ia32_AddrModeD);
953 set_ia32_am_flavour(new_op, ia32_B);
954 set_ia32_ls_mode(new_op, mode);
955 set_ia32_frame_ent(new_op, ent);
956 set_ia32_use_frame(new_op);
958 DBG_OPT_SPILL2ST(irn, new_op);
960 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
963 sched_add_after(sched_point, new_op);
967 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
973 * Fix the mode of Spill/Reload
975 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
977 if (mode_is_float(mode)) {
989 * Block-Walker: Calls the transform functions Spill and Reload.
991 static void ia32_after_ra_walker(ir_node *block, void *env) {
992 ir_node *node, *prev;
993 ia32_code_gen_t *cg = env;
994 ia32_transform_env_t tenv;
997 tenv.irg = current_ir_graph;
999 DEBUG_ONLY(tenv.mod = cg->mod;)
1001 /* beware: the schedule is changed here */
1002 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1003 prev = sched_prev(node);
1004 if (be_is_Reload(node)) {
1005 /* we always reload the whole register */
1006 tenv.dbg = get_irn_dbg_info(node);
1008 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
1009 transform_to_Load(&tenv);
1011 else if (be_is_Spill(node)) {
1012 /* we always spill the whole register */
1013 tenv.dbg = get_irn_dbg_info(node);
1015 tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
1016 transform_to_Store(&tenv);
1022 * We transform Spill and Reload here. This needs to be done before
1023 * stack biasing otherwise we would miss the corrected offset for these nodes.
1025 * If x87 instruction should be emitted, run the x87 simulator and patch
1026 * the virtual instructions. This must obviously be done after register allocation.
1028 static void ia32_after_ra(void *self) {
1029 ia32_code_gen_t *cg = self;
1030 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
1032 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1033 if (cg->used_fp == fp_x87 || cg->force_sim) {
1034 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
1040 * Emits the code, closes the output file and frees
1041 * the code generator interface.
1043 static void ia32_codegen(void *self) {
1044 ia32_code_gen_t *cg = self;
1045 ir_graph *irg = cg->irg;
1047 ia32_finish_irg(irg, cg);
1048 be_dump(irg, "-finished", dump_ir_block_graph_sched);
1049 ia32_gen_routine(cg->isa->out, irg, cg);
1053 /* remove it from the isa */
1056 /* de-allocate code generator */
1057 del_set(cg->reg_set);
1062 static void *ia32_cg_init(const be_irg_t *birg);
1064 static const arch_code_generator_if_t ia32_code_gen_if = {
1066 NULL, /* before abi introduce hook */
1068 ia32_before_sched, /* before scheduling hook */
1069 ia32_before_ra, /* before register allocation hook */
1070 ia32_after_ra, /* after register allocation hook */
1071 ia32_codegen /* emit && done */
1075 * Initializes a IA32 code generator.
1077 static void *ia32_cg_init(const be_irg_t *birg) {
1078 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1079 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1081 cg->impl = &ia32_code_gen_if;
1082 cg->irg = birg->irg;
1083 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1084 cg->arch_env = birg->main_env->arch_env;
1087 cg->blk_sched = NULL;
1088 cg->fp_to_gp = NULL;
1089 cg->gp_to_fp = NULL;
1090 cg->fp_kind = isa->fp_kind;
1091 cg->used_fp = fp_none;
1093 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1095 /* copy optimizations from isa for easier access */
1102 if (isa->name_obst_size) {
1103 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
1104 isa->name_obst_size = 0;
1105 obstack_free(isa->name_obst, NULL);
1106 obstack_init(isa->name_obst);
1110 cur_reg_set = cg->reg_set;
1112 ia32_irn_ops.cg = cg;
1114 return (arch_code_generator_t *)cg;
1119 /*****************************************************************
1120 * ____ _ _ _____ _____
1121 * | _ \ | | | | |_ _|/ ____| /\
1122 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1123 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1124 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1125 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1127 *****************************************************************/
1130 * The template that generates a new ISA object.
1131 * Note that this template can be changed by command line
1134 static ia32_isa_t ia32_isa_template = {
1136 &ia32_isa_if, /* isa interface implementation */
1137 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1138 &ia32_gp_regs[REG_EBP], /* base pointer register */
1139 -1, /* stack direction */
1141 NULL, /* 16bit register names */
1142 NULL, /* 8bit register names */
1146 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1147 IA32_OPT_DOAM | /* optimize address mode default: on */
1148 IA32_OPT_LEA | /* optimize for LEAs default: on */
1149 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1150 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1151 IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
1152 arch_pentium_4, /* instruction architecture */
1153 arch_pentium_4, /* optimize for architecture */
1154 fp_sse2, /* use sse2 unit */
1155 NULL, /* current code generator */
1157 NULL, /* name obstack */
1158 0 /* name obst size */
1163 * Initializes the backend ISA.
1165 static void *ia32_init(FILE *file_handle) {
1166 static int inited = 0;
1172 isa = xmalloc(sizeof(*isa));
1173 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1175 ia32_register_init(isa);
1176 ia32_create_opcodes();
1178 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1179 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1180 /* no SSE2 for these cpu's */
1181 isa->fp_kind = fp_x87;
1183 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1184 /* Pentium 4 don't like inc and dec instructions */
1185 isa->opt &= ~IA32_OPT_INCDEC;
1188 isa->regs_16bit = pmap_create();
1189 isa->regs_8bit = pmap_create();
1190 isa->types = pmap_create();
1191 isa->tv_ent = pmap_create();
1192 isa->out = file_handle;
1194 ia32_build_16bit_reg_map(isa->regs_16bit);
1195 ia32_build_8bit_reg_map(isa->regs_8bit);
1197 /* patch register names of x87 registers */
1199 ia32_st_regs[0].name = "st";
1200 ia32_st_regs[1].name = "st(1)";
1201 ia32_st_regs[2].name = "st(2)";
1202 ia32_st_regs[3].name = "st(3)";
1203 ia32_st_regs[4].name = "st(4)";
1204 ia32_st_regs[5].name = "st(5)";
1205 ia32_st_regs[6].name = "st(6)";
1206 ia32_st_regs[7].name = "st(7)";
1210 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1211 obstack_init(isa->name_obst);
1212 isa->name_obst_size = 0;
1215 ia32_handle_intrinsics();
1216 ia32_switch_section(NULL, NO_SECTION);
1217 fprintf(isa->out, "\t.intel_syntax\n");
1227 * Closes the output file and frees the ISA structure.
1229 static void ia32_done(void *self) {
1230 ia32_isa_t *isa = self;
1232 /* emit now all global declarations */
1233 ia32_gen_decls(isa->out);
1235 pmap_destroy(isa->regs_16bit);
1236 pmap_destroy(isa->regs_8bit);
1237 pmap_destroy(isa->tv_ent);
1238 pmap_destroy(isa->types);
1241 //printf("name obst size = %d bytes\n", isa->name_obst_size);
1242 obstack_free(isa->name_obst, NULL);
1250 * Return the number of register classes for this architecture.
1251 * We report always these:
1252 * - the general purpose registers
1253 * - the SSE floating point register set
1254 * - the virtual floating point registers
1256 static int ia32_get_n_reg_class(const void *self) {
1261 * Return the register class for index i.
1263 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1264 const ia32_isa_t *isa = self;
1265 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1267 return &ia32_reg_classes[CLASS_ia32_gp];
1269 return &ia32_reg_classes[CLASS_ia32_xmm];
1271 return &ia32_reg_classes[CLASS_ia32_vfp];
1275 * Get the register class which shall be used to store a value of a given mode.
1276 * @param self The this pointer.
1277 * @param mode The mode in question.
1278 * @return A register class which can hold values of the given mode.
1280 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1281 const ia32_isa_t *isa = self;
1282 if (mode_is_float(mode)) {
1283 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1286 return &ia32_reg_classes[CLASS_ia32_gp];
1290 * Get the ABI restrictions for procedure calls.
1291 * @param self The this pointer.
1292 * @param method_type The type of the method (procedure) in question.
1293 * @param abi The abi object to be modified
1295 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1296 const ia32_isa_t *isa = self;
1299 unsigned cc = get_method_calling_convention(method_type);
1300 int n = get_method_n_params(method_type);
1303 int i, ignore_1, ignore_2;
1305 const arch_register_t *reg;
1306 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1308 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1310 /* set abi flags for calls */
1311 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1312 call_flags.bits.store_args_sequential = use_push;
1313 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1314 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1315 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1317 /* set stack parameter passing style */
1318 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1320 /* collect the mode for each type */
1321 modes = alloca(n * sizeof(modes[0]));
1323 for (i = 0; i < n; i++) {
1324 tp = get_method_param_type(method_type, i);
1325 modes[i] = get_type_mode(tp);
1328 /* set register parameters */
1329 if (cc & cc_reg_param) {
1330 /* determine the number of parameters passed via registers */
1331 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1333 /* loop over all parameters and set the register requirements */
1334 for (i = 0; i <= biggest_n; i++) {
1335 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1336 assert(reg && "kaputt");
1337 be_abi_call_param_reg(abi, i, reg);
1344 /* set stack parameters */
1345 for (i = stack_idx; i < n; i++) {
1346 be_abi_call_param_stack(abi, i, 1, 0, 0);
1350 /* set return registers */
1351 n = get_method_n_ress(method_type);
1353 assert(n <= 2 && "more than two results not supported");
1355 /* In case of 64bit returns, we will have two 32bit values */
1357 tp = get_method_res_type(method_type, 0);
1358 mode = get_type_mode(tp);
1360 assert(!mode_is_float(mode) && "two FP results not supported");
1362 tp = get_method_res_type(method_type, 1);
1363 mode = get_type_mode(tp);
1365 assert(!mode_is_float(mode) && "two FP results not supported");
1367 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1368 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1371 const arch_register_t *reg;
1373 tp = get_method_res_type(method_type, 0);
1374 assert(is_atomic_type(tp));
1375 mode = get_type_mode(tp);
1377 reg = mode_is_float(mode) ?
1378 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1379 &ia32_gp_regs[REG_EAX];
1381 be_abi_call_res_reg(abi, 0, reg);
1386 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1387 return &ia32_irn_ops;
1390 const arch_irn_handler_t ia32_irn_handler = {
1394 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1395 return &ia32_irn_handler;
1398 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1399 return is_ia32_irn(irn);
1403 * Initializes the code generator interface.
1405 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1406 return &ia32_code_gen_if;
1409 list_sched_selector_t ia32_sched_selector;
1412 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1414 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1415 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1416 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1417 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1418 return &ia32_sched_selector;
1422 * Returns the necessary byte alignment for storing a register of given class.
1424 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1425 ir_mode *mode = arch_register_class_mode(cls);
1426 int bytes = get_mode_size_bytes(mode);
1428 if (mode_is_float(mode) && bytes > 8)
1433 static ia32_intrinsic_env_t intrinsic_env = { NULL, NULL };
1436 * Returns the libFirm configuration parameter for this backend.
1438 static const backend_params *ia32_get_libfirm_params(void) {
1439 static const arch_dep_params_t ad = {
1440 1, /* also use subs */
1441 4, /* maximum shifts */
1442 31, /* maximum shift amount */
1444 1, /* allow Mulhs */
1445 1, /* allow Mulus */
1446 32 /* Mulh allowed up to 32 bit */
1448 static backend_params p = {
1449 NULL, /* no additional opcodes */
1450 NULL, /* will be set later */
1451 1, /* need dword lowering */
1452 ia32_create_intrinsic_fkt,
1453 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1461 /* instruction set architectures. */
1462 static const lc_opt_enum_int_items_t arch_items[] = {
1463 { "386", arch_i386, },
1464 { "486", arch_i486, },
1465 { "pentium", arch_pentium, },
1466 { "586", arch_pentium, },
1467 { "pentiumpro", arch_pentium_pro, },
1468 { "686", arch_pentium_pro, },
1469 { "pentiummmx", arch_pentium_mmx, },
1470 { "pentium2", arch_pentium_2, },
1471 { "p2", arch_pentium_2, },
1472 { "pentium3", arch_pentium_3, },
1473 { "p3", arch_pentium_3, },
1474 { "pentium4", arch_pentium_4, },
1475 { "p4", arch_pentium_4, },
1476 { "pentiumm", arch_pentium_m, },
1477 { "pm", arch_pentium_m, },
1478 { "core", arch_core, },
1480 { "athlon", arch_athlon, },
1481 { "athlon64", arch_athlon_64, },
1482 { "opteron", arch_opteron, },
1486 static lc_opt_enum_int_var_t arch_var = {
1487 &ia32_isa_template.arch, arch_items
1490 static lc_opt_enum_int_var_t opt_arch_var = {
1491 &ia32_isa_template.opt_arch, arch_items
1494 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1496 { "sse2", fp_sse2 },
1500 static lc_opt_enum_int_var_t fp_unit_var = {
1501 &ia32_isa_template.fp_kind, fp_unit_items
1504 static const lc_opt_enum_int_items_t gas_items[] = {
1505 { "linux", ASM_LINUX_GAS },
1506 { "mingw", ASM_MINGW_GAS },
1510 static lc_opt_enum_int_var_t gas_var = {
1511 (int *)&asm_flavour, gas_items
1514 static const lc_opt_table_entry_t ia32_options[] = {
1515 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1516 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1517 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1518 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1519 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1520 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1521 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1522 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1523 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1528 * Register command line options for the ia32 backend.
1532 * ia32-arch=arch create instruction for arch
1533 * ia32-opt=arch optimize for run on arch
1534 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1535 * ia32-incdec optimize for inc/dec
1536 * ia32-noaddrmode do not use address mode
1537 * ia32-nolea do not optimize for LEAs
1538 * ia32-noplacecnst do not place constants,
1539 * ia32-noimmop no operations with immediates
1540 * ia32-noextbb do not use extended basic block scheduling
1541 * ia32-gasmode set the GAS compatibility mode
1543 static void ia32_register_options(lc_opt_entry_t *ent)
1545 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1546 lc_opt_add_table(be_grp_ia32, ia32_options);
1548 #endif /* WITH_LIBCORE */
1550 const arch_isa_if_t ia32_isa_if = {
1553 ia32_get_n_reg_class,
1555 ia32_get_reg_class_for_mode,
1557 ia32_get_irn_handler,
1558 ia32_get_code_generator_if,
1559 ia32_get_list_sched_selector,
1560 ia32_get_reg_class_alignment,
1561 ia32_get_libfirm_params,
1563 ia32_register_options