2 * This is the main ia32 firm backend driver.
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
41 #include "bearch_ia32_t.h"
43 #include "ia32_new_nodes.h" /* ia32 nodes interface */
44 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
45 #include "ia32_gen_decls.h" /* interface declaration emitter */
46 #include "ia32_transform.h"
47 #include "ia32_emitter.h"
48 #include "ia32_map_regs.h"
49 #include "ia32_optimize.h"
51 #include "ia32_dbg_stat.h"
53 #define DEBUG_MODULE "firm.be.ia32.isa"
56 static set *cur_reg_set = NULL;
59 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
61 /* Creates the unique per irg GP NoReg node. */
62 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
63 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
66 /* Creates the unique per irg FP NoReg node. */
67 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
68 return be_abi_get_callee_save_irn(cg->birg->abi,
69 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
72 /**************************************************
75 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
76 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
77 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
78 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
81 **************************************************/
83 static ir_node *my_skip_proj(const ir_node *n) {
91 * Return register requirements for an ia32 node.
92 * If the node returns a tuple (mode_T) then the proj's
93 * will be asked for this information.
95 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
96 const ia32_irn_ops_t *ops = self;
97 const ia32_register_req_t *irn_req;
98 long node_pos = pos == -1 ? 0 : pos;
99 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
100 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
102 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
103 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
107 if (mode == mode_T && pos < 0) {
108 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
112 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
116 node_pos = ia32_translate_proj_pos(irn);
122 irn = my_skip_proj(irn);
124 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
127 if (is_ia32_irn(irn)) {
129 irn_req = get_ia32_in_req(irn, pos);
132 irn_req = get_ia32_out_req(irn, node_pos);
135 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
137 memcpy(req, &(irn_req->req), sizeof(*req));
139 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
140 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
141 req->other_same = get_irn_n(irn, irn_req->same_pos);
144 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
145 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
146 req->other_different = get_irn_n(irn, irn_req->different_pos);
150 /* treat Unknowns like Const with default requirements */
151 if (is_Unknown(irn)) {
152 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
153 if (mode_is_float(mode)) {
154 if (USE_SSE2(ops->cg))
155 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
157 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
159 else if (mode_is_int(mode) || mode_is_reference(mode))
160 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
161 else if (mode == mode_T || mode == mode_M) {
162 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
166 assert(0 && "unsupported Unknown-Mode");
169 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
177 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
179 const ia32_irn_ops_t *ops = self;
181 if (get_irn_mode(irn) == mode_X) {
185 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
188 pos = ia32_translate_proj_pos(irn);
189 irn = my_skip_proj(irn);
192 if (is_ia32_irn(irn)) {
193 const arch_register_t **slots;
195 slots = get_ia32_slots(irn);
199 ia32_set_firm_reg(irn, reg, cur_reg_set);
203 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
205 const arch_register_t *reg = NULL;
209 if (get_irn_mode(irn) == mode_X) {
213 pos = ia32_translate_proj_pos(irn);
214 irn = my_skip_proj(irn);
217 if (is_ia32_irn(irn)) {
218 const arch_register_t **slots;
219 slots = get_ia32_slots(irn);
223 reg = ia32_get_firm_reg(irn, cur_reg_set);
229 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
230 irn = my_skip_proj(irn);
232 return arch_irn_class_branch;
233 else if (is_ia32_Cnst(irn))
234 return arch_irn_class_const;
235 else if (is_ia32_irn(irn))
236 return arch_irn_class_normal;
241 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
242 irn = my_skip_proj(irn);
243 if (is_ia32_irn(irn))
244 return get_ia32_flags(irn);
247 return arch_irn_flags_ignore;
252 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
253 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
256 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
258 const ia32_irn_ops_t *ops = self;
260 if (get_ia32_frame_ent(irn)) {
261 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
263 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
264 snprintf(buf, sizeof(buf), "%d", bias);
266 if (get_ia32_op_type(irn) == ia32_Normal) {
267 set_ia32_cnst(irn, buf);
270 add_ia32_am_offs(irn, buf);
272 set_ia32_am_flavour(irn, am_flav);
278 be_abi_call_flags_bits_t flags;
279 const arch_isa_t *isa;
280 const arch_env_t *aenv;
284 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
286 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
287 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
288 env->flags = fl.bits;
291 env->isa = aenv->isa;
296 * Put all registers which are saved by the prologue/epilogue in a set.
298 * @param self The callback object.
299 * @param s The result set.
301 static void ia32_abi_dont_save_regs(void *self, pset *s)
303 ia32_abi_env_t *env = self;
304 if(env->flags.try_omit_fp)
305 pset_insert_ptr(s, env->isa->bp);
309 * Generate the routine prologue.
311 * @param self The callback object.
312 * @param mem A pointer to the mem node. Update this if you define new memory.
313 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
315 * @return The register which shall be used as a stack frame base.
317 * All nodes which define registers in @p reg_map must keep @p reg_map current.
319 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
321 ia32_abi_env_t *env = self;
323 if (!env->flags.try_omit_fp) {
324 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
325 ir_node *bl = get_irg_start_block(env->irg);
326 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
327 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
331 push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
332 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
333 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
335 /* the push must have SP out register */
336 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
337 set_ia32_flags(push, arch_irn_flags_ignore);
339 /* move esp to ebp */
340 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
341 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
342 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
343 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
345 /* beware: the copy must be done before any other sp use */
346 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
347 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
348 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
349 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
351 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
352 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
361 * Generate the routine epilogue.
362 * @param self The callback object.
363 * @param bl The block for the epilog
364 * @param mem A pointer to the mem node. Update this if you define new memory.
365 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
366 * @return The register which shall be used as a stack frame base.
368 * All nodes which define registers in @p reg_map must keep @p reg_map current.
370 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
372 ia32_abi_env_t *env = self;
373 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
374 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
376 if (env->flags.try_omit_fp) {
377 /* simply remove the stack frame here */
378 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
381 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
382 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
383 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
385 /* gcc always emits a leave at the end of a routine */
386 if (1 || ARCH_AMD(isa->opt_arch)) {
390 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
391 set_ia32_flags(leave, arch_irn_flags_ignore);
392 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
393 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
394 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
399 /* copy ebp to esp */
400 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
403 pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
404 set_ia32_flags(pop, arch_irn_flags_ignore);
405 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
406 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
407 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
409 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
410 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
413 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
414 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
418 * Produces the type which sits between the stack args and the locals on the stack.
419 * it will contain the return address and space to store the old base pointer.
420 * @return The Firm type modeling the ABI between type.
422 static ir_type *ia32_abi_get_between_type(void *self)
424 static ir_type *omit_fp_between_type = NULL;
425 static ir_type *between_type = NULL;
427 ia32_abi_env_t *env = self;
431 entity *ret_addr_ent;
432 entity *omit_fp_ret_addr_ent;
434 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
435 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
437 between_type = new_type_class(new_id_from_str("ia32_between_type"));
438 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
439 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
441 set_entity_offset_bytes(old_bp_ent, 0);
442 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
443 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
445 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
446 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
448 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
449 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
452 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
455 static const be_abi_callbacks_t ia32_abi_callbacks = {
458 ia32_abi_get_between_type,
459 ia32_abi_dont_save_regs,
464 /* fill register allocator interface */
466 static const arch_irn_ops_if_t ia32_irn_ops_if = {
467 ia32_get_irn_reg_req,
472 ia32_get_frame_entity,
476 ia32_irn_ops_t ia32_irn_ops = {
483 /**************************************************
486 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
487 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
488 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
489 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
492 **************************************************/
495 * Transforms the standard firm graph into
498 static void ia32_prepare_graph(void *self) {
499 ia32_code_gen_t *cg = self;
500 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
502 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
504 /* 1st: transform constants and psi condition trees */
505 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_psi_cond_tree, cg);
507 /* 2nd: transform all remaining nodes */
508 ia32_register_transformers();
509 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
510 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
512 /* 3rd: optimize address mode */
513 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
514 ia32_optimize_addressmode(cg);
515 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
516 DEBUG_ONLY(cg->mod = old_mod;)
519 static INLINE int need_constraint_copy(ir_node *irn) {
521 ! is_ia32_Lea(irn) && \
522 ! is_ia32_Conv_I2I(irn) && \
523 ! is_ia32_Conv_I2I8Bit(irn) && \
524 ! is_ia32_CmpCMov(irn) && \
525 ! is_ia32_CmpSet(irn);
529 * Insert copies for all ia32 nodes where the should_be_same requirement
531 * Transform Sub into Neg -- Add if IN2 == OUT
533 static void ia32_finish_node(ir_node *irn, void *env) {
534 ia32_code_gen_t *cg = env;
535 const ia32_register_req_t **reqs;
536 const arch_register_t *out_reg, *in_reg, *in2_reg;
538 ir_node *copy, *in_node, *block, *in2_node;
539 ia32_op_type_t op_tp;
541 if (is_ia32_irn(irn)) {
542 /* AM Dest nodes don't produce any values */
543 op_tp = get_ia32_op_type(irn);
544 if (op_tp == ia32_AddrModeD)
547 reqs = get_ia32_out_req_all(irn);
548 n_res = get_ia32_n_res(irn);
549 block = get_nodes_block(irn);
551 /* check all OUT requirements, if there is a should_be_same */
552 if ((op_tp == ia32_Normal || op_tp == ia32_AddrModeS) && need_constraint_copy(irn))
554 for (i = 0; i < n_res; i++) {
555 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
556 /* get in and out register */
557 out_reg = get_ia32_out_reg(irn, i);
558 in_node = get_irn_n(irn, reqs[i]->same_pos);
559 in_reg = arch_get_irn_register(cg->arch_env, in_node);
561 /* don't copy ignore nodes */
562 if (arch_irn_is(cg->arch_env, in_node, ignore) && is_Proj(in_node))
565 /* check if in and out register are equal */
566 if (! REGS_ARE_EQUAL(out_reg, in_reg)) {
567 /* in case of a commutative op: just exchange the in's */
568 /* beware: the current op could be everything, so test for ia32 */
569 /* commutativity first before getting the second in */
570 if (is_ia32_commutative(irn)) {
571 in2_node = get_irn_n(irn, reqs[i]->same_pos ^ 1);
572 in2_reg = arch_get_irn_register(cg->arch_env, in2_node);
574 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
575 set_irn_n(irn, reqs[i]->same_pos, in2_node);
576 set_irn_n(irn, reqs[i]->same_pos ^ 1, in_node);
583 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
584 /* create copy from in register */
585 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
587 DBG_OPT_2ADDRCPY(copy);
589 /* destination is the out register */
590 arch_set_irn_register(cg->arch_env, copy, out_reg);
592 /* insert copy before the node into the schedule */
593 sched_add_before(irn, copy);
596 set_irn_n(irn, reqs[i]->same_pos, copy);
603 /* If we have a CondJmp/CmpSet/xCmpSet with immediate, we need to */
604 /* check if it's the right operand, otherwise we have */
605 /* to change it, as CMP doesn't support immediate as */
607 if ((is_ia32_CondJmp(irn) || is_ia32_CmpSet(irn) || is_ia32_xCmpSet(irn)) &&
608 (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) &&
609 op_tp == ia32_AddrModeS)
611 set_ia32_op_type(irn, ia32_AddrModeD);
612 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
615 /* check if there is a sub which need to be transformed */
616 ia32_transform_sub_to_neg_add(irn, cg);
618 /* transform a LEA into an Add if possible */
619 //ia32_transform_lea_to_add(irn, cg);
623 /* check for peephole optimization */
624 ia32_peephole_optimization(irn, cg);
627 static void ia32_finish_irg_walker(ir_node *block, void *env) {
630 for (irn = sched_first(block); !sched_is_end(irn); irn = next) {
631 next = sched_next(irn);
632 ia32_finish_node(irn, env);
637 * Add Copy nodes for not fulfilled should_be_equal constraints
639 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
640 irg_block_walk_graph(irg, NULL, ia32_finish_irg_walker, cg);
646 * Dummy functions for hooks we don't need but which must be filled.
648 static void ia32_before_sched(void *self) {
652 * Called before the register allocator.
653 * Calculate a block schedule here. We need it for the x87
654 * simulator and the emitter.
656 static void ia32_before_ra(void *self) {
657 ia32_code_gen_t *cg = self;
659 cg->blk_sched = sched_create_block_schedule(cg->irg);
664 * Transforms a be node into a Load.
666 static void transform_to_Load(ia32_transform_env_t *env) {
667 ir_node *irn = env->irn;
668 entity *ent = be_get_frame_entity(irn);
669 ir_mode *mode = env->mode;
670 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
671 ir_node *nomem = new_rd_NoMem(env->irg);
672 ir_node *sched_point = NULL;
673 ir_node *ptr = get_irn_n(irn, 0);
674 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
675 ir_node *new_op, *proj;
676 const arch_register_t *reg;
678 if (sched_is_scheduled(irn)) {
679 sched_point = sched_prev(irn);
682 if (mode_is_float(mode)) {
683 if (USE_SSE2(env->cg))
684 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
686 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
689 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
692 set_ia32_am_support(new_op, ia32_am_Source);
693 set_ia32_op_type(new_op, ia32_AddrModeS);
694 set_ia32_am_flavour(new_op, ia32_B);
695 set_ia32_ls_mode(new_op, mode);
696 set_ia32_frame_ent(new_op, ent);
697 set_ia32_use_frame(new_op);
699 DBG_OPT_RELOAD2LD(irn, new_op);
701 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
704 sched_add_after(sched_point, new_op);
705 sched_add_after(new_op, proj);
710 /* copy the register from the old node to the new Load */
711 reg = arch_get_irn_register(env->cg->arch_env, irn);
712 arch_set_irn_register(env->cg->arch_env, new_op, reg);
714 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
720 * Transforms a be node into a Store.
722 static void transform_to_Store(ia32_transform_env_t *env) {
723 ir_node *irn = env->irn;
724 entity *ent = be_get_frame_entity(irn);
725 ir_mode *mode = env->mode;
726 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
727 ir_node *nomem = new_rd_NoMem(env->irg);
728 ir_node *ptr = get_irn_n(irn, 0);
729 ir_node *val = get_irn_n(irn, 1);
730 ir_node *new_op, *proj;
731 ir_node *sched_point = NULL;
733 if (sched_is_scheduled(irn)) {
734 sched_point = sched_prev(irn);
737 if (mode_is_float(mode)) {
738 if (USE_SSE2(env->cg))
739 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
741 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
743 else if (get_mode_size_bits(mode) == 8) {
744 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
747 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
750 set_ia32_am_support(new_op, ia32_am_Dest);
751 set_ia32_op_type(new_op, ia32_AddrModeD);
752 set_ia32_am_flavour(new_op, ia32_B);
753 set_ia32_ls_mode(new_op, mode);
754 set_ia32_frame_ent(new_op, ent);
755 set_ia32_use_frame(new_op);
757 DBG_OPT_SPILL2ST(irn, new_op);
759 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
762 sched_add_after(sched_point, new_op);
763 sched_add_after(new_op, proj);
768 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, new_op));
774 * Fix the mode of Spill/Reload
776 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
778 if (mode_is_float(mode)) {
790 * Block-Walker: Calls the transform functions Spill and Reload.
792 static void ia32_after_ra_walker(ir_node *block, void *env) {
793 ir_node *node, *prev;
794 ia32_code_gen_t *cg = env;
795 ia32_transform_env_t tenv;
798 tenv.irg = current_ir_graph;
800 DEBUG_ONLY(tenv.mod = cg->mod;)
802 /* beware: the schedule is changed here */
803 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
804 prev = sched_prev(node);
805 if (be_is_Reload(node)) {
806 /* we always reload the whole register */
807 tenv.dbg = get_irn_dbg_info(node);
809 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
810 transform_to_Load(&tenv);
812 else if (be_is_Spill(node)) {
813 /* we always spill the whole register */
814 tenv.dbg = get_irn_dbg_info(node);
816 tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
817 transform_to_Store(&tenv);
823 * We transform Spill and Reload here. This needs to be done before
824 * stack biasing otherwise we would miss the corrected offset for these nodes.
826 * If x87 instruction should be emitted, run the x87 simulator and patch
827 * the virtual instructions. This must obviously be done after register allocation.
829 static void ia32_after_ra(void *self) {
830 ia32_code_gen_t *cg = self;
831 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
833 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
834 if (cg->used_fp == fp_x87) {
835 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
841 * Emits the code, closes the output file and frees
842 * the code generator interface.
844 static void ia32_codegen(void *self) {
845 ia32_code_gen_t *cg = self;
846 ir_graph *irg = cg->irg;
848 ia32_finish_irg(irg, cg);
849 be_dump(irg, "-finished", dump_ir_block_graph_sched);
850 ia32_gen_routine(cg->isa->out, irg, cg);
854 /* remove it from the isa */
857 /* de-allocate code generator */
858 del_set(cg->reg_set);
863 static void *ia32_cg_init(const be_irg_t *birg);
865 static const arch_code_generator_if_t ia32_code_gen_if = {
867 NULL, /* before abi introduce hook */
869 ia32_before_sched, /* before scheduling hook */
870 ia32_before_ra, /* before register allocation hook */
871 ia32_after_ra, /* after register allocation hook */
872 ia32_codegen /* emit && done */
876 * Initializes a IA32 code generator.
878 static void *ia32_cg_init(const be_irg_t *birg) {
879 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
880 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
882 cg->impl = &ia32_code_gen_if;
884 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
885 cg->arch_env = birg->main_env->arch_env;
888 cg->blk_sched = NULL;
891 cg->fp_kind = isa->fp_kind;
892 cg->used_fp = fp_none;
894 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
896 /* copy optimizations from isa for easier access */
903 if (isa->name_obst_size) {
904 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
905 isa->name_obst_size = 0;
906 obstack_free(isa->name_obst, NULL);
907 obstack_init(isa->name_obst);
911 cur_reg_set = cg->reg_set;
913 ia32_irn_ops.cg = cg;
915 return (arch_code_generator_t *)cg;
920 /*****************************************************************
921 * ____ _ _ _____ _____
922 * | _ \ | | | | |_ _|/ ____| /\
923 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
924 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
925 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
926 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
928 *****************************************************************/
931 * The template that generates a new ISA object.
932 * Note that this template can be changed by command line
935 static ia32_isa_t ia32_isa_template = {
937 &ia32_isa_if, /* isa interface implementation */
938 &ia32_gp_regs[REG_ESP], /* stack pointer register */
939 &ia32_gp_regs[REG_EBP], /* base pointer register */
940 -1, /* stack direction */
942 NULL, /* 16bit register names */
943 NULL, /* 8bit register names */
947 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
948 IA32_OPT_DOAM | /* optimize address mode default: on */
949 IA32_OPT_LEA | /* optimize for LEAs default: on */
950 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
951 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
952 IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
953 arch_pentium_4, /* instruction architecture */
954 arch_pentium_4, /* optimize for architecture */
955 fp_sse2, /* use sse2 unit */
956 NULL, /* current code generator */
958 NULL, /* name obstack */
959 0 /* name obst size */
964 * Initializes the backend ISA.
966 static void *ia32_init(FILE *file_handle) {
967 static int inited = 0;
973 isa = xmalloc(sizeof(*isa));
974 memcpy(isa, &ia32_isa_template, sizeof(*isa));
976 ia32_register_init(isa);
977 ia32_create_opcodes();
979 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
980 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
981 /* no SSE2 for these cpu's */
982 isa->fp_kind = fp_x87;
984 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
985 /* Pentium 4 don't like inc and dec instructions */
986 isa->opt &= ~IA32_OPT_INCDEC;
989 isa->regs_16bit = pmap_create();
990 isa->regs_8bit = pmap_create();
991 isa->types = pmap_create();
992 isa->tv_ent = pmap_create();
993 isa->out = file_handle;
995 ia32_build_16bit_reg_map(isa->regs_16bit);
996 ia32_build_8bit_reg_map(isa->regs_8bit);
998 /* patch register names of x87 registers */
1000 ia32_st_regs[0].name = "st";
1001 ia32_st_regs[1].name = "st(1)";
1002 ia32_st_regs[2].name = "st(2)";
1003 ia32_st_regs[3].name = "st(3)";
1004 ia32_st_regs[4].name = "st(4)";
1005 ia32_st_regs[5].name = "st(5)";
1006 ia32_st_regs[6].name = "st(6)";
1007 ia32_st_regs[7].name = "st(7)";
1011 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1012 obstack_init(isa->name_obst);
1013 isa->name_obst_size = 0;
1016 fprintf(isa->out, "\t.intel_syntax\n");
1026 * Closes the output file and frees the ISA structure.
1028 static void ia32_done(void *self) {
1029 ia32_isa_t *isa = self;
1031 /* emit now all global declarations */
1032 ia32_gen_decls(isa->out);
1034 pmap_destroy(isa->regs_16bit);
1035 pmap_destroy(isa->regs_8bit);
1036 pmap_destroy(isa->tv_ent);
1037 pmap_destroy(isa->types);
1040 //printf("name obst size = %d bytes\n", isa->name_obst_size);
1041 obstack_free(isa->name_obst, NULL);
1049 * Return the number of register classes for this architecture.
1050 * We report always these:
1051 * - the general purpose registers
1052 * - the floating point register set (depending on the unit used for FP)
1053 * - MMX/SSE registers (currently not supported)
1055 static int ia32_get_n_reg_class(const void *self) {
1060 * Return the register class for index i.
1062 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1063 const ia32_isa_t *isa = self;
1064 assert(i >= 0 && i < 2 && "Invalid ia32 register class requested.");
1066 return &ia32_reg_classes[CLASS_ia32_gp];
1067 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1071 * Get the register class which shall be used to store a value of a given mode.
1072 * @param self The this pointer.
1073 * @param mode The mode in question.
1074 * @return A register class which can hold values of the given mode.
1076 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1077 const ia32_isa_t *isa = self;
1078 if (mode_is_float(mode)) {
1079 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1082 return &ia32_reg_classes[CLASS_ia32_gp];
1086 * Get the ABI restrictions for procedure calls.
1087 * @param self The this pointer.
1088 * @param method_type The type of the method (procedure) in question.
1089 * @param abi The abi object to be modified
1091 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1092 const ia32_isa_t *isa = self;
1095 unsigned cc = get_method_calling_convention(method_type);
1096 int n = get_method_n_params(method_type);
1099 int i, ignore_1, ignore_2;
1101 const arch_register_t *reg;
1102 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1104 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1106 /* set abi flags for calls */
1107 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1108 call_flags.bits.store_args_sequential = use_push;
1109 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1110 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1111 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1113 /* set stack parameter passing style */
1114 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1116 /* collect the mode for each type */
1117 modes = alloca(n * sizeof(modes[0]));
1119 for (i = 0; i < n; i++) {
1120 tp = get_method_param_type(method_type, i);
1121 modes[i] = get_type_mode(tp);
1124 /* set register parameters */
1125 if (cc & cc_reg_param) {
1126 /* determine the number of parameters passed via registers */
1127 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1129 /* loop over all parameters and set the register requirements */
1130 for (i = 0; i <= biggest_n; i++) {
1131 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1132 assert(reg && "kaputt");
1133 be_abi_call_param_reg(abi, i, reg);
1140 /* set stack parameters */
1141 for (i = stack_idx; i < n; i++) {
1142 be_abi_call_param_stack(abi, i, 1, 0, 0);
1146 /* set return registers */
1147 n = get_method_n_ress(method_type);
1149 assert(n <= 2 && "more than two results not supported");
1151 /* In case of 64bit returns, we will have two 32bit values */
1153 tp = get_method_res_type(method_type, 0);
1154 mode = get_type_mode(tp);
1156 assert(!mode_is_float(mode) && "two FP results not supported");
1158 tp = get_method_res_type(method_type, 1);
1159 mode = get_type_mode(tp);
1161 assert(!mode_is_float(mode) && "two FP results not supported");
1163 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1164 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1167 const arch_register_t *reg;
1169 tp = get_method_res_type(method_type, 0);
1170 assert(is_atomic_type(tp));
1171 mode = get_type_mode(tp);
1173 reg = mode_is_float(mode) ?
1174 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1175 &ia32_gp_regs[REG_EAX];
1177 be_abi_call_res_reg(abi, 0, reg);
1182 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1183 return &ia32_irn_ops;
1186 const arch_irn_handler_t ia32_irn_handler = {
1190 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1191 return &ia32_irn_handler;
1194 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1195 return is_ia32_irn(irn);
1199 * Initializes the code generator interface.
1201 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1202 return &ia32_code_gen_if;
1205 list_sched_selector_t ia32_sched_selector;
1208 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1210 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1211 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1212 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1213 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1214 return &ia32_sched_selector;
1218 * Returns the necessary byte alignment for storing a register of given class.
1220 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1221 ir_mode *mode = arch_register_class_mode(cls);
1222 int bytes = get_mode_size_bytes(mode);
1224 if (mode_is_float(mode) && bytes > 8)
1231 /* instruction set architectures. */
1232 static const lc_opt_enum_int_items_t arch_items[] = {
1233 { "386", arch_i386, },
1234 { "486", arch_i486, },
1235 { "pentium", arch_pentium, },
1236 { "586", arch_pentium, },
1237 { "pentiumpro", arch_pentium_pro, },
1238 { "686", arch_pentium_pro, },
1239 { "pentiummmx", arch_pentium_mmx, },
1240 { "pentium2", arch_pentium_2, },
1241 { "p2", arch_pentium_2, },
1242 { "pentium3", arch_pentium_3, },
1243 { "p3", arch_pentium_3, },
1244 { "pentium4", arch_pentium_4, },
1245 { "p4", arch_pentium_4, },
1246 { "pentiumm", arch_pentium_m, },
1247 { "pm", arch_pentium_m, },
1248 { "core", arch_core, },
1250 { "athlon", arch_athlon, },
1251 { "athlon64", arch_athlon_64, },
1252 { "opteron", arch_opteron, },
1256 static lc_opt_enum_int_var_t arch_var = {
1257 &ia32_isa_template.arch, arch_items
1260 static lc_opt_enum_int_var_t opt_arch_var = {
1261 &ia32_isa_template.opt_arch, arch_items
1264 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1266 { "sse2", fp_sse2 },
1270 static lc_opt_enum_int_var_t fp_unit_var = {
1271 &ia32_isa_template.fp_kind, fp_unit_items
1274 static const lc_opt_enum_int_items_t gas_items[] = {
1275 { "linux", ASM_LINUX_GAS },
1276 { "mingw", ASM_MINGW_GAS },
1280 static lc_opt_enum_int_var_t gas_var = {
1281 (int *)&asm_flavour, gas_items
1284 static const lc_opt_table_entry_t ia32_options[] = {
1285 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1286 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1287 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1288 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1289 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1290 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1291 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1292 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1293 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1298 * Register command line options for the ia32 backend.
1302 * ia32-arch=arch create instruction for arch
1303 * ia32-opt=arch optimize for run on arch
1304 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1305 * ia32-incdec optimize for inc/dec
1306 * ia32-noaddrmode do not use address mode
1307 * ia32-nolea do not optimize for LEAs
1308 * ia32-noplacecnst do not place constants,
1309 * ia32-noimmop no operations with immediates
1310 * ia32-noextbb do not use extended basic block scheduling
1311 * ia32-gasmode set the GAS compatibility mode
1313 static void ia32_register_options(lc_opt_entry_t *ent)
1315 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1316 lc_opt_add_table(be_grp_ia32, ia32_options);
1318 #endif /* WITH_LIBCORE */
1320 const arch_isa_if_t ia32_isa_if = {
1323 ia32_get_n_reg_class,
1325 ia32_get_reg_class_for_mode,
1327 ia32_get_irn_handler,
1328 ia32_get_code_generator_if,
1329 ia32_get_list_sched_selector,
1330 ia32_get_reg_class_alignment,
1332 ia32_register_options