2 * This is the main ia32 firm backend driver.
17 #include "pseudo_irg.h"
21 #include "iredges_t.h"
29 #include "../beabi.h" /* the general register allocator interface */
30 #include "../benode_t.h"
31 #include "../belower.h"
32 #include "../besched_t.h"
34 #include "bearch_ia32_t.h"
36 #include "ia32_new_nodes.h" /* ia32 nodes interface */
37 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
38 #include "ia32_gen_decls.h" /* interface declaration emitter */
39 #include "ia32_transform.h"
40 #include "ia32_emitter.h"
41 #include "ia32_map_regs.h"
42 #include "ia32_optimize.h"
44 #define DEBUG_MODULE "firm.be.ia32.isa"
47 static set *cur_reg_set = NULL;
50 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
52 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
53 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
56 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
57 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
60 /**************************************************
63 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
64 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
65 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
66 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
69 **************************************************/
71 static ir_node *my_skip_proj(const ir_node *n) {
79 * Return register requirements for an ia32 node.
80 * If the node returns a tuple (mode_T) then the proj's
81 * will be asked for this information.
83 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
84 const ia32_register_req_t *irn_req;
85 long node_pos = pos == -1 ? 0 : pos;
86 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
87 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
89 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
90 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
94 if (mode == mode_T && pos < 0) {
95 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
99 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
104 node_pos = ia32_translate_proj_pos(irn);
110 irn = my_skip_proj(irn);
112 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
115 if (is_ia32_irn(irn)) {
117 irn_req = get_ia32_in_req(irn, pos);
120 irn_req = get_ia32_out_req(irn, node_pos);
123 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
125 memcpy(req, &(irn_req->req), sizeof(*req));
127 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
128 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
129 req->other_same = get_irn_n(irn, irn_req->same_pos);
132 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
133 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
134 req->other_different = get_irn_n(irn, irn_req->different_pos);
138 /* treat Phi like Const with default requirements */
140 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
141 if (mode_is_float(mode))
142 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
143 else if (mode_is_int(mode) || mode_is_reference(mode))
144 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
145 else if (mode == mode_T || mode == mode_M) {
146 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
150 assert(0 && "unsupported Phi-Mode");
153 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
161 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
163 const ia32_irn_ops_t *ops = self;
165 if (get_irn_mode(irn) == mode_X) {
169 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
172 pos = ia32_translate_proj_pos(irn);
173 irn = my_skip_proj(irn);
176 if (is_ia32_irn(irn)) {
177 const arch_register_t **slots;
179 slots = get_ia32_slots(irn);
183 ia32_set_firm_reg(irn, reg, cur_reg_set);
187 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
189 const arch_register_t *reg = NULL;
193 if (get_irn_mode(irn) == mode_X) {
197 pos = ia32_translate_proj_pos(irn);
198 irn = my_skip_proj(irn);
201 if (is_ia32_irn(irn)) {
202 const arch_register_t **slots;
203 slots = get_ia32_slots(irn);
207 reg = ia32_get_firm_reg(irn, cur_reg_set);
213 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
214 irn = my_skip_proj(irn);
216 return arch_irn_class_branch;
217 else if (is_ia32_irn(irn))
218 return arch_irn_class_normal;
223 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
224 irn = my_skip_proj(irn);
225 if (is_ia32_irn(irn))
226 return get_ia32_flags(irn);
232 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
233 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
236 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
238 const ia32_irn_ops_t *ops = self;
240 if (is_ia32_use_frame(irn) && bias != 0) {
241 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
243 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
244 snprintf(buf, sizeof(buf), "%d", bias);
245 add_ia32_am_offs(irn, buf);
247 set_ia32_am_flavour(irn, am_flav);
252 be_abi_call_flags_bits_t flags;
253 const arch_isa_t *isa;
257 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
259 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
260 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
261 env->flags = fl.bits;
263 env->isa = aenv->isa;
267 static void ia32_abi_dont_save_regs(void *self, pset *s)
269 ia32_abi_env_t *env = self;
270 if(env->flags.try_omit_fp)
271 pset_insert_ptr(s, env->isa->bp);
274 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
276 ia32_abi_env_t *env = self;
277 const arch_register_t *frame_reg = env->isa->sp;
279 if(!env->flags.try_omit_fp) {
280 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
281 ir_node *bl = get_irg_start_block(env->irg);
282 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
283 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
284 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
287 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, reg_size, be_stack_dir_along);
288 store_bp = new_rd_ia32_Store(NULL, env->irg, bl, curr_sp, curr_no_reg, curr_bp, *mem, mode_T);
289 set_ia32_am_support(store_bp, ia32_am_Dest);
290 set_ia32_am_flavour(store_bp, ia32_B);
291 set_ia32_op_type(store_bp, ia32_AddrModeD);
292 *mem = new_r_Proj(env->irg, bl, store_bp, mode_M, 0);
293 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
294 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
295 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
297 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
298 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
304 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
306 ia32_abi_env_t *env = self;
307 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
308 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
309 ir_node *curr_no_reg = be_abi_reg_map_get(reg_map, &ia32_gp_regs[REG_XXX]);
311 if(env->flags.try_omit_fp) {
312 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_against);
317 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
319 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
320 load_bp = new_rd_ia32_Load(NULL, env->irg, bl, curr_sp, curr_no_reg, *mem, mode_T);
321 set_ia32_am_support(load_bp, ia32_am_Source);
322 set_ia32_am_flavour(load_bp, ia32_B);
323 set_ia32_op_type(load_bp, ia32_AddrModeS);
324 set_ia32_ls_mode(load_bp, mode_bp);
325 curr_bp = new_r_Proj(env->irg, bl, load_bp, mode_bp, 0);
326 *mem = new_r_Proj(env->irg, bl, load_bp, mode_M, 1);
329 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
330 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
334 * Produces the type which sits between the stack args and the locals on the stack.
335 * it will contain the return address and space to store the old base pointer.
336 * @return The Firm type modeling the ABI between type.
338 static ir_type *ia32_abi_get_between_type(void *self)
340 static ir_type *omit_fp_between_type = NULL;
341 static ir_type *between_type = NULL;
343 ia32_abi_env_t *env = self;
347 entity *ret_addr_ent;
348 entity *omit_fp_ret_addr_ent;
350 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
351 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
353 between_type = new_type_class(new_id_from_str("ia32_between_type"));
354 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
355 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
357 set_entity_offset_bytes(old_bp_ent, 0);
358 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
359 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
361 omit_fp_between_type = new_type_class(new_id_from_str("ia32_between_type_omit_fp"));
362 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, new_id_from_str("ret_addr"), ret_addr_type);
364 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
365 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
368 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
371 static const be_abi_callbacks_t ia32_abi_callbacks = {
374 ia32_abi_get_between_type,
375 ia32_abi_dont_save_regs,
380 /* fill register allocator interface */
382 static const arch_irn_ops_if_t ia32_irn_ops_if = {
383 ia32_get_irn_reg_req,
388 ia32_get_frame_entity,
392 ia32_irn_ops_t ia32_irn_ops = {
399 /**************************************************
402 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
403 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
404 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
405 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
408 **************************************************/
411 * Transforms the standard firm graph into
414 static void ia32_prepare_graph(void *self) {
415 ia32_code_gen_t *cg = self;
416 firm_dbg_module_t *old_mod = cg->mod;
418 cg->mod = firm_dbg_register("firm.be.ia32.transform");
419 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
420 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
425 edges_deactivate(cg->irg);
426 //dead_node_elimination(cg->irg);
427 edges_activate(cg->irg);
429 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
430 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
436 * Insert copies for all ia32 nodes where the should_be_same requirement
438 * Transform Sub into Neg -- Add if IN2 == OUT
440 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
441 ia32_code_gen_t *cg = env;
442 const ia32_register_req_t **reqs;
443 const arch_register_t *out_reg, *in_reg;
445 ir_node *copy, *in_node, *block;
447 if (! is_ia32_irn(irn))
450 /* nodes with destination address mode don't produce values */
451 if (get_ia32_op_type(irn) == ia32_AddrModeD)
454 reqs = get_ia32_out_req_all(irn);
455 n_res = get_ia32_n_res(irn);
456 block = get_nodes_block(irn);
458 /* check all OUT requirements, if there is a should_be_same */
459 for (i = 0; i < n_res; i++) {
460 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
461 /* get in and out register */
462 out_reg = get_ia32_out_reg(irn, i);
463 in_node = get_irn_n(irn, reqs[i]->same_pos);
464 in_reg = arch_get_irn_register(cg->arch_env, in_node);
466 /* check if in and out register are equal */
467 if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
468 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
470 /* create copy from in register */
471 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
473 /* destination is the out register */
474 arch_set_irn_register(cg->arch_env, copy, out_reg);
476 /* insert copy before the node into the schedule */
477 sched_add_before(irn, copy);
480 set_irn_n(irn, reqs[i]->same_pos, copy);
485 /* check if there is a sub which need to be transformed */
486 ia32_transform_sub_to_neg_add(irn, cg);
488 /* transform a LEA into an Add if possible */
489 ia32_transform_lea_to_add(irn, cg);
491 /* check for peephole optimization */
492 ia32_peephole_optimization(irn, cg);
496 * Add Copy nodes for not fulfilled should_be_equal constraints
498 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
499 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
505 * Dummy functions for hooks we don't need but which must be filled.
507 static void ia32_before_sched(void *self) {
510 static void ia32_before_ra(void *self) {
516 * Transforms a be node into a Load.
518 static void transform_to_Load(ia32_transform_env_t *env) {
519 ir_node *irn = env->irn;
520 entity *ent = be_get_frame_entity(irn);
521 ir_mode *mode = env->mode;
522 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
523 ir_node *nomem = new_rd_NoMem(env->irg);
524 ir_node *sched_point = NULL;
525 ir_node *ptr = get_irn_n(irn, 0);
526 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
527 ir_node *new_op, *proj;
528 const arch_register_t *reg;
530 if (sched_is_scheduled(irn)) {
531 sched_point = sched_prev(irn);
534 if (mode_is_float(mode)) {
535 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
538 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
541 set_ia32_am_support(new_op, ia32_am_Source);
542 set_ia32_op_type(new_op, ia32_AddrModeS);
543 set_ia32_am_flavour(new_op, ia32_B);
544 set_ia32_ls_mode(new_op, mode);
545 set_ia32_frame_ent(new_op, ent);
546 set_ia32_use_frame(new_op);
548 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
551 sched_add_after(sched_point, new_op);
552 sched_add_after(new_op, proj);
557 /* copy the register from the old node to the new Load */
558 reg = arch_get_irn_register(env->cg->arch_env, irn);
559 arch_set_irn_register(env->cg->arch_env, new_op, reg);
566 * Transforms a be node into a Store.
568 static void transform_to_Store(ia32_transform_env_t *env) {
569 ir_node *irn = env->irn;
570 entity *ent = be_get_frame_entity(irn);
571 ir_mode *mode = env->mode;
572 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
573 ir_node *nomem = new_rd_NoMem(env->irg);
574 ir_node *ptr = get_irn_n(irn, 0);
575 ir_node *val = get_irn_n(irn, 1);
576 ir_node *new_op, *proj;
577 ir_node *sched_point = NULL;
579 if (sched_is_scheduled(irn)) {
580 sched_point = sched_prev(irn);
583 if (mode_is_float(mode)) {
584 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
586 else if (get_mode_size_bits(mode) == 8) {
587 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
590 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
593 set_ia32_am_support(new_op, ia32_am_Dest);
594 set_ia32_op_type(new_op, ia32_AddrModeD);
595 set_ia32_am_flavour(new_op, ia32_B);
596 set_ia32_ls_mode(new_op, get_irn_mode(val));
597 set_ia32_frame_ent(new_op, ent);
598 set_ia32_use_frame(new_op);
600 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
603 sched_add_after(sched_point, new_op);
604 sched_add_after(new_op, proj);
614 * Calls the transform functions for StackParam, Spill and Reload.
616 static void ia32_after_ra_walker(ir_node *node, void *env) {
617 ia32_code_gen_t *cg = env;
618 ia32_transform_env_t tenv;
623 tenv.block = get_nodes_block(node);
624 tenv.dbg = get_irn_dbg_info(node);
625 tenv.irg = current_ir_graph;
628 tenv.mode = get_irn_mode(node);
631 /* be_is_StackParam(node) || */
632 if (be_is_Reload(node)) {
633 transform_to_Load(&tenv);
635 else if (be_is_Spill(node)) {
636 transform_to_Store(&tenv);
641 * We transform StackParam, Spill and Reload here. This needs to be done before
642 * stack biasing otherwise we would miss the corrected offset for these nodes.
644 static void ia32_after_ra(void *self) {
645 ia32_code_gen_t *cg = self;
646 irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
651 * Emits the code, closes the output file and frees
652 * the code generator interface.
654 static void ia32_codegen(void *self) {
655 ia32_code_gen_t *cg = self;
656 ir_graph *irg = cg->irg;
659 if (cg->emit_decls) {
660 ia32_gen_decls(cg->out);
664 ia32_finish_irg(irg, cg);
665 be_dump(irg, "-finished", dump_ir_block_graph_sched);
666 ia32_gen_routine(out, irg, cg);
670 pmap_destroy(cg->tv_ent);
671 pmap_destroy(cg->types);
673 /* de-allocate code generator */
674 del_set(cg->reg_set);
678 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
680 static const arch_code_generator_if_t ia32_code_gen_if = {
682 NULL, /* before abi introduce hook */
684 ia32_before_sched, /* before scheduling hook */
685 ia32_before_ra, /* before register allocation hook */
686 ia32_after_ra, /* after register allocation hook */
687 ia32_codegen /* emit && done */
691 * Initializes the code generator.
693 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
694 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
695 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
697 cg->impl = &ia32_code_gen_if;
699 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
700 cg->mod = firm_dbg_register("firm.be.ia32.cg");
702 cg->arch_env = birg->main_env->arch_env;
703 cg->types = pmap_create();
704 cg->tv_ent = pmap_create();
707 /* set optimizations */
710 cg->opt.placecnst = 1;
715 if (isa->name_obst_size) {
716 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
717 isa->name_obst_size = 0;
718 obstack_free(isa->name_obst, NULL);
719 obstack_init(isa->name_obst);
725 if (isa->num_codegens > 1)
730 cur_reg_set = cg->reg_set;
732 ia32_irn_ops.cg = cg;
734 return (arch_code_generator_t *)cg;
739 /*****************************************************************
740 * ____ _ _ _____ _____
741 * | _ \ | | | | |_ _|/ ____| /\
742 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
743 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
744 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
745 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
747 *****************************************************************/
749 static ia32_isa_t ia32_isa_template = {
750 &ia32_isa_if, /* isa interface implementation */
751 &ia32_gp_regs[REG_ESP], /* stack pointer register */
752 &ia32_gp_regs[REG_EBP], /* base pointer register */
753 -1, /* stack direction */
754 0, /* number of code generator objects so far */
755 NULL, /* 16bit register names */
756 NULL, /* 8bit register names */
758 NULL, /* name obstack */
759 0 /* name obst size */
764 * Initializes the backend ISA.
766 static void *ia32_init(void) {
767 static int inited = 0;
773 isa = xcalloc(1, sizeof(*isa));
774 memcpy(isa, &ia32_isa_template, sizeof(*isa));
776 ia32_register_init(isa);
777 ia32_create_opcodes();
779 isa->regs_16bit = pmap_create();
780 isa->regs_8bit = pmap_create();
782 ia32_build_16bit_reg_map(isa->regs_16bit);
783 ia32_build_8bit_reg_map(isa->regs_8bit);
786 isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
787 obstack_init(isa->name_obst);
788 isa->name_obst_size = 0;
799 * Closes the output file and frees the ISA structure.
801 static void ia32_done(void *self) {
802 ia32_isa_t *isa = self;
804 pmap_destroy(isa->regs_16bit);
805 pmap_destroy(isa->regs_8bit);
808 //printf("name obst size = %d bytes\n", isa->name_obst_size);
809 obstack_free(isa->name_obst, NULL);
817 static int ia32_get_n_reg_class(const void *self) {
821 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
822 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
823 return &ia32_reg_classes[i];
827 * Get the register class which shall be used to store a value of a given mode.
828 * @param self The this pointer.
829 * @param mode The mode in question.
830 * @return A register class which can hold values of the given mode.
832 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
833 if (mode_is_float(mode))
834 return &ia32_reg_classes[CLASS_ia32_fp];
836 return &ia32_reg_classes[CLASS_ia32_gp];
840 * Get the ABI restrictions for procedure calls.
841 * @param self The this pointer.
842 * @param method_type The type of the method (procedure) in question.
843 * @param abi The abi object to be modified
845 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
848 unsigned cc = get_method_calling_convention(method_type);
849 int n = get_method_n_params(method_type);
852 int i, ignore_1, ignore_2;
854 const arch_register_t *reg;
855 be_abi_call_flags_t call_flags;
857 /* set abi flags for calls */
858 call_flags.bits.left_to_right = 0;
859 call_flags.bits.store_args_sequential = 0;
860 call_flags.bits.try_omit_fp = 1;
861 call_flags.bits.fp_free = 0;
862 call_flags.bits.call_has_imm = 1;
864 /* set stack parameter passing style */
865 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
867 /* collect the mode for each type */
868 modes = alloca(n * sizeof(modes[0]));
870 for (i = 0; i < n; i++) {
871 tp = get_method_param_type(method_type, i);
872 modes[i] = get_type_mode(tp);
875 /* set register parameters */
876 if (cc & cc_reg_param) {
877 /* determine the number of parameters passed via registers */
878 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
880 /* loop over all parameters and set the register requirements */
881 for (i = 0; i <= biggest_n; i++) {
882 reg = ia32_get_RegParam_reg(n, modes, i, cc);
883 assert(reg && "kaputt");
884 be_abi_call_param_reg(abi, i, reg);
891 /* set stack parameters */
892 for (i = stack_idx; i < n; i++) {
893 be_abi_call_param_stack(abi, i, 1, 0, 0);
897 /* set return registers */
898 n = get_method_n_ress(method_type);
900 assert(n <= 2 && "more than two results not supported");
902 /* In case of 64bit returns, we will have two 32bit values */
904 tp = get_method_res_type(method_type, 0);
905 mode = get_type_mode(tp);
907 assert(!mode_is_float(mode) && "two FP results not supported");
909 tp = get_method_res_type(method_type, 1);
910 mode = get_type_mode(tp);
912 assert(!mode_is_float(mode) && "two FP results not supported");
914 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
915 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
918 tp = get_method_res_type(method_type, 0);
919 assert(is_atomic_type(tp));
920 mode = get_type_mode(tp);
922 be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
927 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
928 return &ia32_irn_ops;
931 const arch_irn_handler_t ia32_irn_handler = {
935 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
936 return &ia32_irn_handler;
939 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
940 return is_ia32_irn(irn);
944 * Initializes the code generator interface.
946 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
947 return &ia32_code_gen_if;
950 list_sched_selector_t ia32_sched_selector;
953 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
955 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
956 memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
957 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
958 return &ia32_sched_selector;
962 static void ia32_register_options(lc_opt_entry_t *ent)
965 #endif /* WITH_LIBCORE */
967 const arch_isa_if_t ia32_isa_if = {
969 ia32_register_options,
973 ia32_get_n_reg_class,
975 ia32_get_reg_class_for_mode,
977 ia32_get_irn_handler,
978 ia32_get_code_generator_if,
979 ia32_get_list_sched_selector