2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
29 #include "lc_opts_enum.h"
33 #include "pseudo_irg.h"
38 #include "iredges_t.h"
51 #include "iroptimize.h"
52 #include "instrument.h"
57 #include "../benode.h"
58 #include "../belower.h"
59 #include "../besched.h"
62 #include "../beirgmod.h"
63 #include "../be_dbgout.h"
64 #include "../beblocksched.h"
65 #include "../bemachine.h"
66 #include "../beilpsched.h"
67 #include "../bespillslots.h"
68 #include "../bemodule.h"
69 #include "../begnuas.h"
70 #include "../bestate.h"
71 #include "../beflags.h"
72 #include "../betranshlp.h"
73 #include "../belistsched.h"
75 #include "bearch_ia32_t.h"
77 #include "ia32_new_nodes.h"
78 #include "gen_ia32_regalloc_if.h"
79 #include "gen_ia32_machine.h"
80 #include "ia32_common_transform.h"
81 #include "ia32_transform.h"
82 #include "ia32_emitter.h"
83 #include "ia32_map_regs.h"
84 #include "ia32_optimize.h"
86 #include "ia32_dbg_stat.h"
87 #include "ia32_finish.h"
88 #include "ia32_util.h"
90 #include "ia32_architecture.h"
93 #include "ia32_pbqp_transform.h"
95 transformer_t be_transformer = TRANSFORMER_DEFAULT;
98 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
100 ir_mode *mode_fpcw = NULL;
101 ia32_code_gen_t *ia32_current_cg = NULL;
103 /** The current omit-fp state */
104 static unsigned ia32_curr_fp_ommitted = 0;
105 static ir_type *omit_fp_between_type = NULL;
106 static ir_type *between_type = NULL;
107 static ir_entity *old_bp_ent = NULL;
108 static ir_entity *ret_addr_ent = NULL;
109 static ir_entity *omit_fp_ret_addr_ent = NULL;
112 * The environment for the intrinsic mapping.
114 static ia32_intrinsic_env_t intrinsic_env = {
116 NULL, /* the irg, these entities belong to */
117 NULL, /* entity for __divdi3 library call */
118 NULL, /* entity for __moddi3 library call */
119 NULL, /* entity for __udivdi3 library call */
120 NULL, /* entity for __umoddi3 library call */
124 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
127 * Used to create per-graph unique pseudo nodes.
129 static inline ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
130 create_const_node_func func,
131 const arch_register_t* reg)
133 ir_node *block, *res;
138 block = get_irg_start_block(cg->irg);
139 res = func(NULL, block);
140 arch_set_irn_register(res, reg);
146 /* Creates the unique per irg GP NoReg node. */
147 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg)
149 return create_const(cg, &cg->noreg_gp, new_bd_ia32_NoReg_GP,
150 &ia32_gp_regs[REG_GP_NOREG]);
153 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg)
155 return create_const(cg, &cg->noreg_vfp, new_bd_ia32_NoReg_VFP,
156 &ia32_vfp_regs[REG_VFP_NOREG]);
159 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg)
161 return create_const(cg, &cg->noreg_xmm, new_bd_ia32_NoReg_XMM,
162 &ia32_xmm_regs[REG_XMM_NOREG]);
165 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg)
167 return create_const(cg, &cg->unknown_gp, new_bd_ia32_Unknown_GP,
168 &ia32_gp_regs[REG_GP_UKNWN]);
171 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg)
173 return create_const(cg, &cg->unknown_vfp, new_bd_ia32_Unknown_VFP,
174 &ia32_vfp_regs[REG_VFP_UKNWN]);
177 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg)
179 return create_const(cg, &cg->unknown_xmm, new_bd_ia32_Unknown_XMM,
180 &ia32_xmm_regs[REG_XMM_UKNWN]);
183 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg)
185 return create_const(cg, &cg->fpu_trunc_mode, new_bd_ia32_ChangeCW,
186 &ia32_fp_cw_regs[REG_FPCW]);
191 * Returns the admissible noreg register node for input register pos of node irn.
193 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
195 const arch_register_req_t *req = arch_get_register_req(irn, pos);
197 assert(req != NULL && "Missing register requirements");
198 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
199 return ia32_new_NoReg_gp(cg);
201 if (ia32_cg_config.use_sse2) {
202 return ia32_new_NoReg_xmm(cg);
204 return ia32_new_NoReg_vfp(cg);
208 /**************************************************
211 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
212 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
213 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
214 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
217 **************************************************/
219 static const arch_register_req_t *get_ia32_SwitchJmp_out_req(
220 const ir_node *node, int pos)
224 return arch_no_register_req;
227 static arch_irn_class_t ia32_classify(const ir_node *irn)
229 arch_irn_class_t classification = 0;
231 assert(is_ia32_irn(irn));
233 if (is_ia32_is_reload(irn))
234 classification |= arch_irn_class_reload;
236 if (is_ia32_is_spill(irn))
237 classification |= arch_irn_class_spill;
239 if (is_ia32_is_remat(irn))
240 classification |= arch_irn_class_remat;
242 return classification;
246 * The IA32 ABI callback object.
249 be_abi_call_flags_bits_t flags; /**< The call flags. */
250 const arch_env_t *aenv; /**< The architecture environment. */
251 ir_graph *irg; /**< The associated graph. */
254 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
256 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
259 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent)
261 set_ia32_frame_ent(irn, ent);
264 static void ia32_set_frame_offset(ir_node *irn, int bias)
266 if (get_ia32_frame_ent(irn) == NULL)
269 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
270 ia32_code_gen_t *cg = ia32_current_cg;
271 int omit_fp = be_abi_omit_fp(cg->birg->abi);
273 /* Pop nodes modify the stack pointer before calculating the
274 * destination address, so fix this here
279 add_ia32_am_offs_int(irn, bias);
282 static int ia32_get_sp_bias(const ir_node *node)
284 if (is_ia32_Call(node))
285 return -(int)get_ia32_call_attr_const(node)->pop;
287 if (is_ia32_Push(node))
290 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
297 * Generate the routine prologue.
299 * @param self The callback object.
300 * @param mem A pointer to the mem node. Update this if you define new memory.
301 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
302 * @param stack_bias Points to the current stack bias, can be modified if needed.
304 * @return The register which shall be used as a stack frame base.
306 * All nodes which define registers in @p reg_map must keep @p reg_map current.
308 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
310 ia32_abi_env_t *env = self;
311 ia32_code_gen_t *cg = ia32_current_cg;
312 const arch_env_t *arch_env = env->aenv;
314 ia32_curr_fp_ommitted = env->flags.try_omit_fp;
315 if (! env->flags.try_omit_fp) {
316 ir_node *bl = get_irg_start_block(env->irg);
317 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
318 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
319 ir_node *noreg = ia32_new_NoReg_gp(cg);
322 /* mark bp register as ignore */
323 be_set_constr_single_reg_out(get_Proj_pred(curr_bp),
324 get_Proj_proj(curr_bp), arch_env->bp, arch_register_req_type_ignore);
327 push = new_bd_ia32_Push(NULL, bl, noreg, noreg, *mem, curr_bp, curr_sp);
328 curr_sp = new_r_Proj(push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
329 *mem = new_r_Proj(push, mode_M, pn_ia32_Push_M);
331 /* the push must have SP out register */
332 arch_set_irn_register(curr_sp, arch_env->sp);
334 /* this modifies the stack bias, because we pushed 32bit */
337 /* move esp to ebp */
338 curr_bp = be_new_Copy(arch_env->bp->reg_class, bl, curr_sp);
339 be_set_constr_single_reg_out(curr_bp, 0, arch_env->bp,
340 arch_register_req_type_ignore);
342 /* beware: the copy must be done before any other sp use */
343 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
344 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
345 arch_register_req_type_produces_sp);
347 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
348 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
357 * Generate the routine epilogue.
358 * @param self The callback object.
359 * @param bl The block for the epilog
360 * @param mem A pointer to the mem node. Update this if you define new memory.
361 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
362 * @return The register which shall be used as a stack frame base.
364 * All nodes which define registers in @p reg_map must keep @p reg_map current.
366 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
368 ia32_abi_env_t *env = self;
369 const arch_env_t *arch_env = env->aenv;
370 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
371 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
373 if (env->flags.try_omit_fp) {
374 /* simply remove the stack frame here */
375 curr_sp = be_new_IncSP(arch_env->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
377 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
379 if (ia32_cg_config.use_leave) {
383 leave = new_bd_ia32_Leave(NULL, bl, curr_bp);
384 curr_bp = new_r_Proj(leave, mode_bp, pn_ia32_Leave_frame);
385 curr_sp = new_r_Proj(leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
389 /* the old SP is not needed anymore (kill the proj) */
390 assert(is_Proj(curr_sp));
393 /* copy ebp to esp */
394 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], bl, curr_bp);
395 arch_set_irn_register(curr_sp, arch_env->sp);
396 be_set_constr_single_reg_out(curr_sp, 0, arch_env->sp,
397 arch_register_req_type_ignore);
400 pop = new_bd_ia32_PopEbp(NULL, bl, *mem, curr_sp);
401 curr_bp = new_r_Proj(pop, mode_bp, pn_ia32_Pop_res);
402 curr_sp = new_r_Proj(pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
404 *mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
406 arch_set_irn_register(curr_sp, arch_env->sp);
407 arch_set_irn_register(curr_bp, arch_env->bp);
410 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
411 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
415 * Initialize the callback object.
416 * @param call The call object.
417 * @param aenv The architecture environment.
418 * @param irg The graph with the method.
419 * @return Some pointer. This pointer is passed to all other callback functions as self object.
421 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
423 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
424 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
425 env->flags = fl.bits;
432 * Destroy the callback object.
433 * @param self The callback object.
435 static void ia32_abi_done(void *self)
441 * Build the between type and entities if not already build.
443 static void ia32_build_between_type(void)
445 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
446 if (! between_type) {
447 ir_type *old_bp_type = new_type_primitive(mode_Iu);
448 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
450 between_type = new_type_struct(IDENT("ia32_between_type"));
451 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
452 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
454 set_entity_offset(old_bp_ent, 0);
455 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
456 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
457 set_type_state(between_type, layout_fixed);
459 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
460 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
462 set_entity_offset(omit_fp_ret_addr_ent, 0);
463 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
464 set_type_state(omit_fp_between_type, layout_fixed);
470 * Produces the type which sits between the stack args and the locals on the stack.
471 * it will contain the return address and space to store the old base pointer.
472 * @return The Firm type modeling the ABI between type.
474 static ir_type *ia32_abi_get_between_type(void *self)
476 ia32_abi_env_t *env = self;
478 ia32_build_between_type();
479 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
483 * Return the stack entity that contains the return address.
485 ir_entity *ia32_get_return_address_entity(void)
487 ia32_build_between_type();
488 return ia32_curr_fp_ommitted ? omit_fp_ret_addr_ent : ret_addr_ent;
492 * Return the stack entity that contains the frame address.
494 ir_entity *ia32_get_frame_address_entity(void)
496 ia32_build_between_type();
497 return ia32_curr_fp_ommitted ? NULL : old_bp_ent;
501 * Get the estimated cycle count for @p irn.
503 * @param self The this pointer.
504 * @param irn The node.
506 * @return The estimated cycle count for this operation
508 static int ia32_get_op_estimated_cost(const ir_node *irn)
511 ia32_op_type_t op_tp;
515 if (!is_ia32_irn(irn))
518 assert(is_ia32_irn(irn));
520 cost = get_ia32_latency(irn);
521 op_tp = get_ia32_op_type(irn);
523 if (is_ia32_CopyB(irn)) {
526 else if (is_ia32_CopyB_i(irn)) {
527 int size = get_ia32_copyb_size(irn);
528 cost = 20 + (int)ceil((4/3) * size);
530 /* in case of address mode operations add additional cycles */
531 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
533 In case of stack access and access to fixed addresses add 5 cycles
534 (we assume they are in cache), other memory operations cost 20
537 if (is_ia32_use_frame(irn) || (
538 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
539 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
551 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
553 * @param irn The original operation
554 * @param i Index of the argument we want the inverse operation to yield
555 * @param inverse struct to be filled with the resulting inverse op
556 * @param obstack The obstack to use for allocation of the returned nodes array
557 * @return The inverse operation or NULL if operation invertible
559 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst)
570 ir_node *block, *noreg, *nomem;
573 /* we cannot invert non-ia32 irns */
574 if (! is_ia32_irn(irn))
577 /* operand must always be a real operand (not base, index or mem) */
578 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
581 /* we don't invert address mode operations */
582 if (get_ia32_op_type(irn) != ia32_Normal)
585 /* TODO: adjust for new immediates... */
586 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
590 block = get_nodes_block(irn);
591 mode = get_irn_mode(irn);
592 irn_mode = get_irn_mode(irn);
593 noreg = get_irn_n(irn, 0);
595 dbg = get_irn_dbg_info(irn);
597 /* initialize structure */
598 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
602 switch (get_ia32_irn_opcode(irn)) {
605 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
606 /* we have an add with a const here */
607 /* invers == add with negated const */
608 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
610 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
611 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
612 set_ia32_commutative(inverse->nodes[0]);
614 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
615 /* we have an add with a symconst here */
616 /* invers == sub with const */
617 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
619 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
622 /* normal add: inverse == sub */
623 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
630 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
631 /* we have a sub with a const/symconst here */
632 /* invers == add with this const */
633 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
634 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
635 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
639 if (i == n_ia32_binary_left) {
640 inverse->nodes[0] = new_bd_ia32_Add(dbg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
643 inverse->nodes[0] = new_bd_ia32_Sub(dbg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
651 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
652 /* xor with const: inverse = xor */
653 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
654 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
655 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
659 inverse->nodes[0] = new_bd_ia32_Xor(dbg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
665 inverse->nodes[0] = new_bd_ia32_Not(dbg, block, (ir_node*) irn);
670 inverse->nodes[0] = new_bd_ia32_Neg(dbg, block, (ir_node*) irn);
675 /* inverse operation not supported */
683 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
685 if (mode_is_float(mode))
692 * Get the mode that should be used for spilling value node
694 static ir_mode *get_spill_mode(const ir_node *node)
696 ir_mode *mode = get_irn_mode(node);
697 return get_spill_mode_mode(mode);
701 * Checks whether an addressmode reload for a node with mode mode is compatible
702 * with a spillslot of mode spill_mode
704 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
706 return !mode_is_float(mode) || mode == spillmode;
710 * Check if irn can load its operand at position i from memory (source addressmode).
711 * @param irn The irn to be checked
712 * @param i The operands position
713 * @return Non-Zero if operand can be loaded
715 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
717 ir_node *op = get_irn_n(irn, i);
718 const ir_mode *mode = get_irn_mode(op);
719 const ir_mode *spillmode = get_spill_mode(op);
721 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
722 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
723 !ia32_is_spillmode_compatible(mode, spillmode) ||
724 is_ia32_use_frame(irn)) /* must not already use frame */
727 switch (get_ia32_am_support(irn)) {
732 if (i != n_ia32_unary_op)
738 case n_ia32_binary_left: {
739 const arch_register_req_t *req;
740 if (!is_ia32_commutative(irn))
743 /* we can't swap left/right for limited registers
744 * (As this (currently) breaks constraint handling copies)
746 req = get_ia32_in_req(irn, n_ia32_binary_left);
747 if (req->type & arch_register_req_type_limited)
752 case n_ia32_binary_right:
761 panic("Unknown AM type");
764 /* HACK: must not already use "real" memory.
765 * This can happen for Call and Div */
766 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
772 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
776 ir_mode *dest_op_mode;
778 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
780 set_ia32_op_type(irn, ia32_AddrModeS);
782 load_mode = get_irn_mode(get_irn_n(irn, i));
783 dest_op_mode = get_ia32_ls_mode(irn);
784 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
785 set_ia32_ls_mode(irn, load_mode);
787 set_ia32_use_frame(irn);
788 set_ia32_need_stackent(irn);
790 if (i == n_ia32_binary_left &&
791 get_ia32_am_support(irn) == ia32_am_binary &&
792 /* immediates are only allowed on the right side */
793 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
794 ia32_swap_left_right(irn);
795 i = n_ia32_binary_right;
798 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
800 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
801 set_irn_n(irn, n_ia32_mem, spill);
802 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
803 set_ia32_is_reload(irn);
806 static const be_abi_callbacks_t ia32_abi_callbacks = {
809 ia32_abi_get_between_type,
814 /* register allocator interface */
815 static const arch_irn_ops_t ia32_irn_ops = {
818 ia32_get_frame_entity,
819 ia32_set_frame_entity,
820 ia32_set_frame_offset,
823 ia32_get_op_estimated_cost,
824 ia32_possible_memory_operand,
825 ia32_perform_memory_operand,
828 /* special register allocator interface for SwitchJmp
829 as it possibly has a WIDE range of Proj numbers.
830 We don't want to allocate output for register constraints for
832 static const arch_irn_ops_t ia32_SwitchJmp_irn_ops = {
833 /* Note: we also use SwitchJmp_out_req for the inputs too:
834 This is because the bearch API has a conceptual problem at the moment.
835 Querying for negative proj numbers which can happen for switchs
836 isn't possible and will result in inputs getting queried */
837 get_ia32_SwitchJmp_out_req,
839 ia32_get_frame_entity,
840 ia32_set_frame_entity,
841 ia32_set_frame_offset,
844 ia32_get_op_estimated_cost,
845 ia32_possible_memory_operand,
846 ia32_perform_memory_operand,
849 /**************************************************
852 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
853 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
854 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
855 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
858 **************************************************/
860 static ir_entity *mcount = NULL;
862 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
864 static void ia32_before_abi(void *self)
866 lower_mode_b_config_t lower_mode_b_config = {
867 mode_Iu, /* lowered mode */
868 mode_Bu, /* preferred mode for set */
869 0, /* don't lower direct compares */
871 ia32_code_gen_t *cg = self;
873 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
875 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
878 if (mcount == NULL) {
879 ir_type *tp = new_type_method(0, 0);
880 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
881 /* FIXME: enter the right ld_ident here */
882 set_entity_ld_ident(mcount, get_entity_ident(mcount));
883 set_entity_visibility(mcount, ir_visibility_external);
885 instrument_initcall(cg->irg, mcount);
890 * Transforms the standard firm graph into
893 static void ia32_prepare_graph(void *self)
895 ia32_code_gen_t *cg = self;
897 switch (be_transformer) {
898 case TRANSFORMER_DEFAULT:
899 /* transform remaining nodes into assembler instructions */
900 ia32_transform_graph(cg);
904 case TRANSFORMER_PBQP:
905 case TRANSFORMER_RAND:
906 /* transform nodes into assembler instructions by PBQP magic */
907 ia32_transform_graph_by_pbqp(cg);
912 panic("invalid transformer");
915 /* do local optimizations (mainly CSE) */
916 optimize_graph_df(cg->irg);
919 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
921 /* optimize address mode */
922 ia32_optimize_graph(cg);
924 /* do code placement, to optimize the position of constants */
928 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
931 ir_node *turn_back_am(ir_node *node)
933 dbg_info *dbgi = get_irn_dbg_info(node);
934 ir_node *block = get_nodes_block(node);
935 ir_node *base = get_irn_n(node, n_ia32_base);
936 ir_node *index = get_irn_n(node, n_ia32_index);
937 ir_node *mem = get_irn_n(node, n_ia32_mem);
940 ir_node *load = new_bd_ia32_Load(dbgi, block, base, index, mem);
941 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
943 ia32_copy_am_attrs(load, node);
944 if (is_ia32_is_reload(node))
945 set_ia32_is_reload(load);
946 set_irn_n(node, n_ia32_mem, new_NoMem());
948 switch (get_ia32_am_support(node)) {
950 set_irn_n(node, n_ia32_unary_op, load_res);
954 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
955 set_irn_n(node, n_ia32_binary_left, load_res);
957 set_irn_n(node, n_ia32_binary_right, load_res);
962 panic("Unknown AM type");
964 noreg = ia32_new_NoReg_gp(ia32_current_cg);
965 set_irn_n(node, n_ia32_base, noreg);
966 set_irn_n(node, n_ia32_index, noreg);
967 set_ia32_am_offs_int(node, 0);
968 set_ia32_am_sc(node, NULL);
969 set_ia32_am_scale(node, 0);
970 clear_ia32_am_sc_sign(node);
972 /* rewire mem-proj */
973 if (get_irn_mode(node) == mode_T) {
974 const ir_edge_t *edge;
975 foreach_out_edge(node, edge) {
976 ir_node *out = get_edge_src_irn(edge);
977 if (get_irn_mode(out) == mode_M) {
978 set_Proj_pred(out, load);
979 set_Proj_proj(out, pn_ia32_Load_M);
985 set_ia32_op_type(node, ia32_Normal);
986 if (sched_is_scheduled(node))
987 sched_add_before(node, load);
992 static ir_node *flags_remat(ir_node *node, ir_node *after)
994 /* we should turn back source address mode when rematerializing nodes */
999 if (is_Block(after)) {
1002 block = get_nodes_block(after);
1005 type = get_ia32_op_type(node);
1007 case ia32_AddrModeS:
1011 case ia32_AddrModeD:
1012 /* TODO implement this later... */
1013 panic("found DestAM with flag user %+F this should not happen", node);
1016 default: assert(type == ia32_Normal); break;
1019 copy = exact_copy(node);
1020 set_nodes_block(copy, block);
1021 sched_add_after(after, copy);
1027 * Called before the register allocator.
1029 static void ia32_before_ra(void *self)
1031 ia32_code_gen_t *cg = self;
1033 /* setup fpu rounding modes */
1034 ia32_setup_fpu_mode(cg);
1037 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1040 ia32_add_missing_keeps(cg);
1045 * Transforms a be_Reload into a ia32 Load.
1047 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node)
1049 ir_graph *irg = get_irn_irg(node);
1050 dbg_info *dbg = get_irn_dbg_info(node);
1051 ir_node *block = get_nodes_block(node);
1052 ir_entity *ent = be_get_frame_entity(node);
1053 ir_mode *mode = get_irn_mode(node);
1054 ir_mode *spillmode = get_spill_mode(node);
1055 ir_node *noreg = ia32_new_NoReg_gp(cg);
1056 ir_node *sched_point = NULL;
1057 ir_node *ptr = get_irg_frame(irg);
1058 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1059 ir_node *new_op, *proj;
1060 const arch_register_t *reg;
1062 if (sched_is_scheduled(node)) {
1063 sched_point = sched_prev(node);
1066 if (mode_is_float(spillmode)) {
1067 if (ia32_cg_config.use_sse2)
1068 new_op = new_bd_ia32_xLoad(dbg, block, ptr, noreg, mem, spillmode);
1070 new_op = new_bd_ia32_vfld(dbg, block, ptr, noreg, mem, spillmode);
1072 else if (get_mode_size_bits(spillmode) == 128) {
1073 /* Reload 128 bit SSE registers */
1074 new_op = new_bd_ia32_xxLoad(dbg, block, ptr, noreg, mem);
1077 new_op = new_bd_ia32_Load(dbg, block, ptr, noreg, mem);
1079 set_ia32_op_type(new_op, ia32_AddrModeS);
1080 set_ia32_ls_mode(new_op, spillmode);
1081 set_ia32_frame_ent(new_op, ent);
1082 set_ia32_use_frame(new_op);
1083 set_ia32_is_reload(new_op);
1085 DBG_OPT_RELOAD2LD(node, new_op);
1087 proj = new_rd_Proj(dbg, new_op, mode, pn_ia32_Load_res);
1090 sched_add_after(sched_point, new_op);
1094 /* copy the register from the old node to the new Load */
1095 reg = arch_get_irn_register(node);
1096 arch_set_irn_register(proj, reg);
1098 SET_IA32_ORIG_NODE(new_op, node);
1100 exchange(node, proj);
1104 * Transforms a be_Spill node into a ia32 Store.
1106 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node)
1108 ir_graph *irg = get_irn_irg(node);
1109 dbg_info *dbg = get_irn_dbg_info(node);
1110 ir_node *block = get_nodes_block(node);
1111 ir_entity *ent = be_get_frame_entity(node);
1112 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1113 ir_mode *mode = get_spill_mode(spillval);
1114 ir_node *noreg = ia32_new_NoReg_gp(cg);
1115 ir_node *nomem = new_NoMem();
1116 ir_node *ptr = get_irg_frame(irg);
1117 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1119 ir_node *sched_point = NULL;
1121 if (sched_is_scheduled(node)) {
1122 sched_point = sched_prev(node);
1125 /* No need to spill unknown values... */
1126 if (is_ia32_Unknown_GP(val) ||
1127 is_ia32_Unknown_VFP(val) ||
1128 is_ia32_Unknown_XMM(val)) {
1133 exchange(node, store);
1137 if (mode_is_float(mode)) {
1138 if (ia32_cg_config.use_sse2)
1139 store = new_bd_ia32_xStore(dbg, block, ptr, noreg, nomem, val);
1141 store = new_bd_ia32_vfst(dbg, block, ptr, noreg, nomem, val, mode);
1142 } else if (get_mode_size_bits(mode) == 128) {
1143 /* Spill 128 bit SSE registers */
1144 store = new_bd_ia32_xxStore(dbg, block, ptr, noreg, nomem, val);
1145 } else if (get_mode_size_bits(mode) == 8) {
1146 store = new_bd_ia32_Store8Bit(dbg, block, ptr, noreg, nomem, val);
1148 store = new_bd_ia32_Store(dbg, block, ptr, noreg, nomem, val);
1151 set_ia32_op_type(store, ia32_AddrModeD);
1152 set_ia32_ls_mode(store, mode);
1153 set_ia32_frame_ent(store, ent);
1154 set_ia32_use_frame(store);
1155 set_ia32_is_spill(store);
1156 SET_IA32_ORIG_NODE(store, node);
1157 DBG_OPT_SPILL2ST(node, store);
1160 sched_add_after(sched_point, store);
1164 exchange(node, store);
1167 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
1169 dbg_info *dbg = get_irn_dbg_info(node);
1170 ir_node *block = get_nodes_block(node);
1171 ir_node *noreg = ia32_new_NoReg_gp(cg);
1172 ir_graph *irg = get_irn_irg(node);
1173 ir_node *frame = get_irg_frame(irg);
1175 ir_node *push = new_bd_ia32_Push(dbg, block, frame, noreg, mem, noreg, sp);
1177 set_ia32_frame_ent(push, ent);
1178 set_ia32_use_frame(push);
1179 set_ia32_op_type(push, ia32_AddrModeS);
1180 set_ia32_ls_mode(push, mode_Is);
1181 set_ia32_is_spill(push);
1183 sched_add_before(schedpoint, push);
1187 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
1189 dbg_info *dbg = get_irn_dbg_info(node);
1190 ir_node *block = get_nodes_block(node);
1191 ir_node *noreg = ia32_new_NoReg_gp(cg);
1192 ir_graph *irg = get_irn_irg(node);
1193 ir_node *frame = get_irg_frame(irg);
1195 ir_node *pop = new_bd_ia32_PopMem(dbg, block, frame, noreg, new_NoMem(), sp);
1197 set_ia32_frame_ent(pop, ent);
1198 set_ia32_use_frame(pop);
1199 set_ia32_op_type(pop, ia32_AddrModeD);
1200 set_ia32_ls_mode(pop, mode_Is);
1201 set_ia32_is_reload(pop);
1203 sched_add_before(schedpoint, pop);
1208 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1210 dbg_info *dbg = get_irn_dbg_info(node);
1211 ir_mode *spmode = mode_Iu;
1212 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1215 sp = new_rd_Proj(dbg, pred, spmode, pos);
1216 arch_set_irn_register(sp, spreg);
1222 * Transform MemPerm, currently we do this the ugly way and produce
1223 * push/pop into/from memory cascades. This is possible without using
1226 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node)
1228 ir_node *block = get_nodes_block(node);
1229 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1230 int arity = be_get_MemPerm_entity_arity(node);
1231 ir_node **pops = ALLOCAN(ir_node*, arity);
1235 const ir_edge_t *edge;
1236 const ir_edge_t *next;
1239 for (i = 0; i < arity; ++i) {
1240 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1241 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1242 ir_type *enttype = get_entity_type(inent);
1243 unsigned entsize = get_type_size_bytes(enttype);
1244 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1245 ir_node *mem = get_irn_n(node, i + 1);
1248 /* work around cases where entities have different sizes */
1249 if (entsize2 < entsize)
1251 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1253 push = create_push(cg, node, node, sp, mem, inent);
1254 sp = create_spproj(node, push, pn_ia32_Push_stack);
1256 /* add another push after the first one */
1257 push = create_push(cg, node, node, sp, mem, inent);
1258 add_ia32_am_offs_int(push, 4);
1259 sp = create_spproj(node, push, pn_ia32_Push_stack);
1262 set_irn_n(node, i, new_Bad());
1266 for (i = arity - 1; i >= 0; --i) {
1267 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1268 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1269 ir_type *enttype = get_entity_type(outent);
1270 unsigned entsize = get_type_size_bytes(enttype);
1271 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1274 /* work around cases where entities have different sizes */
1275 if (entsize2 < entsize)
1277 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1279 pop = create_pop(cg, node, node, sp, outent);
1280 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1282 add_ia32_am_offs_int(pop, 4);
1284 /* add another pop after the first one */
1285 pop = create_pop(cg, node, node, sp, outent);
1286 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1293 keep = be_new_Keep(block, 1, in);
1294 sched_add_before(node, keep);
1296 /* exchange memprojs */
1297 foreach_out_edge_safe(node, edge, next) {
1298 ir_node *proj = get_edge_src_irn(edge);
1299 int p = get_Proj_proj(proj);
1303 set_Proj_pred(proj, pops[p]);
1304 set_Proj_proj(proj, pn_ia32_Pop_M);
1307 /* remove memperm */
1308 arity = get_irn_arity(node);
1309 for (i = 0; i < arity; ++i) {
1310 set_irn_n(node, i, new_Bad());
1316 * Block-Walker: Calls the transform functions Spill and Reload.
1318 static void ia32_after_ra_walker(ir_node *block, void *env)
1320 ir_node *node, *prev;
1321 ia32_code_gen_t *cg = env;
1323 /* beware: the schedule is changed here */
1324 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1325 prev = sched_prev(node);
1327 if (be_is_Reload(node)) {
1328 transform_to_Load(cg, node);
1329 } else if (be_is_Spill(node)) {
1330 transform_to_Store(cg, node);
1331 } else if (be_is_MemPerm(node)) {
1332 transform_MemPerm(cg, node);
1338 * Collects nodes that need frame entities assigned.
1340 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1342 be_fec_env_t *env = data;
1343 const ir_mode *mode;
1346 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1347 mode = get_spill_mode_mode(get_irn_mode(node));
1348 align = get_mode_size_bytes(mode);
1349 } else if (is_ia32_irn(node) &&
1350 get_ia32_frame_ent(node) == NULL &&
1351 is_ia32_use_frame(node)) {
1352 if (is_ia32_need_stackent(node))
1355 switch (get_ia32_irn_opcode(node)) {
1357 case iro_ia32_Load: {
1358 const ia32_attr_t *attr = get_ia32_attr_const(node);
1360 if (attr->data.need_32bit_stackent) {
1362 } else if (attr->data.need_64bit_stackent) {
1365 mode = get_ia32_ls_mode(node);
1366 if (is_ia32_is_reload(node))
1367 mode = get_spill_mode_mode(mode);
1369 align = get_mode_size_bytes(mode);
1373 case iro_ia32_vfild:
1375 case iro_ia32_xLoad: {
1376 mode = get_ia32_ls_mode(node);
1381 case iro_ia32_FldCW: {
1382 /* although 2 byte would be enough 4 byte performs best */
1390 panic("unexpected frame user while collection frame entity nodes");
1392 case iro_ia32_FnstCW:
1393 case iro_ia32_Store8Bit:
1394 case iro_ia32_Store:
1397 case iro_ia32_vfist:
1398 case iro_ia32_vfisttp:
1400 case iro_ia32_xStore:
1401 case iro_ia32_xStoreSimple:
1408 be_node_needs_frame_entity(env, node, mode, align);
1412 * We transform Spill and Reload here. This needs to be done before
1413 * stack biasing otherwise we would miss the corrected offset for these nodes.
1415 static void ia32_after_ra(void *self)
1417 ia32_code_gen_t *cg = self;
1418 ir_graph *irg = cg->irg;
1419 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1421 /* create and coalesce frame entities */
1422 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1423 be_assign_entities(fec_env);
1424 be_free_frame_entity_coalescer(fec_env);
1426 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1430 * Last touchups for the graph before emit: x87 simulation to replace the
1431 * virtual with real x87 instructions, creating a block schedule and peephole
1434 static void ia32_finish(void *self)
1436 ia32_code_gen_t *cg = self;
1437 ir_graph *irg = cg->irg;
1439 ia32_finish_irg(irg, cg);
1441 /* we might have to rewrite x87 virtual registers */
1442 if (cg->do_x87_sim) {
1443 x87_simulate_graph(cg->birg);
1446 /* do peephole optimisations */
1447 ia32_peephole_optimization(cg);
1449 /* create block schedule, this also removes empty blocks which might
1450 * produce critical edges */
1451 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1455 * Emits the code, closes the output file and frees
1456 * the code generator interface.
1458 static void ia32_codegen(void *self)
1460 ia32_code_gen_t *cg = self;
1461 ir_graph *irg = cg->irg;
1463 if (ia32_cg_config.emit_machcode) {
1464 ia32_gen_binary_routine(cg, irg);
1466 ia32_gen_routine(cg, irg);
1469 /* remove it from the isa */
1472 assert(ia32_current_cg == cg);
1473 ia32_current_cg = NULL;
1475 /* de-allocate code generator */
1480 * Returns the node representing the PIC base.
1482 static ir_node *ia32_get_pic_base(void *self)
1485 ia32_code_gen_t *cg = self;
1486 ir_node *get_eip = cg->get_eip;
1487 if (get_eip != NULL)
1490 block = get_irg_start_block(cg->irg);
1491 get_eip = new_bd_ia32_GetEIP(NULL, block);
1492 cg->get_eip = get_eip;
1494 be_dep_on_frame(get_eip);
1498 static void *ia32_cg_init(be_irg_t *birg);
1500 static const arch_code_generator_if_t ia32_code_gen_if = {
1502 ia32_get_pic_base, /* return node used as base in pic code addresses */
1503 ia32_before_abi, /* before abi introduce hook */
1506 ia32_before_ra, /* before register allocation hook */
1507 ia32_after_ra, /* after register allocation hook */
1508 ia32_finish, /* called before codegen */
1509 ia32_codegen /* emit && done */
1513 * Initializes a IA32 code generator.
1515 static void *ia32_cg_init(be_irg_t *birg)
1517 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1518 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1520 cg->impl = &ia32_code_gen_if;
1521 cg->irg = birg->irg;
1524 cg->blk_sched = NULL;
1525 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1526 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1529 /* Linux gprof implementation needs base pointer */
1530 birg->main_env->options->omit_fp = 0;
1537 if (isa->name_obst) {
1538 obstack_free(isa->name_obst, NULL);
1539 obstack_init(isa->name_obst);
1543 assert(ia32_current_cg == NULL);
1544 ia32_current_cg = cg;
1546 return (arch_code_generator_t *)cg;
1551 /*****************************************************************
1552 * ____ _ _ _____ _____
1553 * | _ \ | | | | |_ _|/ ____| /\
1554 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1555 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1556 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1557 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1559 *****************************************************************/
1562 * Set output modes for GCC
1564 static const tarval_mode_info mo_integer = {
1571 * set the tarval output mode of all integer modes to decimal
1573 static void set_tarval_output_modes(void)
1577 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1578 ir_mode *mode = get_irp_mode(i);
1580 if (mode_is_int(mode))
1581 set_tarval_mode_output_option(mode, &mo_integer);
1585 const arch_isa_if_t ia32_isa_if;
1588 * The template that generates a new ISA object.
1589 * Note that this template can be changed by command line
1592 static ia32_isa_t ia32_isa_template = {
1594 &ia32_isa_if, /* isa interface implementation */
1595 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1596 &ia32_gp_regs[REG_EBP], /* base pointer register */
1597 &ia32_reg_classes[CLASS_ia32_gp], /* static link pointer register class */
1598 -1, /* stack direction */
1599 2, /* power of two stack alignment, 2^2 == 4 */
1600 NULL, /* main environment */
1601 7, /* costs for a spill instruction */
1602 5, /* costs for a reload instruction */
1604 NULL, /* 16bit register names */
1605 NULL, /* 8bit register names */
1606 NULL, /* 8bit register names high */
1609 NULL, /* current code generator */
1610 NULL, /* abstract machine */
1612 NULL, /* name obstack */
1616 static void init_asm_constraints(void)
1618 be_init_default_asm_constraint_flags();
1620 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1621 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1622 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1623 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1624 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1625 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1626 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1627 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1628 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1629 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1630 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1631 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1632 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1633 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1634 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1635 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1636 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1637 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1638 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1639 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1641 /* no support for autodecrement/autoincrement */
1642 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1643 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1644 /* no float consts */
1645 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1646 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1647 /* makes no sense on x86 */
1648 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1649 /* no support for sse consts yet */
1650 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1651 /* no support for x87 consts yet */
1652 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1653 /* no support for mmx registers yet */
1654 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1655 /* not available in 32bit mode */
1656 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1657 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1659 /* no code yet to determine register class needed... */
1660 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1664 * Initializes the backend ISA.
1666 static arch_env_t *ia32_init(FILE *file_handle)
1668 static int inited = 0;
1676 set_tarval_output_modes();
1678 isa = XMALLOC(ia32_isa_t);
1679 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1681 if (mode_fpcw == NULL) {
1682 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1685 ia32_register_init();
1686 ia32_create_opcodes(&ia32_irn_ops);
1687 /* special handling for SwitchJmp */
1688 op_ia32_SwitchJmp->ops.be_ops = &ia32_SwitchJmp_irn_ops;
1690 be_emit_init(file_handle);
1691 isa->regs_16bit = pmap_create();
1692 isa->regs_8bit = pmap_create();
1693 isa->regs_8bit_high = pmap_create();
1694 isa->types = pmap_create();
1695 isa->tv_ent = pmap_create();
1696 isa->cpu = ia32_init_machine_description();
1698 ia32_build_16bit_reg_map(isa->regs_16bit);
1699 ia32_build_8bit_reg_map(isa->regs_8bit);
1700 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1703 isa->name_obst = XMALLOC(struct obstack);
1704 obstack_init(isa->name_obst);
1707 /* enter the ISA object into the intrinsic environment */
1708 intrinsic_env.isa = isa;
1710 /* emit asm includes */
1711 n = get_irp_n_asms();
1712 for (i = 0; i < n; ++i) {
1713 be_emit_cstring("#APP\n");
1714 be_emit_ident(get_irp_asm(i));
1715 be_emit_cstring("\n#NO_APP\n");
1718 /* needed for the debug support */
1719 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1720 be_emit_irprintf("%stext0:\n", be_gas_get_private_prefix());
1721 be_emit_write_line();
1723 return &isa->arch_env;
1729 * Closes the output file and frees the ISA structure.
1731 static void ia32_done(void *self)
1733 ia32_isa_t *isa = self;
1735 /* emit now all global declarations */
1736 be_gas_emit_decls(isa->arch_env.main_env);
1738 pmap_destroy(isa->regs_16bit);
1739 pmap_destroy(isa->regs_8bit);
1740 pmap_destroy(isa->regs_8bit_high);
1741 pmap_destroy(isa->tv_ent);
1742 pmap_destroy(isa->types);
1745 obstack_free(isa->name_obst, NULL);
1755 * Return the number of register classes for this architecture.
1756 * We report always these:
1757 * - the general purpose registers
1758 * - the SSE floating point register set
1759 * - the virtual floating point registers
1760 * - the SSE vector register set
1762 static unsigned ia32_get_n_reg_class(void)
1768 * Return the register class for index i.
1770 static const arch_register_class_t *ia32_get_reg_class(unsigned i)
1772 assert(i < N_CLASSES);
1773 return &ia32_reg_classes[i];
1777 * Get the register class which shall be used to store a value of a given mode.
1778 * @param self The this pointer.
1779 * @param mode The mode in question.
1780 * @return A register class which can hold values of the given mode.
1782 static const arch_register_class_t *ia32_get_reg_class_for_mode(const ir_mode *mode)
1784 if (mode_is_float(mode)) {
1785 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1788 return &ia32_reg_classes[CLASS_ia32_gp];
1792 * Returns the register for parameter nr.
1794 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1795 const ir_mode *mode)
1797 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1798 &ia32_gp_regs[REG_ECX],
1799 &ia32_gp_regs[REG_EDX],
1802 static const unsigned MAXNUM_GPREG_ARGS = 3;
1804 static const arch_register_t *gpreg_param_reg_regparam[] = {
1805 &ia32_gp_regs[REG_EAX],
1806 &ia32_gp_regs[REG_EDX],
1807 &ia32_gp_regs[REG_ECX]
1810 static const arch_register_t *gpreg_param_reg_this[] = {
1811 &ia32_gp_regs[REG_ECX],
1816 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1817 &ia32_xmm_regs[REG_XMM0],
1818 &ia32_xmm_regs[REG_XMM1],
1819 &ia32_xmm_regs[REG_XMM2],
1820 &ia32_xmm_regs[REG_XMM3],
1821 &ia32_xmm_regs[REG_XMM4],
1822 &ia32_xmm_regs[REG_XMM5],
1823 &ia32_xmm_regs[REG_XMM6],
1824 &ia32_xmm_regs[REG_XMM7]
1827 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1828 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1830 static const unsigned MAXNUM_SSE_ARGS = 8;
1832 if ((cc & cc_this_call) && nr == 0)
1833 return gpreg_param_reg_this[0];
1835 if (! (cc & cc_reg_param))
1838 if (mode_is_float(mode)) {
1839 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1841 if (nr >= MAXNUM_SSE_ARGS)
1844 if (cc & cc_this_call) {
1845 return fpreg_sse_param_reg_this[nr];
1847 return fpreg_sse_param_reg_std[nr];
1848 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1849 unsigned num_regparam;
1851 if (get_mode_size_bits(mode) > 32)
1854 if (nr >= MAXNUM_GPREG_ARGS)
1857 if (cc & cc_this_call) {
1858 return gpreg_param_reg_this[nr];
1860 num_regparam = cc & ~cc_bits;
1861 if (num_regparam == 0) {
1862 /* default fastcall */
1863 return gpreg_param_reg_fastcall[nr];
1865 if (nr < num_regparam)
1866 return gpreg_param_reg_regparam[nr];
1870 panic("unknown argument mode");
1874 * Get the ABI restrictions for procedure calls.
1875 * @param self The this pointer.
1876 * @param method_type The type of the method (procedure) in question.
1877 * @param abi The abi object to be modified
1879 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1887 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1891 /* set abi flags for calls */
1892 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1893 call_flags.bits.store_args_sequential = 0;
1894 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1895 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1896 call_flags.bits.call_has_imm = 0; /* No call immediate, we handle this by ourselves */
1898 /* set parameter passing style */
1899 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1901 cc = get_method_calling_convention(method_type);
1902 if (get_method_variadicity(method_type) == variadicity_variadic) {
1903 /* pass all parameters of a variadic function on the stack */
1904 cc = cc_cdecl_set | (cc & cc_this_call);
1906 if (get_method_additional_properties(method_type) & mtp_property_private &&
1907 ia32_cg_config.optimize_cc) {
1908 /* set the fast calling conventions (allowing up to 3) */
1909 cc = SET_FASTCALL(cc) | 3;
1913 /* we have to pop the shadow parameter ourself for compound calls */
1914 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1915 && !(cc & cc_reg_param)) {
1916 pop_amount += get_mode_size_bytes(mode_P_data);
1919 n = get_method_n_params(method_type);
1920 for (i = regnum = 0; i < n; i++) {
1922 const arch_register_t *reg = NULL;
1924 tp = get_method_param_type(method_type, i);
1925 mode = get_type_mode(tp);
1927 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1930 be_abi_call_param_reg(abi, i, reg);
1933 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1934 * movl has a shorter opcode than mov[sz][bw]l */
1935 ir_mode *load_mode = mode;
1938 unsigned size = get_mode_size_bytes(mode);
1940 if (cc & cc_callee_clear_stk) {
1941 pop_amount += (size + 3U) & ~3U;
1944 if (size < 4) load_mode = mode_Iu;
1947 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1951 be_abi_call_set_pop(abi, pop_amount);
1953 /* set return registers */
1954 n = get_method_n_ress(method_type);
1956 assert(n <= 2 && "more than two results not supported");
1958 /* In case of 64bit returns, we will have two 32bit values */
1960 tp = get_method_res_type(method_type, 0);
1961 mode = get_type_mode(tp);
1963 assert(!mode_is_float(mode) && "two FP results not supported");
1965 tp = get_method_res_type(method_type, 1);
1966 mode = get_type_mode(tp);
1968 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1970 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1971 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1974 const arch_register_t *reg;
1976 tp = get_method_res_type(method_type, 0);
1977 assert(is_atomic_type(tp));
1978 mode = get_type_mode(tp);
1980 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1982 be_abi_call_res_reg(abi, 0, reg);
1986 static int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1990 if (!is_ia32_irn(irn)) {
1994 if (is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1995 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1996 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1997 || is_ia32_Immediate(irn))
2004 * Initializes the code generator interface.
2006 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
2009 return &ia32_code_gen_if;
2013 * Returns the estimated execution time of an ia32 irn.
2015 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn)
2018 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
2021 list_sched_selector_t ia32_sched_selector;
2024 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
2026 static const list_sched_selector_t *ia32_get_list_sched_selector(
2027 const void *self, list_sched_selector_t *selector)
2030 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
2031 ia32_sched_selector.exectime = ia32_sched_exectime;
2032 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
2033 return &ia32_sched_selector;
2036 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
2043 * Returns the necessary byte alignment for storing a register of given class.
2045 static int ia32_get_reg_class_alignment(const arch_register_class_t *cls)
2047 ir_mode *mode = arch_register_class_mode(cls);
2048 int bytes = get_mode_size_bytes(mode);
2050 if (mode_is_float(mode) && bytes > 8)
2055 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
2058 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
2059 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
2060 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2063 static const be_execution_unit_t *_allowed_units_GP[] = {
2064 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2065 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2066 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2067 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2068 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2069 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2070 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2073 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2074 &be_machine_execution_units_DUMMY[0],
2077 static const be_execution_unit_t **_units_callret[] = {
2078 _allowed_units_BRANCH,
2081 static const be_execution_unit_t **_units_other[] = {
2085 static const be_execution_unit_t **_units_dummy[] = {
2086 _allowed_units_DUMMY,
2089 const be_execution_unit_t ***ret;
2091 if (is_ia32_irn(irn)) {
2092 ret = get_ia32_exec_units(irn);
2093 } else if (is_be_node(irn)) {
2094 if (be_is_Return(irn)) {
2095 ret = _units_callret;
2096 } else if (be_is_Barrier(irn)) {
2110 * Return the abstract ia32 machine.
2112 static const be_machine_t *ia32_get_machine(const void *self)
2114 const ia32_isa_t *isa = self;
2119 * Return irp irgs in the desired order.
2121 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2128 static void ia32_mark_remat(ir_node *node)
2130 if (is_ia32_irn(node)) {
2131 set_ia32_is_remat(node);
2136 * Check if Mux(sel, t, f) would represent an Abs (or -Abs).
2138 static bool mux_is_abs(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2147 cmp = get_Proj_pred(sel);
2151 /* must be <, <=, >=, > */
2152 pnc = get_Proj_proj(sel);
2167 if (!is_negated_value(mux_true, mux_false))
2170 /* must be x cmp 0 */
2171 cmp_right = get_Cmp_right(cmp);
2172 if (!is_Const(cmp_right) || !is_Const_null(cmp_right))
2175 cmp_left = get_Cmp_left(cmp);
2176 if (cmp_left != mux_true && cmp_left != mux_false)
2183 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
2185 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
2195 cmp = get_Proj_pred(sel);
2199 cmp_l = get_Cmp_left(cmp);
2200 cmp_r = get_Cmp_right(cmp);
2201 if (!mode_is_float(get_irn_mode(cmp_l)))
2204 /* check for min/max. They're defined as (C-Semantik):
2205 * min(a, b) = a < b ? a : b
2206 * or min(a, b) = a <= b ? a : b
2207 * max(a, b) = a > b ? a : b
2208 * or max(a, b) = a >= b ? a : b
2209 * (Note we only handle float min/max here)
2211 pnc = get_Proj_proj(sel);
2216 if (cmp_l == mux_true && cmp_r == mux_false)
2222 if (cmp_l == mux_true && cmp_r == mux_false)
2228 if (cmp_l == mux_false && cmp_r == mux_true)
2234 if (cmp_l == mux_false && cmp_r == mux_true)
2245 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2247 ir_mode *mode = get_irn_mode(mux_true);
2250 if (!mode_is_int(mode) && !mode_is_reference(mode)
2254 if (is_Const(mux_true) && is_Const(mux_false)) {
2255 /* we can create a set plus up two 3 instructions for any combination of constants */
2262 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
2267 if (!mode_is_float(get_irn_mode(mux_true)))
2270 return is_Const(mux_true) && is_Const(mux_false);
2273 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
2284 cmp = get_Proj_pred(sel);
2288 mode = get_irn_mode(mux_true);
2289 if (mode_is_signed(mode) || mode_is_float(mode))
2292 pn = get_Proj_proj(sel);
2293 cmp_left = get_Cmp_left(cmp);
2294 cmp_right = get_Cmp_right(cmp);
2295 if ((pn & pn_Cmp_Gt) &&
2296 is_Const(mux_false) && is_Const_null(mux_false) && is_Sub(mux_true) &&
2297 get_Sub_left(mux_true) == cmp_left &&
2298 get_Sub_right(mux_true) == cmp_right) {
2299 /* Mux(a >=u b, a - b, 0) unsigned Doz */
2302 if ((pn & pn_Cmp_Lt) &&
2303 is_Const(mux_true) && is_Const_null(mux_true) && is_Sub(mux_false) &&
2304 get_Sub_left(mux_false) == cmp_left &&
2305 get_Sub_right(mux_false) == cmp_right) {
2306 /* Mux(a <=u b, 0, a - b) unsigned Doz */
2313 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
2318 /* we can handle Abs for all modes and compares */
2319 if (mux_is_abs(sel, mux_true, mux_false))
2321 /* we can handle Set for all modes and compares */
2322 if (mux_is_set(sel, mux_true, mux_false))
2324 /* SSE has own min/max operations */
2325 if (ia32_cg_config.use_sse2
2326 && mux_is_float_min_max(sel, mux_true, mux_false))
2328 /* we can handle Mux(?, Const[f], Const[f]) */
2329 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
2330 #ifdef FIRM_GRGEN_BE
2331 /* well, some code selectors can't handle it */
2332 if (be_transformer != TRANSFORMER_PBQP
2333 || be_transformer != TRANSFORMER_RAND)
2340 /* no support for 64bit inputs to cmov */
2341 mode = get_irn_mode(mux_true);
2342 if (get_mode_size_bits(mode) > 32)
2344 /* we can't handle MuxF yet */
2345 if (mode_is_float(mode))
2348 if (mux_is_doz(sel, mux_true, mux_false))
2351 /* Check Cmp before the node */
2353 ir_node *cmp = get_Proj_pred(sel);
2355 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(cmp));
2357 /* we can't handle 64bit compares */
2358 if (get_mode_size_bits(cmp_mode) > 32)
2361 /* we can't handle float compares */
2362 if (mode_is_float(cmp_mode))
2367 /* did we disable cmov generation? */
2368 if (!ia32_cg_config.use_cmov)
2371 /* we can use a cmov */
2375 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
2379 /* we already added all our simple flags to the flags modifier list in
2380 * init, so this flag we don't know. */
2381 return ASM_CONSTRAINT_FLAG_INVALID;
2384 static int ia32_is_valid_clobber(const char *clobber)
2386 return ia32_get_clobber_register(clobber) != NULL;
2390 * Create the trampoline code.
2392 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
2394 ir_node *st, *p = trampoline;
2395 ir_mode *mode = get_irn_mode(p);
2398 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xb9), 0);
2399 mem = new_r_Proj(st, mode_M, pn_Store_M);
2400 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2401 st = new_r_Store(block, mem, p, env, 0);
2402 mem = new_r_Proj(st, mode_M, pn_Store_M);
2403 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2405 st = new_r_Store(block, mem, p, new_Const_long(mode_Bu, 0xe9), 0);
2406 mem = new_r_Proj(st, mode_M, pn_Store_M);
2407 p = new_r_Add(block, p, new_Const_long(mode_Iu, 1), mode);
2408 st = new_r_Store(block, mem, p, callee, 0);
2409 mem = new_r_Proj(st, mode_M, pn_Store_M);
2410 p = new_r_Add(block, p, new_Const_long(mode_Iu, 4), mode);
2416 * Returns the libFirm configuration parameter for this backend.
2418 static const backend_params *ia32_get_libfirm_params(void)
2420 static const ir_settings_if_conv_t ifconv = {
2421 4, /* maxdepth, doesn't matter for Mux-conversion */
2422 ia32_is_mux_allowed /* allows or disallows Mux creation for given selector */
2424 static const ir_settings_arch_dep_t ad = {
2425 1, /* also use subs */
2426 4, /* maximum shifts */
2427 31, /* maximum shift amount */
2428 ia32_evaluate_insn, /* evaluate the instruction sequence */
2430 1, /* allow Mulhs */
2431 1, /* allow Mulus */
2432 32, /* Mulh allowed up to 32 bit */
2434 static backend_params p = {
2435 1, /* need dword lowering */
2436 1, /* support inline assembly */
2437 NULL, /* will be set later */
2438 ia32_create_intrinsic_fkt,
2439 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2440 NULL, /* ifconv info will be set below */
2441 NULL, /* float arithmetic mode, will be set below */
2442 12, /* size of trampoline code */
2443 4, /* alignment of trampoline code */
2444 ia32_create_trampoline_fkt,
2445 4 /* alignment of stack parameter */
2448 ia32_setup_cg_config();
2450 /* doesn't really belong here, but this is the earliest place the backend
2452 init_asm_constraints();
2455 p.if_conv_info = &ifconv;
2456 if (! ia32_cg_config.use_sse2)
2457 p.mode_float_arithmetic = mode_E;
2461 static const lc_opt_enum_int_items_t gas_items[] = {
2462 { "elf", OBJECT_FILE_FORMAT_ELF },
2463 { "mingw", OBJECT_FILE_FORMAT_COFF },
2464 { "macho", OBJECT_FILE_FORMAT_MACH_O },
2468 static lc_opt_enum_int_var_t gas_var = {
2469 (int*) &be_gas_object_file_format, gas_items
2472 #ifdef FIRM_GRGEN_BE
2473 static const lc_opt_enum_int_items_t transformer_items[] = {
2474 { "default", TRANSFORMER_DEFAULT },
2475 { "pbqp", TRANSFORMER_PBQP },
2476 { "random", TRANSFORMER_RAND },
2480 static lc_opt_enum_int_var_t transformer_var = {
2481 (int*)&be_transformer, transformer_items
2485 static const lc_opt_table_entry_t ia32_options[] = {
2486 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2487 #ifdef FIRM_GRGEN_BE
2488 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2490 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2491 &ia32_isa_template.arch_env.stack_alignment),
2495 const arch_isa_if_t ia32_isa_if = {
2498 ia32_handle_intrinsics,
2499 ia32_get_n_reg_class,
2501 ia32_get_reg_class_for_mode,
2503 ia32_get_code_generator_if,
2504 ia32_get_list_sched_selector,
2505 ia32_get_ilp_sched_selector,
2506 ia32_get_reg_class_alignment,
2507 ia32_get_libfirm_params,
2508 ia32_get_allowed_execution_units,
2512 ia32_parse_asm_constraint,
2513 ia32_is_valid_clobber
2516 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);
2517 void be_init_arch_ia32(void)
2519 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2520 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2522 lc_opt_add_table(ia32_grp, ia32_options);
2523 be_register_isa_if("ia32", &ia32_isa_if);
2525 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2527 ia32_init_emitter();
2529 ia32_init_optimize();
2530 ia32_init_transform();
2532 ia32_init_architecture();