2 * This is the main ia32 firm backend driver.
17 #include "pseudo_irg.h"
21 #include "iredges_t.h"
29 #include "../beabi.h" /* the general register allocator interface */
30 #include "../benode_t.h"
31 #include "../belower.h"
32 #include "../besched_t.h"
34 #include "bearch_ia32_t.h"
36 #include "ia32_new_nodes.h" /* ia32 nodes interface */
37 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
38 #include "ia32_gen_decls.h" /* interface declaration emitter */
39 #include "ia32_transform.h"
40 #include "ia32_emitter.h"
41 #include "ia32_map_regs.h"
42 #include "ia32_optimize.h"
44 #define DEBUG_MODULE "firm.be.ia32.isa"
47 static set *cur_reg_set = NULL;
50 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
52 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
53 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
56 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
57 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
60 /**************************************************
63 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
64 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
65 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
66 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
69 **************************************************/
71 static ir_node *my_skip_proj(const ir_node *n) {
78 * Return register requirements for an ia32 node.
79 * If the node returns a tuple (mode_T) then the proj's
80 * will be asked for this information.
82 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
83 const ia32_register_req_t *irn_req;
84 long node_pos = pos == -1 ? 0 : pos;
85 ir_mode *mode = get_irn_mode(irn);
86 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
88 if (mode == mode_T || mode == mode_M) {
89 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
93 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
98 node_pos = ia32_translate_proj_pos(irn);
104 irn = my_skip_proj(irn);
106 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
109 if (is_ia32_irn(irn)) {
111 irn_req = get_ia32_in_req(irn, pos);
114 irn_req = get_ia32_out_req(irn, node_pos);
117 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
119 memcpy(req, &(irn_req->req), sizeof(*req));
121 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
122 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
123 req->other_same = get_irn_n(irn, irn_req->same_pos);
126 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
127 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
128 req->other_different = get_irn_n(irn, irn_req->different_pos);
132 /* treat Phi like Const with default requirements */
134 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
135 if (mode_is_float(mode))
136 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
137 else if (mode_is_int(mode) || mode_is_reference(mode))
138 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
139 else if (mode == mode_T || mode == mode_M) {
140 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
144 assert(0 && "unsupported Phi-Mode");
147 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
155 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
157 const ia32_irn_ops_t *ops = self;
159 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
162 pos = ia32_translate_proj_pos(irn);
163 irn = my_skip_proj(irn);
166 if (is_ia32_irn(irn)) {
167 const arch_register_t **slots;
169 slots = get_ia32_slots(irn);
173 ia32_set_firm_reg(irn, reg, cur_reg_set);
177 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
179 const arch_register_t *reg = NULL;
182 pos = ia32_translate_proj_pos(irn);
183 irn = my_skip_proj(irn);
186 if (is_ia32_irn(irn)) {
187 const arch_register_t **slots;
188 slots = get_ia32_slots(irn);
192 reg = ia32_get_firm_reg(irn, cur_reg_set);
198 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
199 irn = my_skip_proj(irn);
201 return arch_irn_class_branch;
202 else if (is_ia32_irn(irn))
203 return arch_irn_class_normal;
208 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
209 irn = my_skip_proj(irn);
210 if (is_ia32_irn(irn))
211 return get_ia32_flags(irn);
217 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
218 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
221 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
223 const ia32_irn_ops_t *ops = self;
225 if (is_ia32_use_frame(irn) && bias != 0) {
226 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
228 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
229 snprintf(buf, sizeof(buf), "%d", bias);
230 add_ia32_am_offs(irn, buf);
232 set_ia32_am_flavour(irn, am_flav);
236 /* fill register allocator interface */
238 static const arch_irn_ops_if_t ia32_irn_ops_if = {
239 ia32_get_irn_reg_req,
244 ia32_get_frame_entity,
248 ia32_irn_ops_t ia32_irn_ops = {
255 /**************************************************
258 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
259 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
260 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
261 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
264 **************************************************/
267 * Transforms the standard firm graph into
270 static void ia32_prepare_graph(void *self) {
271 ia32_code_gen_t *cg = self;
272 firm_dbg_module_t *old_mod = cg->mod;
274 cg->mod = firm_dbg_register("firm.be.ia32.transform");
275 irg_walk_blkwise_graph(cg->irg, ia32_place_consts_set_modes, ia32_transform_node, cg);
276 dump_ir_block_graph_sched(cg->irg, "-transformed");
278 edges_deactivate(cg->irg);
279 dead_node_elimination(cg->irg);
280 edges_activate(cg->irg);
285 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
286 dump_ir_block_graph_sched(cg->irg, "-am");
292 * Insert copies for all ia32 nodes where the should_be_same requirement
294 * Transform Sub into Neg -- Add if IN2 == OUT
296 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
297 ia32_code_gen_t *cg = env;
298 const ia32_register_req_t **reqs;
299 const arch_register_t *out_reg, *in_reg;
301 ir_node *copy, *in_node, *block;
303 if (! is_ia32_irn(irn))
306 /* nodes with destination address mode don't produce values */
307 if (get_ia32_op_type(irn) == ia32_AddrModeD)
310 reqs = get_ia32_out_req_all(irn);
311 n_res = get_ia32_n_res(irn);
312 block = get_nodes_block(irn);
314 /* check all OUT requirements, if there is a should_be_same */
315 for (i = 0; i < n_res; i++) {
316 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
317 /* get in and out register */
318 out_reg = get_ia32_out_reg(irn, i);
319 in_node = get_irn_n(irn, reqs[i]->same_pos);
320 in_reg = arch_get_irn_register(cg->arch_env, in_node);
322 /* check if in and out register are equal */
323 if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
324 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
326 /* create copy from in register */
327 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
329 /* destination is the out register */
330 arch_set_irn_register(cg->arch_env, copy, out_reg);
332 /* insert copy before the node into the schedule */
333 sched_add_before(irn, copy);
336 set_irn_n(irn, reqs[i]->same_pos, copy);
341 /* check if there is a sub which need to be transformed */
342 ia32_transform_sub_to_neg_add(irn, cg);
346 * Add Copy nodes for not fulfilled should_be_equal constraints
348 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
349 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
355 * Dummy functions for hooks we don't need but which must be filled.
357 static void ia32_before_sched(void *self) {
360 static void ia32_before_ra(void *self) {
366 * Transforms a be node into a Load.
368 static void transform_to_Load(ia32_transform_env_t *env) {
369 ir_node *irn = env->irn;
370 entity *ent = be_get_frame_entity(irn);
371 ir_mode *mode = env->mode;
372 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
373 ir_node *nomem = new_rd_NoMem(env->irg);
374 ir_node *sched_point = NULL;
375 ir_node *ptr = get_irn_n(irn, 0);
376 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
377 ir_node *new_op, *proj;
378 const arch_register_t *reg;
380 if (sched_is_scheduled(irn)) {
381 sched_point = sched_prev(irn);
384 if (mode_is_float(mode)) {
385 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
388 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
391 set_ia32_am_support(new_op, ia32_am_Source);
392 set_ia32_op_type(new_op, ia32_AddrModeS);
393 set_ia32_am_flavour(new_op, ia32_B);
394 set_ia32_ls_mode(new_op, mode);
395 set_ia32_frame_ent(new_op, ent);
396 set_ia32_use_frame(new_op);
398 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
401 sched_add_after(sched_point, new_op);
402 sched_add_after(new_op, proj);
407 /* copy the register from the old node to the new Load */
408 reg = arch_get_irn_register(env->cg->arch_env, irn);
409 arch_set_irn_register(env->cg->arch_env, new_op, reg);
416 * Transforms a be node into a Store.
418 static void transform_to_Store(ia32_transform_env_t *env) {
419 ir_node *irn = env->irn;
420 entity *ent = be_get_frame_entity(irn);
421 ir_mode *mode = env->mode;
422 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
423 ir_node *nomem = new_rd_NoMem(env->irg);
424 ir_node *ptr = get_irn_n(irn, 0);
425 ir_node *val = get_irn_n(irn, 1);
426 ir_node *new_op, *proj;
427 ir_node *sched_point = NULL;
429 if (sched_is_scheduled(irn)) {
430 sched_point = sched_prev(irn);
433 if (mode_is_float(mode)) {
434 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
437 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
440 set_ia32_am_support(new_op, ia32_am_Dest);
441 set_ia32_op_type(new_op, ia32_AddrModeD);
442 set_ia32_am_flavour(new_op, ia32_B);
443 set_ia32_ls_mode(new_op, get_irn_mode(val));
444 set_ia32_frame_ent(new_op, ent);
445 set_ia32_use_frame(new_op);
447 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
450 sched_add_after(sched_point, new_op);
451 sched_add_after(new_op, proj);
461 * Calls the transform functions for StackParam, Spill and Reload.
463 static void ia32_after_ra_walker(ir_node *node, void *env) {
464 ia32_code_gen_t *cg = env;
465 ia32_transform_env_t tenv;
470 tenv.block = get_nodes_block(node);
471 tenv.dbg = get_irn_dbg_info(node);
472 tenv.irg = current_ir_graph;
475 tenv.mode = get_irn_mode(node);
478 /* be_is_StackParam(node) || */
479 if (be_is_Reload(node)) {
480 transform_to_Load(&tenv);
482 else if (be_is_Spill(node)) {
483 transform_to_Store(&tenv);
488 * We transform StackParam, Spill and Reload here. This needs to be done before
489 * stack biasing otherwise we would miss the corrected offset for these nodes.
491 static void ia32_after_ra(void *self) {
492 ia32_code_gen_t *cg = self;
493 irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
498 * Emits the code, closes the output file and frees
499 * the code generator interface.
501 static void ia32_codegen(void *self) {
502 ia32_code_gen_t *cg = self;
503 ir_graph *irg = cg->irg;
506 if (cg->emit_decls) {
507 ia32_gen_decls(cg->out);
511 ia32_finish_irg(irg, cg);
512 dump_ir_block_graph_sched(irg, "-finished");
513 ia32_gen_routine(out, irg, cg);
517 pmap_destroy(cg->tv_ent);
518 pmap_destroy(cg->types);
520 /* de-allocate code generator */
521 del_set(cg->reg_set);
525 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
527 static const arch_code_generator_if_t ia32_code_gen_if = {
529 NULL, /* before abi introduce hook */
531 ia32_before_sched, /* before scheduling hook */
532 ia32_before_ra, /* before register allocation hook */
533 ia32_after_ra, /* after register allocation hook */
534 ia32_codegen /* emit && done */
538 * Initializes the code generator.
540 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
541 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
542 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
544 cg->impl = &ia32_code_gen_if;
546 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
547 cg->mod = firm_dbg_register("firm.be.ia32.cg");
549 cg->arch_env = birg->main_env->arch_env;
550 cg->types = pmap_create();
551 cg->tv_ent = pmap_create();
554 /* set optimizations */
557 cg->opt.placecnst = 1;
561 if (isa->name_obst_size) {
562 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
563 isa->name_obst_size = 0;
564 obstack_free(isa->name_obst, NULL);
565 obstack_init(isa->name_obst);
571 if (isa->num_codegens > 1)
576 cur_reg_set = cg->reg_set;
578 ia32_irn_ops.cg = cg;
580 return (arch_code_generator_t *)cg;
585 /*****************************************************************
586 * ____ _ _ _____ _____
587 * | _ \ | | | | |_ _|/ ____| /\
588 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
589 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
590 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
591 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
593 *****************************************************************/
595 static ia32_isa_t ia32_isa_template = {
596 &ia32_isa_if, /* isa interface implementation */
597 &ia32_gp_regs[REG_ESP], /* stack pointer register */
598 &ia32_gp_regs[REG_EBP], /* base pointer register */
599 -1, /* stack direction */
600 0, /* number of code generator objects so far */
601 NULL /* name obstack */
605 * Initializes the backend ISA.
607 static void *ia32_init(void) {
608 static int inited = 0;
614 isa = xcalloc(1, sizeof(*isa));
615 memcpy(isa, &ia32_isa_template, sizeof(*isa));
617 ia32_register_init(isa);
618 ia32_create_opcodes();
621 isa->name_obst = xcalloc(1, sizeof(*(isa->name_obst)));
622 obstack_init(isa->name_obst);
623 isa->name_obst_size = 0;
634 * Closes the output file and frees the ISA structure.
636 static void ia32_done(void *self) {
637 ia32_isa_t *isa = self;
640 //printf("name obst size = %d bytes\n", isa->name_obst_size);
641 obstack_free(isa->name_obst, NULL);
649 static int ia32_get_n_reg_class(const void *self) {
653 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
654 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
655 return &ia32_reg_classes[i];
659 * Get the register class which shall be used to store a value of a given mode.
660 * @param self The this pointer.
661 * @param mode The mode in question.
662 * @return A register class which can hold values of the given mode.
664 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
665 if (mode_is_float(mode))
666 return &ia32_reg_classes[CLASS_ia32_fp];
668 return &ia32_reg_classes[CLASS_ia32_gp];
672 * Produces the type which sits between the stack args and the locals on the stack.
673 * it will contain the return address and space to store the old base pointer.
674 * @return The Firm type modeling the ABI between type.
676 static ir_type *get_between_type(void)
678 static ir_type *between_type = NULL;
679 static entity *old_bp_ent = NULL;
682 entity *ret_addr_ent;
683 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
684 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
686 between_type = new_type_class(new_id_from_str("ia32_between_type"));
687 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
688 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
690 set_entity_offset_bytes(old_bp_ent, 0);
691 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
692 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
699 * Get the ABI restrictions for procedure calls.
700 * @param self The this pointer.
701 * @param method_type The type of the method (procedure) in question.
702 * @param abi The abi object to be modified
704 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
705 ir_type *between_type;
708 unsigned cc = get_method_calling_convention(method_type);
709 int n = get_method_n_params(method_type);
714 const arch_register_t *reg;
715 be_abi_call_flags_t call_flags;
717 /* set abi flags for calls */
718 call_flags.bits.left_to_right = 0;
719 call_flags.bits.store_args_sequential = 0;
720 call_flags.bits.try_omit_fp = 1;
721 call_flags.bits.fp_free = 0;
722 call_flags.bits.call_has_imm = 1;
724 /* get the between type and the frame pointer save entity */
725 between_type = get_between_type();
727 /* set stack parameter passing style */
728 be_abi_call_set_flags(abi, call_flags, between_type);
730 /* collect the mode for each type */
731 modes = alloca(n * sizeof(modes[0]));
733 for (i = 0; i < n; i++) {
734 tp = get_method_param_type(method_type, i);
735 modes[i] = get_type_mode(tp);
738 /* set register parameters */
739 if (cc & cc_reg_param) {
740 /* determine the number of parameters passed via registers */
741 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore, &ignore);
743 /* loop over all parameters and set the register requirements */
744 for (i = 0; i <= biggest_n; i++) {
745 reg = ia32_get_RegParam_reg(n, modes, i, cc);
746 assert(reg && "kaputt");
747 be_abi_call_param_reg(abi, i, reg);
754 /* set stack parameters */
755 for (i = stack_idx; i < n; i++) {
756 be_abi_call_param_stack(abi, i);
760 /* set return registers */
761 n = get_method_n_ress(method_type);
763 assert(n <= 2 && "more than two results not supported");
765 /* In case of 64bit returns, we will have two 32bit values */
767 tp = get_method_res_type(method_type, 0);
768 mode = get_type_mode(tp);
770 assert(!mode_is_float(mode) && "two FP results not supported");
772 tp = get_method_res_type(method_type, 1);
773 mode = get_type_mode(tp);
775 assert(!mode_is_float(mode) && "two FP results not supported");
777 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
778 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
781 tp = get_method_res_type(method_type, 0);
782 assert(is_atomic_type(tp));
783 mode = get_type_mode(tp);
785 be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
790 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
791 return &ia32_irn_ops;
794 const arch_irn_handler_t ia32_irn_handler = {
798 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
799 return &ia32_irn_handler;
802 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
803 return is_ia32_irn(irn);
807 * Initializes the code generator interface.
809 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
810 return &ia32_code_gen_if;
813 list_sched_selector_t ia32_sched_selector;
816 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
818 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
819 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
820 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
821 return &ia32_sched_selector;
825 static void ia32_register_options(lc_opt_entry_t *ent)
828 #endif /* WITH_LIBCORE */
830 const arch_isa_if_t ia32_isa_if = {
832 ia32_register_options,
836 ia32_get_n_reg_class,
838 ia32_get_reg_class_for_mode,
840 ia32_get_irn_handler,
841 ia32_get_code_generator_if,
842 ia32_get_list_sched_selector