2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
31 #include "lc_opts_enum.h"
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
53 #include "iroptimize.h"
54 #include "instrument.h"
57 #include "../beirg_t.h"
58 #include "../benode_t.h"
59 #include "../belower.h"
60 #include "../besched_t.h"
63 #include "../beirgmod.h"
64 #include "../be_dbgout.h"
65 #include "../beblocksched.h"
66 #include "../bemachine.h"
67 #include "../beilpsched.h"
68 #include "../bespillslots.h"
69 #include "../bemodule.h"
70 #include "../begnuas.h"
71 #include "../bestate.h"
72 #include "../beflags.h"
73 #include "../betranshlp.h"
75 #include "bearch_ia32_t.h"
77 #include "ia32_new_nodes.h"
78 #include "gen_ia32_regalloc_if.h"
79 #include "gen_ia32_machine.h"
80 #include "ia32_common_transform.h"
81 #include "ia32_transform.h"
82 #include "ia32_emitter.h"
83 #include "ia32_map_regs.h"
84 #include "ia32_optimize.h"
86 #include "ia32_dbg_stat.h"
87 #include "ia32_finish.h"
88 #include "ia32_util.h"
90 #include "ia32_architecture.h"
93 #include "ia32_pbqp_transform.h"
96 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
99 static set *cur_reg_set = NULL;
101 ir_mode *mode_fpcw = NULL;
102 ia32_code_gen_t *ia32_current_cg = NULL;
105 * The environment for the intrinsic mapping.
107 static ia32_intrinsic_env_t intrinsic_env = {
109 NULL, /* the irg, these entities belong to */
110 NULL, /* entity for first div operand (move into FPU) */
111 NULL, /* entity for second div operand (move into FPU) */
112 NULL, /* entity for converts ll -> d */
113 NULL, /* entity for converts d -> ll */
114 NULL, /* entity for __divdi3 library call */
115 NULL, /* entity for __moddi3 library call */
116 NULL, /* entity for __udivdi3 library call */
117 NULL, /* entity for __umoddi3 library call */
118 NULL, /* bias value for conversion from float to unsigned 64 */
122 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
124 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
125 create_const_node_func func,
126 const arch_register_t* reg)
128 ir_node *block, *res;
133 block = get_irg_start_block(cg->irg);
134 res = func(NULL, cg->irg, block);
135 arch_set_irn_register(res, reg);
138 add_irn_dep(get_irg_end(cg->irg), res);
139 /* add_irn_dep(get_irg_start(cg->irg), res); */
144 /* Creates the unique per irg GP NoReg node. */
145 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
146 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
147 &ia32_gp_regs[REG_GP_NOREG]);
150 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
151 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
152 &ia32_vfp_regs[REG_VFP_NOREG]);
155 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
156 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
157 &ia32_xmm_regs[REG_XMM_NOREG]);
160 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
161 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
162 &ia32_gp_regs[REG_GP_UKNWN]);
165 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
166 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
167 &ia32_vfp_regs[REG_VFP_UKNWN]);
170 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
171 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
172 &ia32_xmm_regs[REG_XMM_UKNWN]);
175 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
176 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
177 &ia32_fp_cw_regs[REG_FPCW]);
182 * Returns the admissible noreg register node for input register pos of node irn.
184 static ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos)
186 const arch_register_req_t *req = arch_get_register_req(irn, pos);
188 assert(req != NULL && "Missing register requirements");
189 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
190 return ia32_new_NoReg_gp(cg);
192 if (ia32_cg_config.use_sse2) {
193 return ia32_new_NoReg_xmm(cg);
195 return ia32_new_NoReg_vfp(cg);
199 /**************************************************
202 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
203 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
204 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
205 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
208 **************************************************/
211 * Return register requirements for an ia32 node.
212 * If the node returns a tuple (mode_T) then the proj's
213 * will be asked for this information.
215 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
218 ir_mode *mode = get_irn_mode(node);
221 if (mode == mode_X || is_Block(node)) {
222 return arch_no_register_req;
225 if (mode == mode_T && pos < 0) {
226 return arch_no_register_req;
229 node_pos = pos == -1 ? 0 : pos;
231 if (mode == mode_M || pos >= 0) {
232 return arch_no_register_req;
235 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
236 node = skip_Proj_const(node);
239 if (is_ia32_irn(node)) {
240 const arch_register_req_t *req;
242 req = get_ia32_in_req(node, pos);
244 req = get_ia32_out_req(node, node_pos);
251 /* unknowns should be transformed already */
252 assert(!is_Unknown(node));
253 return arch_no_register_req;
256 static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
260 if (get_irn_mode(irn) == mode_X) {
265 pos = get_Proj_proj(irn);
266 irn = skip_Proj(irn);
269 if (is_ia32_irn(irn)) {
270 const arch_register_t **slots;
272 slots = get_ia32_slots(irn);
275 ia32_set_firm_reg(irn, reg, cur_reg_set);
279 static const arch_register_t *ia32_get_irn_reg(const ir_node *irn)
284 if (get_irn_mode(irn) == mode_X) {
288 pos = get_Proj_proj(irn);
289 irn = skip_Proj_const(irn);
292 if (is_ia32_irn(irn)) {
293 const arch_register_t **slots = get_ia32_slots(irn);
294 assert(pos < get_ia32_n_res(irn));
297 return ia32_get_firm_reg(irn, cur_reg_set);
301 static arch_irn_class_t ia32_classify(const ir_node *irn) {
302 arch_irn_class_t classification = arch_irn_class_normal;
304 irn = skip_Proj_const(irn);
307 classification |= arch_irn_class_branch;
309 if (! is_ia32_irn(irn))
310 return classification & ~arch_irn_class_normal;
313 classification |= arch_irn_class_load;
316 classification |= arch_irn_class_store;
318 if (is_ia32_is_reload(irn))
319 classification |= arch_irn_class_reload;
321 if (is_ia32_is_spill(irn))
322 classification |= arch_irn_class_spill;
324 if (is_ia32_is_remat(irn))
325 classification |= arch_irn_class_remat;
327 return classification;
330 static arch_irn_flags_t ia32_get_flags(const ir_node *irn) {
331 arch_irn_flags_t flags = arch_irn_flags_none;
334 return arch_irn_flags_ignore;
336 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
337 ir_node *pred = get_Proj_pred(irn);
339 if(is_ia32_irn(pred)) {
340 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
346 if (is_ia32_irn(irn)) {
347 flags |= get_ia32_flags(irn);
354 * The IA32 ABI callback object.
357 be_abi_call_flags_bits_t flags; /**< The call flags. */
358 const arch_env_t *aenv; /**< The architecture environment. */
359 ir_graph *irg; /**< The associated graph. */
362 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
363 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
366 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
367 set_ia32_frame_ent(irn, ent);
370 static void ia32_set_frame_offset(ir_node *irn, int bias)
372 if (get_ia32_frame_ent(irn) == NULL)
375 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
376 ia32_code_gen_t *cg = ia32_current_cg;
377 int omit_fp = be_abi_omit_fp(cg->birg->abi);
379 /* Pop nodes modify the stack pointer before calculating the
380 * destination address, so fix this here
385 add_ia32_am_offs_int(irn, bias);
388 static int ia32_get_sp_bias(const ir_node *node)
390 if (is_ia32_Call(node))
391 return -(int)get_ia32_call_attr_const(node)->pop;
393 if (is_ia32_Push(node))
396 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
403 * Put all registers which are saved by the prologue/epilogue in a set.
405 * @param self The callback object.
406 * @param s The result set.
408 static void ia32_abi_dont_save_regs(void *self, pset *s)
410 ia32_abi_env_t *env = self;
411 if(env->flags.try_omit_fp)
412 pset_insert_ptr(s, env->aenv->bp);
416 * Generate the routine prologue.
418 * @param self The callback object.
419 * @param mem A pointer to the mem node. Update this if you define new memory.
420 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
421 * @param stack_bias Points to the current stack bias, can be modified if needed.
423 * @return The register which shall be used as a stack frame base.
425 * All nodes which define registers in @p reg_map must keep @p reg_map current.
427 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map, int *stack_bias)
429 ia32_abi_env_t *env = self;
430 ia32_code_gen_t *cg = ia32_current_cg;
431 const arch_env_t *arch_env = env->aenv;
433 if (! env->flags.try_omit_fp) {
434 ir_graph *irg =env->irg;
435 ir_node *bl = get_irg_start_block(irg);
436 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
437 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
438 ir_node *noreg = ia32_new_NoReg_gp(cg);
441 /* ALL nodes representing bp must be set to ignore. */
442 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
445 push = new_rd_ia32_Push(NULL, irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
446 curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
447 *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
449 /* the push must have SP out register */
450 arch_set_irn_register(curr_sp, arch_env->sp);
451 set_ia32_flags(push, arch_irn_flags_ignore);
453 /* this modifies the stack bias, because we pushed 32bit */
456 /* move esp to ebp */
457 curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
458 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
459 arch_set_irn_register(curr_bp, arch_env->bp);
460 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
462 /* beware: the copy must be done before any other sp use */
463 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
464 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp);
465 arch_set_irn_register(curr_sp, arch_env->sp);
466 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
468 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
469 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
478 * Generate the routine epilogue.
479 * @param self The callback object.
480 * @param bl The block for the epilog
481 * @param mem A pointer to the mem node. Update this if you define new memory.
482 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
483 * @return The register which shall be used as a stack frame base.
485 * All nodes which define registers in @p reg_map must keep @p reg_map current.
487 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
489 ia32_abi_env_t *env = self;
490 const arch_env_t *arch_env = env->aenv;
491 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
492 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
493 ir_graph *irg = env->irg;
495 if (env->flags.try_omit_fp) {
496 /* simply remove the stack frame here */
497 curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
499 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
501 if (ia32_cg_config.use_leave) {
505 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_bp);
506 set_ia32_flags(leave, arch_irn_flags_ignore);
507 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
508 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
512 /* the old SP is not needed anymore (kill the proj) */
513 assert(is_Proj(curr_sp));
516 /* copy ebp to esp */
517 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
518 arch_set_irn_register(curr_sp, arch_env->sp);
519 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
522 pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
523 set_ia32_flags(pop, arch_irn_flags_ignore);
524 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
525 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
527 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
529 arch_set_irn_register(curr_sp, arch_env->sp);
530 arch_set_irn_register(curr_bp, arch_env->bp);
533 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
534 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
538 * Initialize the callback object.
539 * @param call The call object.
540 * @param aenv The architecture environment.
541 * @param irg The graph with the method.
542 * @return Some pointer. This pointer is passed to all other callback functions as self object.
544 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
546 ia32_abi_env_t *env = XMALLOC(ia32_abi_env_t);
547 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
548 env->flags = fl.bits;
555 * Destroy the callback object.
556 * @param self The callback object.
558 static void ia32_abi_done(void *self) {
563 * Produces the type which sits between the stack args and the locals on the stack.
564 * it will contain the return address and space to store the old base pointer.
565 * @return The Firm type modeling the ABI between type.
567 static ir_type *ia32_abi_get_between_type(void *self)
569 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
570 static ir_type *omit_fp_between_type = NULL;
571 static ir_type *between_type = NULL;
573 ia32_abi_env_t *env = self;
575 if (! between_type) {
576 ir_entity *old_bp_ent;
577 ir_entity *ret_addr_ent;
578 ir_entity *omit_fp_ret_addr_ent;
580 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
581 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
583 between_type = new_type_struct(IDENT("ia32_between_type"));
584 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
585 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
587 set_entity_offset(old_bp_ent, 0);
588 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
589 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
590 set_type_state(between_type, layout_fixed);
592 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
593 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
595 set_entity_offset(omit_fp_ret_addr_ent, 0);
596 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
597 set_type_state(omit_fp_between_type, layout_fixed);
600 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
605 * Get the estimated cycle count for @p irn.
607 * @param self The this pointer.
608 * @param irn The node.
610 * @return The estimated cycle count for this operation
612 static int ia32_get_op_estimated_cost(const ir_node *irn)
615 ia32_op_type_t op_tp;
619 if (!is_ia32_irn(irn))
622 assert(is_ia32_irn(irn));
624 cost = get_ia32_latency(irn);
625 op_tp = get_ia32_op_type(irn);
627 if (is_ia32_CopyB(irn)) {
630 else if (is_ia32_CopyB_i(irn)) {
631 int size = get_ia32_copyb_size(irn);
632 cost = 20 + (int)ceil((4/3) * size);
634 /* in case of address mode operations add additional cycles */
635 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
637 In case of stack access and access to fixed addresses add 5 cycles
638 (we assume they are in cache), other memory operations cost 20
641 if (is_ia32_use_frame(irn) || (
642 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
643 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
655 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
657 * @param irn The original operation
658 * @param i Index of the argument we want the inverse operation to yield
659 * @param inverse struct to be filled with the resulting inverse op
660 * @param obstack The obstack to use for allocation of the returned nodes array
661 * @return The inverse operation or NULL if operation invertible
663 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
667 ir_node *block, *noreg, *nomem;
670 /* we cannot invert non-ia32 irns */
671 if (! is_ia32_irn(irn))
674 /* operand must always be a real operand (not base, index or mem) */
675 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
678 /* we don't invert address mode operations */
679 if (get_ia32_op_type(irn) != ia32_Normal)
682 /* TODO: adjust for new immediates... */
683 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
687 irg = get_irn_irg(irn);
688 block = get_nodes_block(irn);
689 mode = get_irn_mode(irn);
690 irn_mode = get_irn_mode(irn);
691 noreg = get_irn_n(irn, 0);
692 nomem = new_r_NoMem(irg);
693 dbg = get_irn_dbg_info(irn);
695 /* initialize structure */
696 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
700 switch (get_ia32_irn_opcode(irn)) {
703 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
704 /* we have an add with a const here */
705 /* invers == add with negated const */
706 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
708 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
709 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
710 set_ia32_commutative(inverse->nodes[0]);
712 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
713 /* we have an add with a symconst here */
714 /* invers == sub with const */
715 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
717 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
720 /* normal add: inverse == sub */
721 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
728 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
729 /* we have a sub with a const/symconst here */
730 /* invers == add with this const */
731 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
732 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
733 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
737 if (i == n_ia32_binary_left) {
738 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
741 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
749 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
750 /* xor with const: inverse = xor */
751 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
752 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
753 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
757 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
763 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
768 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
773 /* inverse operation not supported */
780 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
782 if(mode_is_float(mode))
789 * Get the mode that should be used for spilling value node
791 static ir_mode *get_spill_mode(const ir_node *node)
793 ir_mode *mode = get_irn_mode(node);
794 return get_spill_mode_mode(mode);
798 * Checks whether an addressmode reload for a node with mode mode is compatible
799 * with a spillslot of mode spill_mode
801 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
803 return !mode_is_float(mode) || mode == spillmode;
807 * Check if irn can load its operand at position i from memory (source addressmode).
808 * @param irn The irn to be checked
809 * @param i The operands position
810 * @return Non-Zero if operand can be loaded
812 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
814 ir_node *op = get_irn_n(irn, i);
815 const ir_mode *mode = get_irn_mode(op);
816 const ir_mode *spillmode = get_spill_mode(op);
818 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
819 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
820 !ia32_is_spillmode_compatible(mode, spillmode) ||
821 is_ia32_use_frame(irn)) /* must not already use frame */
824 switch (get_ia32_am_support(irn)) {
829 if (i != n_ia32_unary_op)
835 case n_ia32_binary_left: {
836 const arch_register_req_t *req;
837 if (!is_ia32_commutative(irn))
840 /* we can't swap left/right for limited registers
841 * (As this (currently) breaks constraint handling copies)
843 req = get_ia32_in_req(irn, n_ia32_binary_left);
844 if (req->type & arch_register_req_type_limited)
849 case n_ia32_binary_right:
858 panic("Unknown AM type");
861 /* HACK: must not already use "real" memory.
862 * This can happen for Call and Div */
863 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
869 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
873 ir_mode *dest_op_mode;
875 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
877 set_ia32_op_type(irn, ia32_AddrModeS);
879 load_mode = get_irn_mode(get_irn_n(irn, i));
880 dest_op_mode = get_ia32_ls_mode(irn);
881 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
882 set_ia32_ls_mode(irn, load_mode);
884 set_ia32_use_frame(irn);
885 set_ia32_need_stackent(irn);
887 if (i == n_ia32_binary_left &&
888 get_ia32_am_support(irn) == ia32_am_binary &&
889 /* immediates are only allowed on the right side */
890 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
891 ia32_swap_left_right(irn);
892 i = n_ia32_binary_right;
895 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
897 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
898 set_irn_n(irn, n_ia32_mem, spill);
899 set_irn_n(irn, i, ia32_get_admissible_noreg(ia32_current_cg, irn, i));
900 set_ia32_is_reload(irn);
903 static const be_abi_callbacks_t ia32_abi_callbacks = {
906 ia32_abi_get_between_type,
907 ia32_abi_dont_save_regs,
912 /* fill register allocator interface */
914 static const arch_irn_ops_t ia32_irn_ops = {
915 ia32_get_irn_reg_req,
920 ia32_get_frame_entity,
921 ia32_set_frame_entity,
922 ia32_set_frame_offset,
925 ia32_get_op_estimated_cost,
926 ia32_possible_memory_operand,
927 ia32_perform_memory_operand,
930 /**************************************************
933 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
934 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
935 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
936 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
939 **************************************************/
941 static ir_entity *mcount = NULL;
943 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
945 static void ia32_before_abi(void *self) {
946 lower_mode_b_config_t lower_mode_b_config = {
947 mode_Iu, /* lowered mode */
948 mode_Bu, /* preferred mode for set */
949 0, /* don't lower direct compares */
951 ia32_code_gen_t *cg = self;
953 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
955 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
957 if (mcount == NULL) {
958 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
959 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
960 /* FIXME: enter the right ld_ident here */
961 set_entity_ld_ident(mcount, get_entity_ident(mcount));
962 set_entity_visibility(mcount, visibility_external_allocated);
964 instrument_initcall(cg->irg, mcount);
968 transformer_t be_transformer = TRANSFORMER_DEFAULT;
971 * Transforms the standard firm graph into
974 static void ia32_prepare_graph(void *self) {
975 ia32_code_gen_t *cg = self;
977 /* do local optimizations */
978 optimize_graph_df(cg->irg);
980 /* TODO: we often have dead code reachable through out-edges here. So for
981 * now we rebuild edges (as we need correct user count for code selection)
984 edges_deactivate(cg->irg);
985 edges_activate(cg->irg);
989 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
991 switch (be_transformer) {
992 case TRANSFORMER_DEFAULT:
993 /* transform remaining nodes into assembler instructions */
994 ia32_transform_graph(cg);
998 case TRANSFORMER_PBQP:
999 case TRANSFORMER_RAND:
1000 /* transform nodes into assembler instructions by PBQP magic */
1001 ia32_transform_graph_by_pbqp(cg);
1005 default: panic("invalid transformer");
1008 /* do local optimizations (mainly CSE) */
1009 optimize_graph_df(cg->irg);
1012 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
1014 /* optimize address mode */
1015 ia32_optimize_graph(cg);
1018 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
1020 /* do code placement, to optimize the position of constants */
1021 place_code(cg->irg);
1024 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
1028 * Dummy functions for hooks we don't need but which must be filled.
1030 static void ia32_before_sched(void *self) {
1034 ir_node *turn_back_am(ir_node *node)
1036 ir_graph *irg = current_ir_graph;
1037 dbg_info *dbgi = get_irn_dbg_info(node);
1038 ir_node *block = get_nodes_block(node);
1039 ir_node *base = get_irn_n(node, n_ia32_base);
1040 ir_node *index = get_irn_n(node, n_ia32_index);
1041 ir_node *mem = get_irn_n(node, n_ia32_mem);
1044 ir_node *load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1045 ir_node *load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1047 ia32_copy_am_attrs(load, node);
1048 if (is_ia32_is_reload(node))
1049 set_ia32_is_reload(load);
1050 set_irn_n(node, n_ia32_mem, new_NoMem());
1052 switch (get_ia32_am_support(node)) {
1054 set_irn_n(node, n_ia32_unary_op, load_res);
1057 case ia32_am_binary:
1058 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
1059 set_irn_n(node, n_ia32_binary_left, load_res);
1061 set_irn_n(node, n_ia32_binary_right, load_res);
1066 panic("Unknown AM type");
1068 noreg = ia32_new_NoReg_gp(ia32_current_cg);
1069 set_irn_n(node, n_ia32_base, noreg);
1070 set_irn_n(node, n_ia32_index, noreg);
1071 set_ia32_am_offs_int(node, 0);
1072 set_ia32_am_sc(node, NULL);
1073 set_ia32_am_scale(node, 0);
1074 clear_ia32_am_sc_sign(node);
1076 /* rewire mem-proj */
1077 if (get_irn_mode(node) == mode_T) {
1078 const ir_edge_t *edge;
1079 foreach_out_edge(node, edge) {
1080 ir_node *out = get_edge_src_irn(edge);
1081 if (get_irn_mode(out) == mode_M) {
1082 set_Proj_pred(out, load);
1083 set_Proj_proj(out, pn_ia32_Load_M);
1089 set_ia32_op_type(node, ia32_Normal);
1090 if (sched_is_scheduled(node))
1091 sched_add_before(node, load);
1096 static ir_node *flags_remat(ir_node *node, ir_node *after)
1098 /* we should turn back source address mode when rematerializing nodes */
1099 ia32_op_type_t type;
1103 if (is_Block(after)) {
1106 block = get_nodes_block(after);
1109 type = get_ia32_op_type(node);
1111 case ia32_AddrModeS:
1115 case ia32_AddrModeD:
1116 /* TODO implement this later... */
1117 panic("found DestAM with flag user %+F this should not happen", node);
1120 default: assert(type == ia32_Normal); break;
1123 copy = exact_copy(node);
1124 set_nodes_block(copy, block);
1125 sched_add_after(after, copy);
1131 * Called before the register allocator.
1133 static void ia32_before_ra(void *self) {
1134 ia32_code_gen_t *cg = self;
1136 /* setup fpu rounding modes */
1137 ia32_setup_fpu_mode(cg);
1140 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1143 ia32_add_missing_keeps(cg);
1148 * Transforms a be_Reload into a ia32 Load.
1150 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1151 ir_graph *irg = get_irn_irg(node);
1152 dbg_info *dbg = get_irn_dbg_info(node);
1153 ir_node *block = get_nodes_block(node);
1154 ir_entity *ent = be_get_frame_entity(node);
1155 ir_mode *mode = get_irn_mode(node);
1156 ir_mode *spillmode = get_spill_mode(node);
1157 ir_node *noreg = ia32_new_NoReg_gp(cg);
1158 ir_node *sched_point = NULL;
1159 ir_node *ptr = get_irg_frame(irg);
1160 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1161 ir_node *new_op, *proj;
1162 const arch_register_t *reg;
1164 if (sched_is_scheduled(node)) {
1165 sched_point = sched_prev(node);
1168 if (mode_is_float(spillmode)) {
1169 if (ia32_cg_config.use_sse2)
1170 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1172 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1174 else if (get_mode_size_bits(spillmode) == 128) {
1175 /* Reload 128 bit SSE registers */
1176 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1179 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1181 set_ia32_op_type(new_op, ia32_AddrModeS);
1182 set_ia32_ls_mode(new_op, spillmode);
1183 set_ia32_frame_ent(new_op, ent);
1184 set_ia32_use_frame(new_op);
1185 set_ia32_is_reload(new_op);
1187 DBG_OPT_RELOAD2LD(node, new_op);
1189 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1192 sched_add_after(sched_point, new_op);
1196 /* copy the register from the old node to the new Load */
1197 reg = arch_get_irn_register(node);
1198 arch_set_irn_register(new_op, reg);
1200 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1202 exchange(node, proj);
1206 * Transforms a be_Spill node into a ia32 Store.
1208 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1209 ir_graph *irg = get_irn_irg(node);
1210 dbg_info *dbg = get_irn_dbg_info(node);
1211 ir_node *block = get_nodes_block(node);
1212 ir_entity *ent = be_get_frame_entity(node);
1213 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1214 ir_mode *mode = get_spill_mode(spillval);
1215 ir_node *noreg = ia32_new_NoReg_gp(cg);
1216 ir_node *nomem = new_rd_NoMem(irg);
1217 ir_node *ptr = get_irg_frame(irg);
1218 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1220 ir_node *sched_point = NULL;
1222 if (sched_is_scheduled(node)) {
1223 sched_point = sched_prev(node);
1226 /* No need to spill unknown values... */
1227 if(is_ia32_Unknown_GP(val) ||
1228 is_ia32_Unknown_VFP(val) ||
1229 is_ia32_Unknown_XMM(val)) {
1234 exchange(node, store);
1238 if (mode_is_float(mode)) {
1239 if (ia32_cg_config.use_sse2)
1240 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1242 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1243 } else if (get_mode_size_bits(mode) == 128) {
1244 /* Spill 128 bit SSE registers */
1245 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1246 } else if (get_mode_size_bits(mode) == 8) {
1247 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1249 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1252 set_ia32_op_type(store, ia32_AddrModeD);
1253 set_ia32_ls_mode(store, mode);
1254 set_ia32_frame_ent(store, ent);
1255 set_ia32_use_frame(store);
1256 set_ia32_is_spill(store);
1257 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1258 DBG_OPT_SPILL2ST(node, store);
1261 sched_add_after(sched_point, store);
1265 exchange(node, store);
1268 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1269 ir_graph *irg = get_irn_irg(node);
1270 dbg_info *dbg = get_irn_dbg_info(node);
1271 ir_node *block = get_nodes_block(node);
1272 ir_node *noreg = ia32_new_NoReg_gp(cg);
1273 ir_node *frame = get_irg_frame(irg);
1275 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
1277 set_ia32_frame_ent(push, ent);
1278 set_ia32_use_frame(push);
1279 set_ia32_op_type(push, ia32_AddrModeS);
1280 set_ia32_ls_mode(push, mode_Is);
1281 set_ia32_is_spill(push);
1283 sched_add_before(schedpoint, push);
1287 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1288 ir_graph *irg = get_irn_irg(node);
1289 dbg_info *dbg = get_irn_dbg_info(node);
1290 ir_node *block = get_nodes_block(node);
1291 ir_node *noreg = ia32_new_NoReg_gp(cg);
1292 ir_node *frame = get_irg_frame(irg);
1294 ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1296 set_ia32_frame_ent(pop, ent);
1297 set_ia32_use_frame(pop);
1298 set_ia32_op_type(pop, ia32_AddrModeD);
1299 set_ia32_ls_mode(pop, mode_Is);
1300 set_ia32_is_reload(pop);
1302 sched_add_before(schedpoint, pop);
1307 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
1309 ir_graph *irg = get_irn_irg(node);
1310 dbg_info *dbg = get_irn_dbg_info(node);
1311 ir_node *block = get_nodes_block(node);
1312 ir_mode *spmode = mode_Iu;
1313 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1316 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1317 arch_set_irn_register(sp, spreg);
1323 * Transform MemPerm, currently we do this the ugly way and produce
1324 * push/pop into/from memory cascades. This is possible without using
1327 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1328 ir_graph *irg = get_irn_irg(node);
1329 ir_node *block = get_nodes_block(node);
1333 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1334 const ir_edge_t *edge;
1335 const ir_edge_t *next;
1338 arity = be_get_MemPerm_entity_arity(node);
1339 pops = alloca(arity * sizeof(pops[0]));
1342 for(i = 0; i < arity; ++i) {
1343 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1344 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1345 ir_type *enttype = get_entity_type(inent);
1346 unsigned entsize = get_type_size_bytes(enttype);
1347 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1348 ir_node *mem = get_irn_n(node, i + 1);
1351 /* work around cases where entities have different sizes */
1352 if(entsize2 < entsize)
1354 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1356 push = create_push(cg, node, node, sp, mem, inent);
1357 sp = create_spproj(node, push, pn_ia32_Push_stack);
1359 /* add another push after the first one */
1360 push = create_push(cg, node, node, sp, mem, inent);
1361 add_ia32_am_offs_int(push, 4);
1362 sp = create_spproj(node, push, pn_ia32_Push_stack);
1365 set_irn_n(node, i, new_Bad());
1369 for(i = arity - 1; i >= 0; --i) {
1370 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1371 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1372 ir_type *enttype = get_entity_type(outent);
1373 unsigned entsize = get_type_size_bytes(enttype);
1374 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1377 /* work around cases where entities have different sizes */
1378 if(entsize2 < entsize)
1380 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1382 pop = create_pop(cg, node, node, sp, outent);
1383 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1385 add_ia32_am_offs_int(pop, 4);
1387 /* add another pop after the first one */
1388 pop = create_pop(cg, node, node, sp, outent);
1389 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
1396 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1397 sched_add_before(node, keep);
1399 /* exchange memprojs */
1400 foreach_out_edge_safe(node, edge, next) {
1401 ir_node *proj = get_edge_src_irn(edge);
1402 int p = get_Proj_proj(proj);
1406 set_Proj_pred(proj, pops[p]);
1407 set_Proj_proj(proj, pn_ia32_Pop_M);
1410 /* remove memperm */
1411 arity = get_irn_arity(node);
1412 for(i = 0; i < arity; ++i) {
1413 set_irn_n(node, i, new_Bad());
1419 * Block-Walker: Calls the transform functions Spill and Reload.
1421 static void ia32_after_ra_walker(ir_node *block, void *env) {
1422 ir_node *node, *prev;
1423 ia32_code_gen_t *cg = env;
1425 /* beware: the schedule is changed here */
1426 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1427 prev = sched_prev(node);
1429 if (be_is_Reload(node)) {
1430 transform_to_Load(cg, node);
1431 } else if (be_is_Spill(node)) {
1432 transform_to_Store(cg, node);
1433 } else if (be_is_MemPerm(node)) {
1434 transform_MemPerm(cg, node);
1440 * Collects nodes that need frame entities assigned.
1442 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1444 be_fec_env_t *env = data;
1446 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1447 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1448 int align = get_mode_size_bytes(mode);
1449 be_node_needs_frame_entity(env, node, mode, align);
1450 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1451 && is_ia32_use_frame(node)) {
1452 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1453 const ir_mode *mode = get_ia32_ls_mode(node);
1454 const ia32_attr_t *attr = get_ia32_attr_const(node);
1457 if (is_ia32_is_reload(node)) {
1458 mode = get_spill_mode_mode(mode);
1461 if(attr->data.need_64bit_stackent) {
1464 if(attr->data.need_32bit_stackent) {
1467 align = get_mode_size_bytes(mode);
1468 be_node_needs_frame_entity(env, node, mode, align);
1469 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1470 || is_ia32_vfld(node)) {
1471 const ir_mode *mode = get_ia32_ls_mode(node);
1473 be_node_needs_frame_entity(env, node, mode, align);
1474 } else if(is_ia32_FldCW(node)) {
1475 /* although 2 byte would be enough 4 byte performs best */
1476 const ir_mode *mode = mode_Iu;
1478 be_node_needs_frame_entity(env, node, mode, align);
1481 assert(is_ia32_St(node) ||
1482 is_ia32_xStoreSimple(node) ||
1483 is_ia32_vfst(node) ||
1484 is_ia32_vfist(node) ||
1485 is_ia32_vfisttp(node) ||
1486 is_ia32_FnstCW(node));
1493 * We transform Spill and Reload here. This needs to be done before
1494 * stack biasing otherwise we would miss the corrected offset for these nodes.
1496 static void ia32_after_ra(void *self) {
1497 ia32_code_gen_t *cg = self;
1498 ir_graph *irg = cg->irg;
1499 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1501 /* create and coalesce frame entities */
1502 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1503 be_assign_entities(fec_env);
1504 be_free_frame_entity_coalescer(fec_env);
1506 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1510 * Last touchups for the graph before emit: x87 simulation to replace the
1511 * virtual with real x87 instructions, creating a block schedule and peephole
1514 static void ia32_finish(void *self) {
1515 ia32_code_gen_t *cg = self;
1516 ir_graph *irg = cg->irg;
1518 ia32_finish_irg(irg, cg);
1520 /* we might have to rewrite x87 virtual registers */
1521 if (cg->do_x87_sim) {
1522 x87_simulate_graph(cg->birg);
1525 /* do peephole optimisations */
1526 ia32_peephole_optimization(cg);
1528 /* create block schedule, this also removes empty blocks which might
1529 * produce critical edges */
1530 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1534 * Emits the code, closes the output file and frees
1535 * the code generator interface.
1537 static void ia32_codegen(void *self) {
1538 ia32_code_gen_t *cg = self;
1539 ir_graph *irg = cg->irg;
1541 ia32_gen_routine(cg, irg);
1545 /* remove it from the isa */
1548 assert(ia32_current_cg == cg);
1549 ia32_current_cg = NULL;
1551 /* de-allocate code generator */
1552 del_set(cg->reg_set);
1557 * Returns the node representing the PIC base.
1559 static ir_node *ia32_get_pic_base(void *self) {
1561 ia32_code_gen_t *cg = self;
1562 ir_node *get_eip = cg->get_eip;
1563 if (get_eip != NULL)
1566 block = get_irg_start_block(cg->irg);
1567 get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
1568 cg->get_eip = get_eip;
1570 be_dep_on_frame(get_eip);
1574 static void *ia32_cg_init(be_irg_t *birg);
1576 static const arch_code_generator_if_t ia32_code_gen_if = {
1578 ia32_get_pic_base, /* return node used as base in pic code addresses */
1579 ia32_before_abi, /* before abi introduce hook */
1582 ia32_before_sched, /* before scheduling hook */
1583 ia32_before_ra, /* before register allocation hook */
1584 ia32_after_ra, /* after register allocation hook */
1585 ia32_finish, /* called before codegen */
1586 ia32_codegen /* emit && done */
1590 * Initializes a IA32 code generator.
1592 static void *ia32_cg_init(be_irg_t *birg) {
1593 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1594 ia32_code_gen_t *cg = XMALLOCZ(ia32_code_gen_t);
1596 cg->impl = &ia32_code_gen_if;
1597 cg->irg = birg->irg;
1598 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1600 cg->arch_env = birg->main_env->arch_env;
1602 cg->blk_sched = NULL;
1603 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1604 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1607 /* Linux gprof implementation needs base pointer */
1608 birg->main_env->options->omit_fp = 0;
1615 if (isa->name_obst) {
1616 obstack_free(isa->name_obst, NULL);
1617 obstack_init(isa->name_obst);
1621 cur_reg_set = cg->reg_set;
1623 assert(ia32_current_cg == NULL);
1624 ia32_current_cg = cg;
1626 return (arch_code_generator_t *)cg;
1631 /*****************************************************************
1632 * ____ _ _ _____ _____
1633 * | _ \ | | | | |_ _|/ ____| /\
1634 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1635 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1636 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1637 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1639 *****************************************************************/
1642 * Set output modes for GCC
1644 static const tarval_mode_info mo_integer = {
1651 * set the tarval output mode of all integer modes to decimal
1653 static void set_tarval_output_modes(void)
1657 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1658 ir_mode *mode = get_irp_mode(i);
1660 if (mode_is_int(mode))
1661 set_tarval_mode_output_option(mode, &mo_integer);
1665 const arch_isa_if_t ia32_isa_if;
1668 * The template that generates a new ISA object.
1669 * Note that this template can be changed by command line
1672 static ia32_isa_t ia32_isa_template = {
1674 &ia32_isa_if, /* isa interface implementation */
1675 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1676 &ia32_gp_regs[REG_EBP], /* base pointer register */
1677 -1, /* stack direction */
1678 2, /* power of two stack alignment, 2^2 == 4 */
1679 NULL, /* main environment */
1680 7, /* costs for a spill instruction */
1681 5, /* costs for a reload instruction */
1683 NULL, /* 16bit register names */
1684 NULL, /* 8bit register names */
1685 NULL, /* 8bit register names high */
1688 NULL, /* current code generator */
1689 NULL, /* abstract machine */
1691 NULL, /* name obstack */
1695 static void init_asm_constraints(void)
1697 be_init_default_asm_constraint_flags();
1699 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1700 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1701 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1702 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1703 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1704 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1705 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1706 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1707 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1708 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1709 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1710 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1711 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1712 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1713 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1714 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1715 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1716 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1717 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1718 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1720 /* no support for autodecrement/autoincrement */
1721 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1722 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1723 /* no float consts */
1724 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1725 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1726 /* makes no sense on x86 */
1727 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1728 /* no support for sse consts yet */
1729 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1730 /* no support for x87 consts yet */
1731 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1732 /* no support for mmx registers yet */
1733 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1734 /* not available in 32bit mode */
1735 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1736 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1738 /* no code yet to determine register class needed... */
1739 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1743 * Initializes the backend ISA.
1745 static arch_env_t *ia32_init(FILE *file_handle) {
1746 static int inited = 0;
1754 set_tarval_output_modes();
1756 isa = XMALLOC(ia32_isa_t);
1757 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1759 if(mode_fpcw == NULL) {
1760 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1763 ia32_register_init();
1764 ia32_create_opcodes(&ia32_irn_ops);
1766 be_emit_init(file_handle);
1767 isa->regs_16bit = pmap_create();
1768 isa->regs_8bit = pmap_create();
1769 isa->regs_8bit_high = pmap_create();
1770 isa->types = pmap_create();
1771 isa->tv_ent = pmap_create();
1772 isa->cpu = ia32_init_machine_description();
1774 ia32_build_16bit_reg_map(isa->regs_16bit);
1775 ia32_build_8bit_reg_map(isa->regs_8bit);
1776 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1779 isa->name_obst = XMALLOC(struct obstack);
1780 obstack_init(isa->name_obst);
1783 /* enter the ISA object into the intrinsic environment */
1784 intrinsic_env.isa = isa;
1785 ia32_handle_intrinsics();
1787 /* emit asm includes */
1788 n = get_irp_n_asms();
1789 for (i = 0; i < n; ++i) {
1790 be_emit_cstring("#APP\n");
1791 be_emit_ident(get_irp_asm(i));
1792 be_emit_cstring("\n#NO_APP\n");
1795 /* needed for the debug support */
1796 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1797 be_emit_cstring(".Ltext0:\n");
1798 be_emit_write_line();
1800 /* we mark referenced global entities, so we can only emit those which
1801 * are actually referenced. (Note: you mustn't use the type visited flag
1802 * elsewhere in the backend)
1804 inc_master_type_visited();
1806 return &isa->arch_env;
1812 * Closes the output file and frees the ISA structure.
1814 static void ia32_done(void *self) {
1815 ia32_isa_t *isa = self;
1817 /* emit now all global declarations */
1818 be_gas_emit_decls(isa->arch_env.main_env, 1);
1820 pmap_destroy(isa->regs_16bit);
1821 pmap_destroy(isa->regs_8bit);
1822 pmap_destroy(isa->regs_8bit_high);
1823 pmap_destroy(isa->tv_ent);
1824 pmap_destroy(isa->types);
1827 obstack_free(isa->name_obst, NULL);
1837 * Return the number of register classes for this architecture.
1838 * We report always these:
1839 * - the general purpose registers
1840 * - the SSE floating point register set
1841 * - the virtual floating point registers
1842 * - the SSE vector register set
1844 static unsigned ia32_get_n_reg_class(const void *self) {
1850 * Return the register class for index i.
1852 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1856 assert(i < N_CLASSES);
1857 return &ia32_reg_classes[i];
1861 * Get the register class which shall be used to store a value of a given mode.
1862 * @param self The this pointer.
1863 * @param mode The mode in question.
1864 * @return A register class which can hold values of the given mode.
1866 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1867 const ir_mode *mode)
1871 if (mode_is_float(mode)) {
1872 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1875 return &ia32_reg_classes[CLASS_ia32_gp];
1879 * Get the ABI restrictions for procedure calls.
1880 * @param self The this pointer.
1881 * @param method_type The type of the method (procedure) in question.
1882 * @param abi The abi object to be modified
1884 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1892 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1896 /* set abi flags for calls */
1897 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1898 call_flags.bits.store_args_sequential = 0;
1899 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1900 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1901 call_flags.bits.call_has_imm = 0; /* No call immediates, we handle this by ourselves */
1903 /* set parameter passing style */
1904 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1906 if (get_method_variadicity(method_type) == variadicity_variadic) {
1907 /* pass all parameters of a variadic function on the stack */
1910 cc = get_method_calling_convention(method_type);
1911 if (get_method_additional_properties(method_type) & mtp_property_private &&
1912 ia32_cg_config.optimize_cc) {
1913 /* set the calling conventions to register parameter */
1914 cc = (cc & ~cc_bits) | cc_reg_param;
1918 /* we have to pop the shadow parameter ourself for compound calls */
1919 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1920 && !(cc & cc_reg_param)) {
1921 pop_amount += get_mode_size_bytes(mode_P_data);
1924 n = get_method_n_params(method_type);
1925 for (i = regnum = 0; i < n; i++) {
1927 const arch_register_t *reg = NULL;
1929 tp = get_method_param_type(method_type, i);
1930 mode = get_type_mode(tp);
1932 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1935 be_abi_call_param_reg(abi, i, reg);
1938 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1939 * movl has a shorter opcode than mov[sz][bw]l */
1940 ir_mode *load_mode = mode;
1943 unsigned size = get_mode_size_bytes(mode);
1945 if (cc & cc_callee_clear_stk) {
1946 pop_amount += (size + 3U) & ~3U;
1949 if (size < 4) load_mode = mode_Iu;
1952 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1956 be_abi_call_set_pop(abi, pop_amount);
1958 /* set return registers */
1959 n = get_method_n_ress(method_type);
1961 assert(n <= 2 && "more than two results not supported");
1963 /* In case of 64bit returns, we will have two 32bit values */
1965 tp = get_method_res_type(method_type, 0);
1966 mode = get_type_mode(tp);
1968 assert(!mode_is_float(mode) && "two FP results not supported");
1970 tp = get_method_res_type(method_type, 1);
1971 mode = get_type_mode(tp);
1973 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1975 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1976 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1979 const arch_register_t *reg;
1981 tp = get_method_res_type(method_type, 0);
1982 assert(is_atomic_type(tp));
1983 mode = get_type_mode(tp);
1985 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1987 be_abi_call_res_reg(abi, 0, reg);
1991 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1995 if(!is_ia32_irn(irn)) {
1999 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
2000 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
2001 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
2002 || is_ia32_Immediate(irn))
2009 * Initializes the code generator interface.
2011 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
2014 return &ia32_code_gen_if;
2018 * Returns the estimated execution time of an ia32 irn.
2020 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
2022 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
2025 list_sched_selector_t ia32_sched_selector;
2028 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
2030 static const list_sched_selector_t *ia32_get_list_sched_selector(
2031 const void *self, list_sched_selector_t *selector)
2034 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
2035 ia32_sched_selector.exectime = ia32_sched_exectime;
2036 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
2037 return &ia32_sched_selector;
2040 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
2047 * Returns the necessary byte alignment for storing a register of given class.
2049 static int ia32_get_reg_class_alignment(const void *self,
2050 const arch_register_class_t *cls)
2052 ir_mode *mode = arch_register_class_mode(cls);
2053 int bytes = get_mode_size_bytes(mode);
2056 if (mode_is_float(mode) && bytes > 8)
2061 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
2062 const void *self, const ir_node *irn)
2064 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
2065 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
2066 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2069 static const be_execution_unit_t *_allowed_units_GP[] = {
2070 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2071 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2072 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2073 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2074 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2075 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2076 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2079 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2080 &be_machine_execution_units_DUMMY[0],
2083 static const be_execution_unit_t **_units_callret[] = {
2084 _allowed_units_BRANCH,
2087 static const be_execution_unit_t **_units_other[] = {
2091 static const be_execution_unit_t **_units_dummy[] = {
2092 _allowed_units_DUMMY,
2095 const be_execution_unit_t ***ret;
2098 if (is_ia32_irn(irn)) {
2099 ret = get_ia32_exec_units(irn);
2100 } else if (is_be_node(irn)) {
2101 if (be_is_Return(irn)) {
2102 ret = _units_callret;
2103 } else if (be_is_Barrier(irn)) {
2117 * Return the abstract ia32 machine.
2119 static const be_machine_t *ia32_get_machine(const void *self) {
2120 const ia32_isa_t *isa = self;
2125 * Return irp irgs in the desired order.
2127 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2134 static void ia32_mark_remat(const void *self, ir_node *node) {
2136 if (is_ia32_irn(node)) {
2137 set_ia32_is_remat(node);
2142 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2143 * @return 1 if allowed, 0 otherwise
2145 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2148 ir_node *cmp = NULL;
2150 /* we can't handle psis with 64bit compares yet */
2152 cmp = get_Proj_pred(sel);
2154 ir_node *left = get_Cmp_left(cmp);
2155 ir_mode *cmp_mode = get_irn_mode(left);
2156 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2163 if (ia32_cg_config.use_cmov) {
2164 if (ia32_cg_config.use_sse2 && cmp != NULL) {
2165 pn_Cmp pn = get_Proj_proj(sel);
2166 ir_node *cl = get_Cmp_left(cmp);
2167 ir_node *cr = get_Cmp_right(cmp);
2169 /* check the Phi nodes: no 64bit and no floating point cmov */
2170 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2171 ir_mode *mode = get_irn_mode(phi);
2173 if (mode_is_float(mode)) {
2174 /* check for Min, Max */
2175 ir_node *t = get_Phi_pred(phi, i);
2176 ir_node *f = get_Phi_pred(phi, j);
2179 /* SSE2 supports Min & Max */
2180 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2181 if (cl == t && cr == f) {
2182 /* Psi(a <=/>= b, a, b) => MIN, MAX */
2184 } else if (cl == f && cr == t) {
2185 /* Psi(a <=/>= b, b, a) => MAX, MIN */
2192 } else if (get_mode_size_bits(mode) > 32)
2196 /* check the Phi nodes: no 64bit and no floating point cmov */
2197 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2198 ir_mode *mode = get_irn_mode(phi);
2200 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2210 /* No cmov, only some special cases */
2214 /* Now some supported cases here */
2215 pn = get_Proj_proj(sel);
2216 cl = get_Cmp_left(cmp);
2217 cr = get_Cmp_right(cmp);
2219 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2220 ir_mode *mode = get_irn_mode(phi);
2224 t = get_Phi_pred(phi, i);
2225 f = get_Phi_pred(phi, j);
2227 /* no floating point and no 64bit yet */
2228 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2231 if (is_Const(t) && is_Const(f)) {
2232 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2233 /* always support Psi(x, C1, C2) */
2236 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2239 } else if (cl == t && cr == f) {
2240 /* Psi(a <=/>= b, a, b) => Min, Max */
2242 } else if (cl == f && cr == t) {
2243 /* Psi(a <=/>= b, b, a) => Max, Min */
2246 } else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2247 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2248 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2249 /* Psi(a >=u b, a - b, 0) unsigned Doz */
2251 } else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2252 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2253 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2254 /* Psi(a <=u b, 0, a - b) unsigned Doz */
2256 } else if (is_Const(cr) && is_Const_null(cr)) {
2257 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2258 /* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
2260 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2261 /* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
2269 /* all checks passed */
2275 static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
2280 /* we already added all our simple flags to the flags modifier list in
2281 * init, so this flag we don't know. */
2282 return ASM_CONSTRAINT_FLAG_INVALID;
2285 static int ia32_is_valid_clobber(const void *self, const char *clobber)
2289 return ia32_get_clobber_register(clobber) != NULL;
2293 * Returns the libFirm configuration parameter for this backend.
2295 static const backend_params *ia32_get_libfirm_params(void) {
2296 static const ir_settings_if_conv_t ifconv = {
2297 4, /* maxdepth, doesn't matter for Psi-conversion */
2298 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2300 static const ir_settings_arch_dep_t ad = {
2301 1, /* also use subs */
2302 4, /* maximum shifts */
2303 31, /* maximum shift amount */
2304 ia32_evaluate_insn, /* evaluate the instruction sequence */
2306 1, /* allow Mulhs */
2307 1, /* allow Mulus */
2308 32 /* Mulh allowed up to 32 bit */
2310 static backend_params p = {
2311 1, /* need dword lowering */
2312 1, /* support inline assembly */
2313 0, /* no immediate floating point mode. */
2314 NULL, /* no additional opcodes */
2315 NULL, /* will be set later */
2316 ia32_create_intrinsic_fkt,
2317 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2318 NULL, /* will be set below */
2319 NULL /* will be set below */
2322 ia32_setup_cg_config();
2324 /* doesn't really belong here, but this is the earliest place the backend
2326 init_asm_constraints();
2329 p.if_conv_info = &ifconv;
2333 static const lc_opt_enum_int_items_t gas_items[] = {
2334 { "elf", GAS_FLAVOUR_ELF },
2335 { "mingw", GAS_FLAVOUR_MINGW },
2336 { "yasm", GAS_FLAVOUR_YASM },
2337 { "macho", GAS_FLAVOUR_MACH_O },
2341 static lc_opt_enum_int_var_t gas_var = {
2342 (int*) &be_gas_flavour, gas_items
2345 static const lc_opt_enum_int_items_t transformer_items[] = {
2346 { "default", TRANSFORMER_DEFAULT },
2347 #ifdef FIRM_GRGEN_BE
2348 { "pbqp", TRANSFORMER_PBQP },
2349 { "random", TRANSFORMER_RAND },
2354 static lc_opt_enum_int_var_t transformer_var = {
2355 (int*)&be_transformer, transformer_items
2358 static const lc_opt_table_entry_t ia32_options[] = {
2359 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2360 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2361 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2362 &ia32_isa_template.arch_env.stack_alignment),
2366 const arch_isa_if_t ia32_isa_if = {
2369 ia32_get_n_reg_class,
2371 ia32_get_reg_class_for_mode,
2373 ia32_get_code_generator_if,
2374 ia32_get_list_sched_selector,
2375 ia32_get_ilp_sched_selector,
2376 ia32_get_reg_class_alignment,
2377 ia32_get_libfirm_params,
2378 ia32_get_allowed_execution_units,
2382 ia32_parse_asm_constraint,
2383 ia32_is_valid_clobber
2386 void ia32_init_emitter(void);
2387 void ia32_init_finish(void);
2388 void ia32_init_optimize(void);
2389 void ia32_init_transform(void);
2390 void ia32_init_x87(void);
2392 void be_init_arch_ia32(void)
2394 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2395 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2397 lc_opt_add_table(ia32_grp, ia32_options);
2398 be_register_isa_if("ia32", &ia32_isa_if);
2400 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2402 ia32_init_emitter();
2404 ia32_init_optimize();
2405 ia32_init_transform();
2407 ia32_init_architecture();
2410 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);