2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
28 #include "lc_opts_enum.h"
36 #include "iredges_t.h"
49 #include "iroptimize.h"
50 #include "instrument.h"
53 #include "lower_calls.h"
54 #include "lower_mode_b.h"
55 #include "lower_softfloat.h"
64 #include "beblocksched.h"
65 #include "bespillutil.h"
66 #include "bespillslots.h"
71 #include "betranshlp.h"
72 #include "belistsched.h"
73 #include "beabihelper.h"
76 #include "bearch_ia32_t.h"
78 #include "ia32_new_nodes.h"
79 #include "gen_ia32_regalloc_if.h"
80 #include "ia32_common_transform.h"
81 #include "ia32_transform.h"
82 #include "ia32_emitter.h"
83 #include "ia32_optimize.h"
85 #include "ia32_dbg_stat.h"
86 #include "ia32_finish.h"
88 #include "ia32_architecture.h"
91 #include "ia32_pbqp_transform.h"
93 transformer_t be_transformer = TRANSFORMER_DEFAULT;
96 ir_mode *ia32_mode_fpcw;
100 /** The current omit-fp state */
101 static ir_type *omit_fp_between_type = NULL;
102 static ir_type *between_type = NULL;
103 static ir_entity *old_bp_ent = NULL;
104 static ir_entity *ret_addr_ent = NULL;
105 static ir_entity *omit_fp_ret_addr_ent = NULL;
108 * The environment for the intrinsic mapping.
110 static ia32_intrinsic_env_t intrinsic_env = {
112 NULL, /* the irg, these entities belong to */
113 NULL, /* entity for __divdi3 library call */
114 NULL, /* entity for __moddi3 library call */
115 NULL, /* entity for __udivdi3 library call */
116 NULL, /* entity for __umoddi3 library call */
120 typedef ir_node *(*create_const_node_func) (dbg_info *dbgi, ir_node *block);
123 * Used to create per-graph unique pseudo nodes.
125 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
126 create_const_node_func func,
127 const arch_register_t* reg)
129 ir_node *block, *res;
134 block = get_irg_start_block(irg);
135 res = func(NULL, block);
136 arch_set_irn_register(res, reg);
142 /* Creates the unique per irg GP NoReg node. */
143 ir_node *ia32_new_NoReg_gp(ir_graph *irg)
145 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
146 return create_const(irg, &irg_data->noreg_gp, new_bd_ia32_NoReg_GP,
147 &ia32_registers[REG_GP_NOREG]);
150 ir_node *ia32_new_NoReg_fp(ir_graph *irg)
152 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
153 return create_const(irg, &irg_data->noreg_fp, new_bd_ia32_NoReg_FP,
154 &ia32_registers[REG_FP_NOREG]);
157 ir_node *ia32_new_NoReg_xmm(ir_graph *irg)
159 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
160 return create_const(irg, &irg_data->noreg_xmm, new_bd_ia32_NoReg_XMM,
161 &ia32_registers[REG_XMM_NOREG]);
164 ir_node *ia32_new_Fpu_truncate(ir_graph *irg)
166 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
167 return create_const(irg, &irg_data->fpu_trunc_mode, new_bd_ia32_ChangeCW,
168 &ia32_registers[REG_FPCW]);
173 * Returns the admissible noreg register node for input register pos of node irn.
175 static ir_node *ia32_get_admissible_noreg(ir_node *irn, int pos)
177 ir_graph *irg = get_irn_irg(irn);
178 const arch_register_req_t *req = arch_get_irn_register_req_in(irn, pos);
180 assert(req != NULL && "Missing register requirements");
181 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
182 return ia32_new_NoReg_gp(irg);
184 if (ia32_cg_config.use_sse2) {
185 return ia32_new_NoReg_xmm(irg);
187 return ia32_new_NoReg_fp(irg);
191 static ir_entity *ia32_get_frame_entity(const ir_node *irn)
193 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
196 static void ia32_set_frame_entity(ir_node *node, ir_entity *entity)
198 if (is_be_node(node))
199 be_node_set_frame_entity(node, entity);
201 set_ia32_frame_ent(node, entity);
204 static void ia32_set_frame_offset(ir_node *irn, int bias)
206 if (get_ia32_frame_ent(irn) == NULL)
209 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
210 ir_graph *irg = get_irn_irg(irn);
211 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
212 if (layout->sp_relative) {
213 /* Pop nodes modify the stack pointer before calculating the
214 * destination address, so fix this here
219 add_ia32_am_offs_int(irn, bias);
222 static int ia32_get_sp_bias(const ir_node *node)
224 if (is_ia32_Call(node))
225 return -(int)get_ia32_call_attr_const(node)->pop;
227 if (is_ia32_Push(node))
230 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
233 if (is_ia32_Leave(node) || is_ia32_CopyEbpEsp(node)) {
234 return SP_BIAS_RESET;
241 * Build the between type and entities if not already build.
243 static void ia32_build_between_type(void)
245 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
246 if (between_type == NULL) {
247 ir_type *old_bp_type = new_type_primitive(mode_Iu);
248 ir_type *ret_addr_type = new_type_primitive(mode_Iu);
250 between_type = new_type_struct(IDENT("ia32_between_type"));
251 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
252 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
254 set_entity_offset(old_bp_ent, 0);
255 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
256 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
257 set_type_state(between_type, layout_fixed);
259 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
260 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
262 set_entity_offset(omit_fp_ret_addr_ent, 0);
263 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
264 set_type_state(omit_fp_between_type, layout_fixed);
270 * Produces the type which sits between the stack args and the locals on the stack.
271 * it will contain the return address and space to store the old base pointer.
272 * @return The Firm type modeling the ABI between type.
274 static ir_type *ia32_abi_get_between_type(ir_graph *irg)
276 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
277 ia32_build_between_type();
278 return layout->sp_relative ? omit_fp_between_type : between_type;
282 * Return the stack entity that contains the return address.
284 ir_entity *ia32_get_return_address_entity(ir_graph *irg)
286 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
287 ia32_build_between_type();
288 return layout->sp_relative ? omit_fp_ret_addr_ent : ret_addr_ent;
292 * Return the stack entity that contains the frame address.
294 ir_entity *ia32_get_frame_address_entity(ir_graph *irg)
296 const be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
297 ia32_build_between_type();
298 return layout->sp_relative ? NULL : old_bp_ent;
302 * Get the estimated cycle count for @p irn.
304 * @param self The this pointer.
305 * @param irn The node.
307 * @return The estimated cycle count for this operation
309 static int ia32_get_op_estimated_cost(const ir_node *irn)
312 ia32_op_type_t op_tp;
316 if (!is_ia32_irn(irn))
319 assert(is_ia32_irn(irn));
321 cost = get_ia32_latency(irn);
322 op_tp = get_ia32_op_type(irn);
324 if (is_ia32_CopyB(irn)) {
327 else if (is_ia32_CopyB_i(irn)) {
328 int size = get_ia32_copyb_size(irn);
329 cost = 20 + (int)ceil((4/3) * size);
331 /* in case of address mode operations add additional cycles */
332 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
334 In case of stack access and access to fixed addresses add 5 cycles
335 (we assume they are in cache), other memory operations cost 20
338 if (is_ia32_use_frame(irn) || (
339 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_base)) &&
340 is_ia32_NoReg_GP(get_irn_n(irn, n_ia32_index))
351 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
353 if (mode_is_float(mode))
360 * Get the mode that should be used for spilling value node
362 static ir_mode *get_spill_mode(const ir_node *node)
364 ir_mode *mode = get_irn_mode(node);
365 return get_spill_mode_mode(mode);
369 * Checks whether an addressmode reload for a node with mode mode is compatible
370 * with a spillslot of mode spill_mode
372 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
374 return !mode_is_float(mode) || mode == spillmode;
378 * Check if irn can load its operand at position i from memory (source addressmode).
379 * @param irn The irn to be checked
380 * @param i The operands position
381 * @return Non-Zero if operand can be loaded
383 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i)
385 ir_node *op = get_irn_n(irn, i);
386 const ir_mode *mode = get_irn_mode(op);
387 const ir_mode *spillmode = get_spill_mode(op);
389 if (!is_ia32_irn(irn) || /* must be an ia32 irn */
390 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
391 !ia32_is_spillmode_compatible(mode, spillmode) ||
392 is_ia32_use_frame(irn)) /* must not already use frame */
395 switch (get_ia32_am_support(irn)) {
400 if (i != n_ia32_unary_op)
406 case n_ia32_binary_left: {
407 const arch_register_req_t *req;
408 if (!is_ia32_commutative(irn))
411 /* we can't swap left/right for limited registers
412 * (As this (currently) breaks constraint handling copies)
414 req = arch_get_irn_register_req_in(irn, n_ia32_binary_left);
415 if (req->type & arch_register_req_type_limited)
420 case n_ia32_binary_right:
429 panic("Unknown AM type");
432 /* HACK: must not already use "real" memory.
433 * This can happen for Call and Div */
434 if (!is_NoMem(get_irn_n(irn, n_ia32_mem)))
440 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
444 ir_mode *dest_op_mode;
446 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
448 set_ia32_op_type(irn, ia32_AddrModeS);
450 load_mode = get_irn_mode(get_irn_n(irn, i));
451 dest_op_mode = get_ia32_ls_mode(irn);
452 if (get_mode_size_bits(load_mode) <= get_mode_size_bits(dest_op_mode)) {
453 set_ia32_ls_mode(irn, load_mode);
455 set_ia32_use_frame(irn);
456 set_ia32_need_stackent(irn);
458 if (i == n_ia32_binary_left &&
459 get_ia32_am_support(irn) == ia32_am_binary &&
460 /* immediates are only allowed on the right side */
461 !is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_right))) {
462 ia32_swap_left_right(irn);
463 i = n_ia32_binary_right;
466 assert(is_NoMem(get_irn_n(irn, n_ia32_mem)));
468 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
469 set_irn_n(irn, n_ia32_mem, spill);
470 set_irn_n(irn, i, ia32_get_admissible_noreg(irn, i));
471 set_ia32_is_reload(irn);
474 static const be_abi_callbacks_t ia32_abi_callbacks = {
475 ia32_abi_get_between_type,
478 /* register allocator interface */
479 static const arch_irn_ops_t ia32_irn_ops = {
480 ia32_get_frame_entity,
481 ia32_set_frame_offset,
483 ia32_get_op_estimated_cost,
484 ia32_possible_memory_operand,
485 ia32_perform_memory_operand,
488 static ir_entity *mcount = NULL;
489 static int gprof = 0;
491 static void ia32_before_abi(ir_graph *irg)
494 if (mcount == NULL) {
495 ir_type *tp = new_type_method(0, 0);
496 ident *id = new_id_from_str("mcount");
497 mcount = new_entity(get_glob_type(), id, tp);
498 /* FIXME: enter the right ld_ident here */
499 set_entity_ld_ident(mcount, get_entity_ident(mcount));
500 set_entity_visibility(mcount, ir_visibility_external);
502 instrument_initcall(irg, mcount);
507 * Transforms the standard firm graph into
510 static void ia32_prepare_graph(ir_graph *irg)
512 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
515 switch (be_transformer) {
516 case TRANSFORMER_DEFAULT:
517 /* transform remaining nodes into assembler instructions */
518 ia32_transform_graph(irg);
521 case TRANSFORMER_PBQP:
522 case TRANSFORMER_RAND:
523 /* transform nodes into assembler instructions by PBQP magic */
524 ia32_transform_graph_by_pbqp(irg);
528 panic("invalid transformer");
531 ia32_transform_graph(irg);
534 /* do local optimizations (mainly CSE) */
535 optimize_graph_df(irg);
536 /* backend code expects that outedges are always enabled */
540 dump_ir_graph(irg, "transformed");
542 /* optimize address mode */
543 ia32_optimize_graph(irg);
545 /* do code placement, to optimize the position of constants */
547 /* backend code expects that outedges are always enabled */
551 dump_ir_graph(irg, "place");
554 ir_node *ia32_turn_back_am(ir_node *node)
556 dbg_info *dbgi = get_irn_dbg_info(node);
557 ir_graph *irg = get_irn_irg(node);
558 ir_node *block = get_nodes_block(node);
559 ir_node *base = get_irn_n(node, n_ia32_base);
560 ir_node *idx = get_irn_n(node, n_ia32_index);
561 ir_node *mem = get_irn_n(node, n_ia32_mem);
564 ir_node *load = new_bd_ia32_Load(dbgi, block, base, idx, mem);
565 ir_node *load_res = new_rd_Proj(dbgi, load, mode_Iu, pn_ia32_Load_res);
567 ia32_copy_am_attrs(load, node);
568 if (is_ia32_is_reload(node))
569 set_ia32_is_reload(load);
570 set_irn_n(node, n_ia32_mem, get_irg_no_mem(irg));
572 switch (get_ia32_am_support(node)) {
574 set_irn_n(node, n_ia32_unary_op, load_res);
578 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
579 set_irn_n(node, n_ia32_binary_left, load_res);
581 set_irn_n(node, n_ia32_binary_right, load_res);
586 panic("Unknown AM type");
588 noreg = ia32_new_NoReg_gp(irg);
589 set_irn_n(node, n_ia32_base, noreg);
590 set_irn_n(node, n_ia32_index, noreg);
591 set_ia32_am_offs_int(node, 0);
592 set_ia32_am_sc(node, NULL);
593 set_ia32_am_scale(node, 0);
594 clear_ia32_am_sc_sign(node);
596 /* rewire mem-proj */
597 if (get_irn_mode(node) == mode_T) {
598 foreach_out_edge(node, edge) {
599 ir_node *out = get_edge_src_irn(edge);
600 if (get_irn_mode(out) == mode_M) {
601 set_Proj_pred(out, load);
602 set_Proj_proj(out, pn_ia32_Load_M);
608 set_ia32_op_type(node, ia32_Normal);
609 if (sched_is_scheduled(node))
610 sched_add_before(node, load);
615 static ir_node *flags_remat(ir_node *node, ir_node *after)
617 /* we should turn back source address mode when rematerializing nodes */
622 if (is_Block(after)) {
625 block = get_nodes_block(after);
628 type = get_ia32_op_type(node);
631 ia32_turn_back_am(node);
635 /* TODO implement this later... */
636 panic("found DestAM with flag user %+F this should not happen", node);
638 default: assert(type == ia32_Normal); break;
641 copy = exact_copy(node);
642 set_nodes_block(copy, block);
643 sched_add_after(after, copy);
649 * Called before the register allocator.
651 static void ia32_before_ra(ir_graph *irg)
653 /* setup fpu rounding modes */
654 ia32_setup_fpu_mode(irg);
657 be_sched_fix_flags(irg, &ia32_reg_classes[CLASS_ia32_flags],
660 be_add_missing_keeps(irg);
665 * Transforms a be_Reload into a ia32 Load.
667 static void transform_to_Load(ir_node *node)
669 ir_graph *irg = get_irn_irg(node);
670 dbg_info *dbgi = get_irn_dbg_info(node);
671 ir_node *block = get_nodes_block(node);
672 ir_entity *ent = be_get_frame_entity(node);
673 ir_mode *mode = get_irn_mode(node);
674 ir_mode *spillmode = get_spill_mode(node);
675 ir_node *noreg = ia32_new_NoReg_gp(irg);
676 ir_node *sched_point = NULL;
677 ir_node *ptr = get_irg_frame(irg);
678 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
679 ir_node *new_op, *proj;
680 const arch_register_t *reg;
682 if (sched_is_scheduled(node)) {
683 sched_point = sched_prev(node);
686 if (mode_is_float(spillmode)) {
687 if (ia32_cg_config.use_sse2)
688 new_op = new_bd_ia32_xLoad(dbgi, block, ptr, noreg, mem, spillmode);
690 new_op = new_bd_ia32_fld(dbgi, block, ptr, noreg, mem, spillmode);
692 else if (get_mode_size_bits(spillmode) == 128) {
693 /* Reload 128 bit SSE registers */
694 new_op = new_bd_ia32_xxLoad(dbgi, block, ptr, noreg, mem);
697 new_op = new_bd_ia32_Load(dbgi, block, ptr, noreg, mem);
699 set_ia32_op_type(new_op, ia32_AddrModeS);
700 set_ia32_ls_mode(new_op, spillmode);
701 set_ia32_frame_ent(new_op, ent);
702 set_ia32_use_frame(new_op);
703 set_ia32_is_reload(new_op);
705 DBG_OPT_RELOAD2LD(node, new_op);
707 proj = new_rd_Proj(dbgi, new_op, mode, pn_ia32_Load_res);
710 sched_add_after(sched_point, new_op);
714 /* copy the register from the old node to the new Load */
715 reg = arch_get_irn_register(node);
716 arch_set_irn_register(proj, reg);
718 SET_IA32_ORIG_NODE(new_op, node);
720 exchange(node, proj);
724 * Transforms a be_Spill node into a ia32 Store.
726 static void transform_to_Store(ir_node *node)
728 ir_graph *irg = get_irn_irg(node);
729 dbg_info *dbgi = get_irn_dbg_info(node);
730 ir_node *block = get_nodes_block(node);
731 ir_entity *ent = be_get_frame_entity(node);
732 const ir_node *spillval = get_irn_n(node, n_be_Spill_val);
733 ir_mode *mode = get_spill_mode(spillval);
734 ir_node *noreg = ia32_new_NoReg_gp(irg);
735 ir_node *nomem = get_irg_no_mem(irg);
736 ir_node *ptr = get_irg_frame(irg);
737 ir_node *val = get_irn_n(node, n_be_Spill_val);
740 ir_node *sched_point = NULL;
742 if (sched_is_scheduled(node)) {
743 sched_point = sched_prev(node);
746 if (mode_is_float(mode)) {
747 if (ia32_cg_config.use_sse2) {
748 store = new_bd_ia32_xStore(dbgi, block, ptr, noreg, nomem, val);
749 res = new_r_Proj(store, mode_M, pn_ia32_xStore_M);
751 store = new_bd_ia32_fst(dbgi, block, ptr, noreg, nomem, val, mode);
752 res = new_r_Proj(store, mode_M, pn_ia32_fst_M);
754 } else if (get_mode_size_bits(mode) == 128) {
755 /* Spill 128 bit SSE registers */
756 store = new_bd_ia32_xxStore(dbgi, block, ptr, noreg, nomem, val);
757 res = new_r_Proj(store, mode_M, pn_ia32_xxStore_M);
758 } else if (get_mode_size_bits(mode) == 8) {
759 store = new_bd_ia32_Store8Bit(dbgi, block, ptr, noreg, nomem, val);
760 res = new_r_Proj(store, mode_M, pn_ia32_Store8Bit_M);
762 store = new_bd_ia32_Store(dbgi, block, ptr, noreg, nomem, val);
763 res = new_r_Proj(store, mode_M, pn_ia32_Store_M);
766 set_ia32_op_type(store, ia32_AddrModeD);
767 set_ia32_ls_mode(store, mode);
768 set_ia32_frame_ent(store, ent);
769 set_ia32_use_frame(store);
770 set_ia32_is_spill(store);
771 SET_IA32_ORIG_NODE(store, node);
772 DBG_OPT_SPILL2ST(node, store);
775 sched_add_after(sched_point, store);
782 static ir_node *create_push(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent)
784 dbg_info *dbgi = get_irn_dbg_info(node);
785 ir_node *block = get_nodes_block(node);
786 ir_graph *irg = get_irn_irg(node);
787 ir_node *noreg = ia32_new_NoReg_gp(irg);
788 ir_node *frame = get_irg_frame(irg);
790 ir_node *push = new_bd_ia32_Push(dbgi, block, frame, noreg, mem, noreg, sp);
792 set_ia32_frame_ent(push, ent);
793 set_ia32_use_frame(push);
794 set_ia32_op_type(push, ia32_AddrModeS);
795 set_ia32_ls_mode(push, mode_Is);
796 set_ia32_is_spill(push);
798 sched_add_before(schedpoint, push);
802 static ir_node *create_pop(ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent)
804 dbg_info *dbgi = get_irn_dbg_info(node);
805 ir_node *block = get_nodes_block(node);
806 ir_graph *irg = get_irn_irg(node);
807 ir_node *noreg = ia32_new_NoReg_gp(irg);
808 ir_node *frame = get_irg_frame(irg);
810 ir_node *pop = new_bd_ia32_PopMem(dbgi, block, frame, noreg,
811 get_irg_no_mem(irg), sp);
813 set_ia32_frame_ent(pop, ent);
814 set_ia32_use_frame(pop);
815 set_ia32_op_type(pop, ia32_AddrModeD);
816 set_ia32_ls_mode(pop, mode_Is);
817 set_ia32_is_reload(pop);
819 sched_add_before(schedpoint, pop);
824 static ir_node* create_spproj(ir_node *node, ir_node *pred, int pos)
826 dbg_info *dbgi = get_irn_dbg_info(node);
827 ir_mode *spmode = mode_Iu;
828 const arch_register_t *spreg = &ia32_registers[REG_ESP];
831 sp = new_rd_Proj(dbgi, pred, spmode, pos);
832 arch_set_irn_register(sp, spreg);
838 * Transform MemPerm, currently we do this the ugly way and produce
839 * push/pop into/from memory cascades. This is possible without using
842 static void transform_MemPerm(ir_node *node)
844 ir_node *block = get_nodes_block(node);
845 ir_graph *irg = get_irn_irg(node);
846 ir_node *sp = be_get_initial_reg_value(irg, &ia32_registers[REG_ESP]);
847 int arity = be_get_MemPerm_entity_arity(node);
848 ir_node **pops = ALLOCAN(ir_node*, arity);
854 for (i = 0; i < arity; ++i) {
855 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
856 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
857 ir_type *enttype = get_entity_type(inent);
858 unsigned entsize = get_type_size_bytes(enttype);
859 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
860 ir_node *mem = get_irn_n(node, i + 1);
863 /* work around cases where entities have different sizes */
864 if (entsize2 < entsize)
866 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
868 push = create_push(node, node, sp, mem, inent);
869 sp = create_spproj(node, push, pn_ia32_Push_stack);
871 /* add another push after the first one */
872 push = create_push(node, node, sp, mem, inent);
873 add_ia32_am_offs_int(push, 4);
874 sp = create_spproj(node, push, pn_ia32_Push_stack);
877 set_irn_n(node, i, new_r_Bad(irg, mode_X));
881 for (i = arity - 1; i >= 0; --i) {
882 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
883 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
884 ir_type *enttype = get_entity_type(outent);
885 unsigned entsize = get_type_size_bytes(enttype);
886 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
889 /* work around cases where entities have different sizes */
890 if (entsize2 < entsize)
892 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
894 pop = create_pop(node, node, sp, outent);
895 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
897 add_ia32_am_offs_int(pop, 4);
899 /* add another pop after the first one */
900 pop = create_pop(node, node, sp, outent);
901 sp = create_spproj(node, pop, pn_ia32_Pop_stack);
908 keep = be_new_Keep(block, 1, in);
909 sched_add_before(node, keep);
911 /* exchange memprojs */
912 foreach_out_edge_safe(node, edge) {
913 ir_node *proj = get_edge_src_irn(edge);
914 int p = get_Proj_proj(proj);
918 set_Proj_pred(proj, pops[p]);
919 set_Proj_proj(proj, pn_ia32_Pop_M);
928 * Block-Walker: Calls the transform functions Spill and Reload.
930 static void ia32_after_ra_walker(ir_node *block, void *env)
932 ir_node *node, *prev;
935 /* beware: the schedule is changed here */
936 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
937 prev = sched_prev(node);
939 if (be_is_Reload(node)) {
940 transform_to_Load(node);
941 } else if (be_is_Spill(node)) {
942 transform_to_Store(node);
943 } else if (be_is_MemPerm(node)) {
944 transform_MemPerm(node);
950 * Collects nodes that need frame entities assigned.
952 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
954 be_fec_env_t *env = (be_fec_env_t*)data;
958 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
959 mode = get_spill_mode_mode(get_irn_mode(node));
960 align = get_mode_size_bytes(mode);
961 } else if (is_ia32_irn(node) &&
962 get_ia32_frame_ent(node) == NULL &&
963 is_ia32_use_frame(node)) {
964 if (is_ia32_need_stackent(node))
967 switch (get_ia32_irn_opcode(node)) {
969 case iro_ia32_Load: {
970 const ia32_attr_t *attr = get_ia32_attr_const(node);
972 if (attr->data.need_32bit_stackent) {
974 } else if (attr->data.need_64bit_stackent) {
977 mode = get_ia32_ls_mode(node);
978 if (is_ia32_is_reload(node))
979 mode = get_spill_mode_mode(mode);
981 align = get_mode_size_bytes(mode);
987 case iro_ia32_xLoad: {
988 mode = get_ia32_ls_mode(node);
993 case iro_ia32_FldCW: {
994 /* although 2 byte would be enough 4 byte performs best */
1002 panic("unexpected frame user while collection frame entity nodes");
1004 case iro_ia32_FnstCW:
1005 case iro_ia32_Store8Bit:
1006 case iro_ia32_Store:
1009 case iro_ia32_fisttp:
1010 case iro_ia32_xStore:
1011 case iro_ia32_xStoreSimple:
1018 be_node_needs_frame_entity(env, node, mode, align);
1021 static int determine_ebp_input(ir_node *ret)
1023 const arch_register_t *bp = &ia32_registers[REG_EBP];
1024 int arity = get_irn_arity(ret);
1027 for (i = 0; i < arity; ++i) {
1028 ir_node *input = get_irn_n(ret, i);
1029 if (arch_get_irn_register(input) == bp)
1032 panic("no ebp input found at %+F", ret);
1035 static void introduce_epilog(ir_node *ret)
1037 const arch_register_t *sp = &ia32_registers[REG_ESP];
1038 const arch_register_t *bp = &ia32_registers[REG_EBP];
1039 ir_graph *irg = get_irn_irg(ret);
1040 ir_type *frame_type = get_irg_frame_type(irg);
1041 unsigned frame_size = get_type_size_bytes(frame_type);
1042 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1043 ir_node *block = get_nodes_block(ret);
1044 ir_node *first_sp = get_irn_n(ret, n_be_Return_sp);
1045 ir_node *curr_sp = first_sp;
1046 ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
1048 if (!layout->sp_relative) {
1049 int n_ebp = determine_ebp_input(ret);
1050 ir_node *curr_bp = get_irn_n(ret, n_ebp);
1051 if (ia32_cg_config.use_leave) {
1052 ir_node *leave = new_bd_ia32_Leave(NULL, block, curr_bp);
1053 curr_bp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_frame);
1054 curr_sp = new_r_Proj(leave, mode_gp, pn_ia32_Leave_stack);
1055 arch_set_irn_register(curr_bp, bp);
1056 arch_set_irn_register(curr_sp, sp);
1057 sched_add_before(ret, leave);
1060 ir_node *curr_mem = get_irn_n(ret, n_be_Return_mem);
1061 /* copy ebp to esp */
1062 curr_sp = new_bd_ia32_CopyEbpEsp(NULL, block, curr_bp);
1063 arch_set_irn_register(curr_sp, sp);
1064 sched_add_before(ret, curr_sp);
1067 pop = new_bd_ia32_PopEbp(NULL, block, curr_mem, curr_sp);
1068 curr_bp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_res);
1069 curr_sp = new_r_Proj(pop, mode_gp, pn_ia32_PopEbp_stack);
1070 curr_mem = new_r_Proj(pop, mode_M, pn_ia32_Pop_M);
1071 arch_set_irn_register(curr_bp, bp);
1072 arch_set_irn_register(curr_sp, sp);
1073 sched_add_before(ret, pop);
1075 set_irn_n(ret, n_be_Return_mem, curr_mem);
1077 set_irn_n(ret, n_ebp, curr_bp);
1079 ir_node *incsp = be_new_IncSP(sp, block, curr_sp, -(int)frame_size, 0);
1080 sched_add_before(ret, incsp);
1083 set_irn_n(ret, n_be_Return_sp, curr_sp);
1085 /* keep verifier happy... */
1086 if (get_irn_n_edges(first_sp) == 0 && is_Proj(first_sp)) {
1087 kill_node(first_sp);
1092 * put the Prolog code at the beginning, epilog code before each return
1094 static void introduce_prolog_epilog(ir_graph *irg)
1096 const arch_register_t *sp = &ia32_registers[REG_ESP];
1097 const arch_register_t *bp = &ia32_registers[REG_EBP];
1098 ir_node *start = get_irg_start(irg);
1099 ir_node *block = get_nodes_block(start);
1100 ir_type *frame_type = get_irg_frame_type(irg);
1101 unsigned frame_size = get_type_size_bytes(frame_type);
1102 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1103 ir_node *initial_sp = be_get_initial_reg_value(irg, sp);
1104 ir_node *curr_sp = initial_sp;
1105 ir_mode *mode_gp = mode_Iu;
1107 if (!layout->sp_relative) {
1109 ir_node *mem = get_irg_initial_mem(irg);
1110 ir_node *noreg = ia32_new_NoReg_gp(irg);
1111 ir_node *initial_bp = be_get_initial_reg_value(irg, bp);
1112 ir_node *push = new_bd_ia32_Push(NULL, block, noreg, noreg, mem, initial_bp, initial_sp);
1115 curr_sp = new_r_Proj(push, mode_gp, pn_ia32_Push_stack);
1116 arch_set_irn_register(curr_sp, sp);
1117 sched_add_after(start, push);
1119 /* move esp to ebp */
1120 ir_node *const curr_bp = be_new_Copy(block, curr_sp);
1121 sched_add_after(push, curr_bp);
1122 be_set_constr_single_reg_out(curr_bp, 0, bp, arch_register_req_type_ignore);
1123 curr_sp = be_new_CopyKeep_single(block, curr_sp, curr_bp);
1124 sched_add_after(curr_bp, curr_sp);
1125 be_set_constr_single_reg_out(curr_sp, 0, sp, arch_register_req_type_produces_sp);
1126 edges_reroute_except(initial_bp, curr_bp, push);
1128 incsp = be_new_IncSP(sp, block, curr_sp, frame_size, 0);
1129 edges_reroute_except(initial_sp, incsp, push);
1130 sched_add_after(curr_sp, incsp);
1132 /* make sure the initial IncSP is really used by someone */
1133 if (get_irn_n_edges(incsp) <= 1) {
1134 ir_node *in[] = { incsp };
1135 ir_node *keep = be_new_Keep(block, 1, in);
1136 sched_add_after(incsp, keep);
1139 layout->initial_bias = -4;
1141 ir_node *const incsp = be_new_IncSP(sp, block, initial_sp, frame_size, 0);
1142 edges_reroute_except(initial_sp, incsp, incsp);
1143 sched_add_after(start, incsp);
1146 /* introduce epilog for every return node */
1148 ir_node *end_block = get_irg_end_block(irg);
1149 int arity = get_irn_arity(end_block);
1152 for (i = 0; i < arity; ++i) {
1153 ir_node *ret = get_irn_n(end_block, i);
1154 assert(be_is_Return(ret));
1155 introduce_epilog(ret);
1161 * Last touchups for the graph before emit: x87 simulation to replace the
1162 * virtual with real x87 instructions, creating a block schedule and peephole
1165 static void ia32_finish_graph(ir_graph *irg)
1167 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1168 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
1169 bool at_begin = stack_layout->sp_relative ? true : false;
1170 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
1172 /* create and coalesce frame entities */
1173 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1174 be_assign_entities(fec_env, ia32_set_frame_entity, at_begin);
1175 be_free_frame_entity_coalescer(fec_env);
1177 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, NULL);
1179 introduce_prolog_epilog(irg);
1181 /* fix stack entity offsets */
1182 be_abi_fix_stack_nodes(irg);
1183 be_abi_fix_stack_bias(irg);
1185 /* fix 2-address code constraints */
1186 ia32_finish_irg(irg);
1188 /* we might have to rewrite x87 virtual registers */
1189 if (irg_data->do_x87_sim) {
1190 ia32_x87_simulate_graph(irg);
1193 /* do peephole optimisations */
1194 ia32_peephole_optimization(irg);
1196 be_remove_dead_nodes_from_schedule(irg);
1198 /* create block schedule, this also removes empty blocks which might
1199 * produce critical edges */
1200 irg_data->blk_sched = be_create_block_schedule(irg);
1204 * Emits the code, closes the output file and frees
1205 * the code generator interface.
1207 static void ia32_emit(ir_graph *irg)
1209 if (ia32_cg_config.emit_machcode) {
1210 ia32_gen_binary_routine(irg);
1212 ia32_gen_routine(irg);
1217 * Returns the node representing the PIC base.
1219 static ir_node *ia32_get_pic_base(ir_graph *irg)
1221 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1223 ir_node *get_eip = irg_data->get_eip;
1224 if (get_eip != NULL)
1227 block = get_irg_start_block(irg);
1228 get_eip = new_bd_ia32_GetEIP(NULL, block);
1229 irg_data->get_eip = get_eip;
1235 * Initializes a IA32 code generator.
1237 static void ia32_init_graph(ir_graph *irg)
1239 struct obstack *obst = be_get_be_obst(irg);
1240 ia32_irg_data_t *irg_data = OALLOCZ(obst, ia32_irg_data_t);
1242 irg_data->dump = (be_options.dump_flags & DUMP_BE) ? 1 : 0;
1245 /* Linux gprof implementation needs base pointer */
1246 be_options.omit_fp = 0;
1249 be_birg_from_irg(irg)->isa_link = irg_data;
1252 static const tarval_mode_info mo_integer = {
1259 * set the tarval output mode of all integer modes to decimal
1261 static void set_tarval_output_modes(void)
1265 for (i = ir_get_n_modes(); i > 0;) {
1266 ir_mode *mode = ir_get_mode(--i);
1268 if (mode_is_int(mode))
1269 set_tarval_mode_output_option(mode, &mo_integer);
1273 extern const arch_isa_if_t ia32_isa_if;
1275 static void init_asm_constraints(void)
1277 be_init_default_asm_constraint_flags();
1279 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1280 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1281 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1282 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1283 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1284 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1285 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1286 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1287 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1288 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1289 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1290 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1291 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1292 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1293 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1294 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1295 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1296 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1297 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1298 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1300 /* no support for autodecrement/autoincrement */
1301 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1302 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1303 /* no float consts */
1304 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1305 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1306 /* makes no sense on x86 */
1307 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1308 /* no support for sse consts yet */
1309 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1310 /* no support for x87 consts yet */
1311 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1312 /* no support for mmx registers yet */
1313 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1314 /* not available in 32bit mode */
1315 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1316 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1318 /* no code yet to determine register class needed... */
1319 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1323 * Check if Mux(sel, mux_true, mux_false) would represent a Max or Min operation
1325 static bool mux_is_float_min_max(ir_node *sel, ir_node *mux_true,
1330 ir_relation relation;
1335 cmp_l = get_Cmp_left(sel);
1336 cmp_r = get_Cmp_right(sel);
1337 if (!mode_is_float(get_irn_mode(cmp_l)))
1340 /* check for min/max. They're defined as (C-Semantik):
1341 * min(a, b) = a < b ? a : b
1342 * or min(a, b) = a <= b ? a : b
1343 * max(a, b) = a > b ? a : b
1344 * or max(a, b) = a >= b ? a : b
1345 * (Note we only handle float min/max here)
1347 relation = get_Cmp_relation(sel);
1349 case ir_relation_greater_equal:
1350 case ir_relation_greater:
1352 if (cmp_l == mux_true && cmp_r == mux_false)
1355 case ir_relation_less_equal:
1356 case ir_relation_less:
1358 if (cmp_l == mux_true && cmp_r == mux_false)
1361 case ir_relation_unordered_greater_equal:
1362 case ir_relation_unordered_greater:
1364 if (cmp_l == mux_false && cmp_r == mux_true)
1367 case ir_relation_unordered_less_equal:
1368 case ir_relation_unordered_less:
1370 if (cmp_l == mux_false && cmp_r == mux_true)
1381 static bool mux_is_set(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1383 ir_mode *mode = get_irn_mode(mux_true);
1386 if (!mode_is_int(mode) && !mode_is_reference(mode)
1390 if (is_Const(mux_true) && is_Const(mux_false)) {
1391 /* we can create a set plus up two 3 instructions for any combination
1399 static bool mux_is_float_const_const(ir_node *sel, ir_node *mux_true,
1404 if (!mode_is_float(get_irn_mode(mux_true)))
1407 return is_Const(mux_true) && is_Const(mux_false);
1410 static bool mux_is_doz(ir_node *sel, ir_node *mux_true, ir_node *mux_false)
1417 ir_relation relation;
1422 mode = get_irn_mode(mux_true);
1423 if (mode_is_signed(mode) || mode_is_float(mode))
1426 relation = get_Cmp_relation(sel);
1427 cmp_left = get_Cmp_left(sel);
1428 cmp_right = get_Cmp_right(sel);
1430 /* "move" zero constant to false input */
1431 if (is_Const(mux_true) && is_Const_null(mux_true)) {
1432 ir_node *tmp = mux_false;
1433 mux_false = mux_true;
1435 relation = get_negated_relation(relation);
1437 if (!is_Const(mux_false) || !is_Const_null(mux_false))
1439 if (!is_Sub(mux_true))
1441 sub_left = get_Sub_left(mux_true);
1442 sub_right = get_Sub_right(mux_true);
1444 /* Mux(a >=u b, 0, a-b) */
1445 if ((relation & ir_relation_greater)
1446 && sub_left == cmp_left && sub_right == cmp_right)
1448 /* Mux(a <=u b, 0, b-a) */
1449 if ((relation & ir_relation_less)
1450 && sub_left == cmp_right && sub_right == cmp_left)
1456 static int ia32_is_mux_allowed(ir_node *sel, ir_node *mux_false,
1461 /* middleend can handle some things */
1462 if (ir_is_optimizable_mux(sel, mux_false, mux_true))
1464 /* we can handle Set for all modes and compares */
1465 if (mux_is_set(sel, mux_true, mux_false))
1467 /* SSE has own min/max operations */
1468 if (ia32_cg_config.use_sse2
1469 && mux_is_float_min_max(sel, mux_true, mux_false))
1471 /* we can handle Mux(?, Const[f], Const[f]) */
1472 if (mux_is_float_const_const(sel, mux_true, mux_false)) {
1473 #ifdef FIRM_GRGEN_BE
1474 /* well, some code selectors can't handle it */
1475 if (be_transformer != TRANSFORMER_PBQP
1476 || be_transformer != TRANSFORMER_RAND)
1483 /* no support for 64bit inputs to cmov */
1484 mode = get_irn_mode(mux_true);
1485 if (get_mode_size_bits(mode) > 32)
1487 /* we can handle Abs for all modes and compares (except 64bit) */
1488 if (ir_mux_is_abs(sel, mux_false, mux_true) != 0)
1490 /* we can't handle MuxF yet */
1491 if (mode_is_float(mode))
1494 if (mux_is_doz(sel, mux_true, mux_false))
1497 /* Check Cmp before the node */
1499 ir_mode *cmp_mode = get_irn_mode(get_Cmp_left(sel));
1501 /* we can't handle 64bit compares */
1502 if (get_mode_size_bits(cmp_mode) > 32)
1505 /* we can't handle float compares */
1506 if (mode_is_float(cmp_mode))
1510 /* did we disable cmov generation? */
1511 if (!ia32_cg_config.use_cmov)
1514 /* we can use a cmov */
1519 * Create the trampoline code.
1521 static ir_node *ia32_create_trampoline_fkt(ir_node *block, ir_node *mem, ir_node *trampoline, ir_node *env, ir_node *callee)
1523 ir_graph *const irg = get_irn_irg(block);
1524 ir_node * p = trampoline;
1525 ir_mode *const mode = get_irn_mode(p);
1526 ir_node *const one = new_r_Const(irg, get_mode_one(mode_Iu));
1527 ir_node *const four = new_r_Const_long(irg, mode_Iu, 4);
1531 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xb9), cons_none);
1532 mem = new_r_Proj(st, mode_M, pn_Store_M);
1533 p = new_r_Add(block, p, one, mode);
1534 st = new_r_Store(block, mem, p, env, cons_none);
1535 mem = new_r_Proj(st, mode_M, pn_Store_M);
1536 p = new_r_Add(block, p, four, mode);
1538 st = new_r_Store(block, mem, p, new_r_Const_long(irg, mode_Bu, 0xe9), cons_none);
1539 mem = new_r_Proj(st, mode_M, pn_Store_M);
1540 p = new_r_Add(block, p, one, mode);
1541 st = new_r_Store(block, mem, p, callee, cons_none);
1542 mem = new_r_Proj(st, mode_M, pn_Store_M);
1547 static const ir_settings_arch_dep_t ia32_arch_dep = {
1548 1, /* also use subs */
1549 4, /* maximum shifts */
1550 63, /* maximum shift amount */
1551 ia32_evaluate_insn, /* evaluate the instruction sequence */
1553 1, /* allow Mulhs */
1554 1, /* allow Mulus */
1555 32, /* Mulh allowed up to 32 bit */
1557 static backend_params ia32_backend_params = {
1558 1, /* support inline assembly */
1559 1, /* support Rotl nodes */
1560 0, /* little endian */
1561 1, /* modulo shift efficient */
1562 0, /* non-modulo shift not efficient */
1563 &ia32_arch_dep, /* will be set later */
1564 ia32_is_mux_allowed,
1565 32, /* machine_size */
1566 NULL, /* float arithmetic mode, will be set below */
1567 NULL, /* long long type */
1568 NULL, /* unsigned long long type */
1569 NULL, /* long double type */
1570 12, /* size of trampoline code */
1571 4, /* alignment of trampoline code */
1572 ia32_create_trampoline_fkt,
1573 4 /* alignment of stack parameter */
1577 * Initializes the backend ISA.
1579 static void ia32_init(void)
1581 ir_mode *mode_long_long;
1582 ir_mode *mode_unsigned_long_long;
1583 ir_type *type_long_long;
1584 ir_type *type_unsigned_long_long;
1586 ia32_setup_cg_config();
1588 init_asm_constraints();
1590 ia32_mode_fpcw = new_int_mode("Fpcw", irma_twos_complement, 16, 0, 0);
1592 /* note mantissa is 64bit but with explicitely encoded 1 so the really
1593 * usable part as counted by firm is only 63 bits */
1594 ia32_mode_E = new_float_mode("E", irma_x86_extended_float, 15, 63);
1595 ia32_type_E = new_type_primitive(ia32_mode_E);
1596 set_type_size_bytes(ia32_type_E, 12);
1597 set_type_alignment_bytes(ia32_type_E, 4);
1599 mode_long_long = new_int_mode("long long", irma_twos_complement, 64, 1, 64);
1600 type_long_long = new_type_primitive(mode_long_long);
1601 mode_unsigned_long_long
1602 = new_int_mode("unsigned long long", irma_twos_complement, 64, 0, 64);
1603 type_unsigned_long_long = new_type_primitive(mode_unsigned_long_long);
1605 ia32_backend_params.type_long_long = type_long_long;
1606 ia32_backend_params.type_unsigned_long_long = type_unsigned_long_long;
1608 if (ia32_cg_config.use_sse2 || ia32_cg_config.use_softfloat) {
1609 ia32_backend_params.mode_float_arithmetic = NULL;
1610 ia32_backend_params.type_long_double = NULL;
1612 ia32_backend_params.mode_float_arithmetic = ia32_mode_E;
1613 ia32_backend_params.type_long_double = ia32_type_E;
1616 ia32_register_init();
1617 obstack_init(&opcodes_obst);
1618 ia32_create_opcodes(&ia32_irn_ops);
1621 static void ia32_finish(void)
1623 if (between_type != NULL) {
1624 free_type(between_type);
1625 between_type = NULL;
1627 ia32_free_opcodes();
1628 obstack_free(&opcodes_obst, NULL);
1632 * The template that generates a new ISA object.
1633 * Note that this template can be changed by command line
1636 static ia32_isa_t ia32_isa_template = {
1638 &ia32_isa_if, /* isa interface implementation */
1643 &ia32_registers[REG_ESP], /* stack pointer register */
1644 &ia32_registers[REG_EBP], /* base pointer register */
1645 2, /* power of two stack alignment, 2^2 == 4 */
1646 NULL, /* main environment */
1647 7, /* costs for a spill instruction */
1648 5, /* costs for a reload instruction */
1649 false, /* no custom abi handling */
1652 IA32_FPU_ARCH_X87, /* FPU architecture */
1655 static arch_env_t *ia32_begin_codegeneration(const be_main_env_t *env)
1657 ia32_isa_t *isa = XMALLOC(ia32_isa_t);
1659 set_tarval_output_modes();
1661 *isa = ia32_isa_template;
1662 isa->tv_ent = pmap_create();
1664 /* enter the ISA object into the intrinsic environment */
1665 intrinsic_env.isa = isa;
1667 be_emit_init(env->file_handle);
1668 be_gas_begin_compilation_unit(env);
1674 * Closes the output file and frees the ISA structure.
1676 static void ia32_end_codegeneration(void *self)
1678 ia32_isa_t *isa = (ia32_isa_t*)self;
1680 /* emit now all global declarations */
1681 be_gas_end_compilation_unit(isa->base.main_env);
1685 pmap_destroy(isa->tv_ent);
1690 * Returns the register for parameter nr.
1692 static const arch_register_t *ia32_get_RegParam_reg(unsigned cc, unsigned nr,
1693 const ir_mode *mode)
1695 static const arch_register_t *gpreg_param_reg_fastcall[] = {
1696 &ia32_registers[REG_ECX],
1697 &ia32_registers[REG_EDX],
1700 static const unsigned MAXNUM_GPREG_ARGS = 3;
1702 static const arch_register_t *gpreg_param_reg_regparam[] = {
1703 &ia32_registers[REG_EAX],
1704 &ia32_registers[REG_EDX],
1705 &ia32_registers[REG_ECX]
1708 static const arch_register_t *gpreg_param_reg_this[] = {
1709 &ia32_registers[REG_ECX],
1714 static const arch_register_t *fpreg_sse_param_reg_std[] = {
1715 &ia32_registers[REG_XMM0],
1716 &ia32_registers[REG_XMM1],
1717 &ia32_registers[REG_XMM2],
1718 &ia32_registers[REG_XMM3],
1719 &ia32_registers[REG_XMM4],
1720 &ia32_registers[REG_XMM5],
1721 &ia32_registers[REG_XMM6],
1722 &ia32_registers[REG_XMM7]
1725 static const arch_register_t *fpreg_sse_param_reg_this[] = {
1726 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
1728 static const unsigned MAXNUM_SSE_ARGS = 8;
1730 if ((cc & cc_this_call) && nr == 0)
1731 return gpreg_param_reg_this[0];
1733 if (! (cc & cc_reg_param))
1736 if (mode_is_float(mode)) {
1737 if (!ia32_cg_config.use_sse2 || (cc & cc_fpreg_param) == 0)
1739 if (nr >= MAXNUM_SSE_ARGS)
1742 if (cc & cc_this_call) {
1743 return fpreg_sse_param_reg_this[nr];
1745 return fpreg_sse_param_reg_std[nr];
1746 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
1747 unsigned num_regparam;
1749 if (get_mode_size_bits(mode) > 32)
1752 if (nr >= MAXNUM_GPREG_ARGS)
1755 if (cc & cc_this_call) {
1756 return gpreg_param_reg_this[nr];
1758 num_regparam = cc & ~cc_bits;
1759 if (num_regparam == 0) {
1760 /* default fastcall */
1761 return gpreg_param_reg_fastcall[nr];
1763 if (nr < num_regparam)
1764 return gpreg_param_reg_regparam[nr];
1768 panic("unknown argument mode");
1772 * Get the ABI restrictions for procedure calls.
1774 static void ia32_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
1779 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1781 /* set abi flags for calls */
1782 /* call_flags.try_omit_fp not changed: can handle both settings */
1783 call_flags.call_has_imm = false; /* No call immediate, we handle this by ourselves */
1785 /* set parameter passing style */
1786 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1788 cc = get_method_calling_convention(method_type);
1789 if (get_method_variadicity(method_type) == variadicity_variadic) {
1790 /* pass all parameters of a variadic function on the stack */
1791 cc = cc_cdecl_set | (cc & cc_this_call);
1793 if (get_method_additional_properties(method_type) & mtp_property_private &&
1794 ia32_cg_config.optimize_cc) {
1795 /* set the fast calling conventions (allowing up to 3) */
1796 cc = SET_FASTCALL(cc) | 3;
1800 /* we have to pop the shadow parameter ourself for compound calls */
1801 if ( (get_method_calling_convention(method_type) & cc_compound_ret)
1802 && !(cc & cc_reg_param)) {
1803 pop_amount += get_mode_size_bytes(mode_P_data);
1806 n = get_method_n_params(method_type);
1807 for (i = regnum = 0; i < n; i++) {
1808 const arch_register_t *reg = NULL;
1809 ir_type *tp = get_method_param_type(method_type, i);
1810 ir_mode *mode = get_type_mode(tp);
1813 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1816 be_abi_call_param_reg(abi, i, reg, ABI_CONTEXT_BOTH);
1819 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1820 * movl has a shorter opcode than mov[sz][bw]l */
1821 ir_mode *load_mode = mode;
1824 unsigned size = get_mode_size_bytes(mode);
1826 if (cc & cc_callee_clear_stk) {
1827 pop_amount += (size + 3U) & ~3U;
1830 if (size < 4) load_mode = mode_Iu;
1833 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0, ABI_CONTEXT_BOTH);
1837 be_abi_call_set_pop(abi, pop_amount);
1839 /* set return registers */
1840 n = get_method_n_ress(method_type);
1842 assert(n <= 2 && "more than two results not supported");
1844 /* In case of 64bit returns, we will have two 32bit values */
1846 ir_type *tp = get_method_res_type(method_type, 0);
1847 ir_mode *mode = get_type_mode(tp);
1849 assert(!mode_is_float(mode) && "two FP results not supported");
1851 tp = get_method_res_type(method_type, 1);
1852 mode = get_type_mode(tp);
1854 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1856 be_abi_call_res_reg(abi, 0, &ia32_registers[REG_EAX], ABI_CONTEXT_BOTH);
1857 be_abi_call_res_reg(abi, 1, &ia32_registers[REG_EDX], ABI_CONTEXT_BOTH);
1860 ir_type *tp = get_method_res_type(method_type, 0);
1861 ir_mode *mode = get_type_mode(tp);
1862 const arch_register_t *reg;
1863 assert(is_atomic_type(tp));
1865 reg = mode_is_float(mode) ? &ia32_registers[REG_ST0] : &ia32_registers[REG_EAX];
1867 be_abi_call_res_reg(abi, 0, reg, ABI_CONTEXT_BOTH);
1871 static void ia32_mark_remat(ir_node *node)
1873 if (is_ia32_irn(node)) {
1874 set_ia32_is_remat(node);
1878 static asm_constraint_flags_t ia32_parse_asm_constraint(const char **c)
1882 /* we already added all our simple flags to the flags modifier list in
1883 * init, so this flag we don't know. */
1884 return ASM_CONSTRAINT_FLAG_INVALID;
1887 static int ia32_is_valid_clobber(const char *clobber)
1889 return ia32_get_clobber_register(clobber) != NULL;
1892 static void ia32_lower_for_target(void)
1894 ir_mode *mode_gp = ia32_reg_classes[CLASS_ia32_gp].mode;
1895 size_t i, n_irgs = get_irp_n_irgs();
1897 /* perform doubleword lowering */
1898 lwrdw_param_t lower_dw_params = {
1899 1, /* little endian */
1900 64, /* doubleword size */
1901 ia32_create_intrinsic_fkt,
1905 /* lower compound param handling
1906 * Note: we lower compound arguments ourself, since on ia32 we don't
1907 * have hidden parameters but know where to find the structs on the stack.
1908 * (This also forces us to always allocate space for the compound arguments
1909 * on the callframe and we can't just use an arbitrary position on the
1912 lower_calls_with_compounds(LF_RETURN_HIDDEN | LF_DONT_LOWER_ARGUMENTS);
1914 /* replace floating point operations by function calls */
1915 if (ia32_cg_config.use_softfloat) {
1916 lower_floating_point();
1919 for (i = 0; i < n_irgs; ++i) {
1920 ir_graph *irg = get_irp_irg(i);
1921 /* break up switches with wide ranges */
1922 lower_switch(irg, 4, 256, mode_gp);
1925 ir_prepare_dw_lowering(&lower_dw_params);
1928 for (i = 0; i < n_irgs; ++i) {
1929 ir_graph *irg = get_irp_irg(i);
1930 /* lower for mode_b stuff */
1931 ir_lower_mode_b(irg, mode_Iu);
1934 for (i = 0; i < n_irgs; ++i) {
1935 ir_graph *irg = get_irp_irg(i);
1936 /* Turn all small CopyBs into loads/stores, keep medium-sized CopyBs,
1937 * so we can generate rep movs later, and turn all big CopyBs into
1939 lower_CopyB(irg, 64, 8193, true);
1944 * Returns the libFirm configuration parameter for this backend.
1946 static const backend_params *ia32_get_libfirm_params(void)
1948 return &ia32_backend_params;
1952 * Check if the given register is callee or caller save.
1954 static int ia32_register_saved_by(const arch_register_t *reg, int callee)
1957 /* check for callee saved */
1958 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
1959 switch (reg->index) {
1970 /* check for caller saved */
1971 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_gp]) {
1972 switch (reg->index) {
1980 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_xmm]) {
1981 /* all XMM registers are caller save */
1982 return reg->index != REG_XMM_NOREG;
1983 } else if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_fp]) {
1984 /* all FP registers are caller save */
1985 return reg->index != REG_FP_NOREG;
1991 static const lc_opt_enum_int_items_t gas_items[] = {
1992 { "elf", OBJECT_FILE_FORMAT_ELF },
1993 { "mingw", OBJECT_FILE_FORMAT_COFF },
1994 { "macho", OBJECT_FILE_FORMAT_MACH_O },
1998 static lc_opt_enum_int_var_t gas_var = {
1999 (int*) &be_gas_object_file_format, gas_items
2002 #ifdef FIRM_GRGEN_BE
2003 static const lc_opt_enum_int_items_t transformer_items[] = {
2004 { "default", TRANSFORMER_DEFAULT },
2005 { "pbqp", TRANSFORMER_PBQP },
2006 { "random", TRANSFORMER_RAND },
2010 static lc_opt_enum_int_var_t transformer_var = {
2011 (int*)&be_transformer, transformer_items
2015 static const lc_opt_table_entry_t ia32_options[] = {
2016 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2017 #ifdef FIRM_GRGEN_BE
2018 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2020 LC_OPT_ENT_INT ("stackalign", "set power of two stack alignment for calls",
2021 &ia32_isa_template.base.stack_alignment),
2022 LC_OPT_ENT_BOOL("gprof", "create gprof profiling code", &gprof),
2026 const arch_isa_if_t ia32_isa_if = {
2029 ia32_get_libfirm_params,
2030 ia32_lower_for_target,
2031 ia32_parse_asm_constraint,
2032 ia32_is_valid_clobber,
2034 ia32_begin_codegeneration,
2035 ia32_end_codegeneration,
2039 ia32_get_pic_base, /* return node used as base in pic code addresses */
2042 ia32_register_saved_by,
2044 ia32_handle_intrinsics,
2045 ia32_before_abi, /* before abi introduce hook */
2047 ia32_before_ra, /* before register allocation hook */
2048 ia32_finish_graph, /* called before codegen */
2049 ia32_emit, /* emit && done */
2052 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32)
2053 void be_init_arch_ia32(void)
2055 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2056 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2058 lc_opt_add_table(ia32_grp, ia32_options);
2059 be_register_isa_if("ia32", &ia32_isa_if);
2061 ia32_init_emitter();
2063 ia32_init_optimize();
2064 ia32_init_transform();
2066 ia32_init_architecture();