2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
41 #include "bearch_ia32_t.h"
43 #include "ia32_new_nodes.h" /* ia32 nodes interface */
44 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
45 #include "ia32_gen_decls.h" /* interface declaration emitter */
46 #include "ia32_transform.h"
47 #include "ia32_emitter.h"
48 #include "ia32_map_regs.h"
49 #include "ia32_optimize.h"
51 #include "ia32_dbg_stat.h"
52 #include "ia32_finish.h"
53 #include "ia32_util.h"
55 #define DEBUG_MODULE "firm.be.ia32.isa"
58 static set *cur_reg_set = NULL;
61 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
63 /* Creates the unique per irg GP NoReg node. */
64 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
65 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
68 /* Creates the unique per irg FP NoReg node. */
69 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
70 return be_abi_get_callee_save_irn(cg->birg->abi,
71 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
74 /* returns the first Proj with given mode from mode_T node */
75 static ir_node *get_proj_for_mode(ir_node *node, ir_mode *mode) {
76 const ir_edge_t *edge;
78 assert(get_irn_mode(node) == mode_T && "Need mode_T node.");
80 foreach_out_edge(node, edge) {
81 ir_node *proj = get_edge_src_irn(edge);
82 if (get_irn_mode(proj) == mode)
89 /**************************************************
92 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
93 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
94 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
95 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
98 **************************************************/
100 static ir_node *my_skip_proj(const ir_node *n) {
102 n = get_Proj_pred(n);
108 * Return register requirements for an ia32 node.
109 * If the node returns a tuple (mode_T) then the proj's
110 * will be asked for this information.
112 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
113 const ia32_irn_ops_t *ops = self;
114 const ia32_register_req_t *irn_req;
115 long node_pos = pos == -1 ? 0 : pos;
116 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
117 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
119 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
120 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
124 if (mode == mode_T && pos < 0) {
125 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
129 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
133 node_pos = ia32_translate_proj_pos(irn);
139 irn = my_skip_proj(irn);
141 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
144 if (is_ia32_irn(irn)) {
146 irn_req = get_ia32_in_req(irn, pos);
149 irn_req = get_ia32_out_req(irn, node_pos);
152 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
154 memcpy(req, &(irn_req->req), sizeof(*req));
156 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
157 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
158 req->other_same = get_irn_n(irn, irn_req->same_pos);
161 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
162 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
163 req->other_different = get_irn_n(irn, irn_req->different_pos);
167 /* treat Unknowns like Const with default requirements */
168 if (is_Unknown(irn)) {
169 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
170 if (mode_is_float(mode)) {
171 if (USE_SSE2(ops->cg))
172 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
174 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
176 else if (mode_is_int(mode) || mode_is_reference(mode))
177 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
178 else if (mode == mode_T || mode == mode_M) {
179 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
183 assert(0 && "unsupported Unknown-Mode");
186 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
194 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
196 const ia32_irn_ops_t *ops = self;
198 if (get_irn_mode(irn) == mode_X) {
202 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
205 pos = ia32_translate_proj_pos(irn);
206 irn = my_skip_proj(irn);
209 if (is_ia32_irn(irn)) {
210 const arch_register_t **slots;
212 slots = get_ia32_slots(irn);
216 ia32_set_firm_reg(irn, reg, cur_reg_set);
220 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
222 const arch_register_t *reg = NULL;
226 if (get_irn_mode(irn) == mode_X) {
230 pos = ia32_translate_proj_pos(irn);
231 irn = my_skip_proj(irn);
234 if (is_ia32_irn(irn)) {
235 const arch_register_t **slots;
236 slots = get_ia32_slots(irn);
240 reg = ia32_get_firm_reg(irn, cur_reg_set);
246 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
247 irn = my_skip_proj(irn);
249 return arch_irn_class_branch;
250 else if (is_ia32_Cnst(irn))
251 return arch_irn_class_const;
252 else if (is_ia32_Ld(irn))
253 return arch_irn_class_load;
254 else if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
255 return arch_irn_class_store;
256 else if (is_ia32_irn(irn))
257 return arch_irn_class_normal;
262 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
263 irn = my_skip_proj(irn);
264 if (is_ia32_irn(irn))
265 return get_ia32_flags(irn);
268 return arch_irn_flags_ignore;
273 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
274 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
277 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
279 const ia32_irn_ops_t *ops = self;
281 if (get_ia32_frame_ent(irn)) {
282 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
284 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
285 snprintf(buf, sizeof(buf), "%d", bias);
287 if (get_ia32_op_type(irn) == ia32_Normal) {
288 set_ia32_cnst(irn, buf);
291 add_ia32_am_offs(irn, buf);
293 set_ia32_am_flavour(irn, am_flav);
299 be_abi_call_flags_bits_t flags;
300 const arch_isa_t *isa;
301 const arch_env_t *aenv;
305 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
307 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
308 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
309 env->flags = fl.bits;
312 env->isa = aenv->isa;
317 * Put all registers which are saved by the prologue/epilogue in a set.
319 * @param self The callback object.
320 * @param s The result set.
322 static void ia32_abi_dont_save_regs(void *self, pset *s)
324 ia32_abi_env_t *env = self;
325 if(env->flags.try_omit_fp)
326 pset_insert_ptr(s, env->isa->bp);
330 * Generate the routine prologue.
332 * @param self The callback object.
333 * @param mem A pointer to the mem node. Update this if you define new memory.
334 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
336 * @return The register which shall be used as a stack frame base.
338 * All nodes which define registers in @p reg_map must keep @p reg_map current.
340 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
342 ia32_abi_env_t *env = self;
344 if (!env->flags.try_omit_fp) {
345 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
346 ir_node *bl = get_irg_start_block(env->irg);
347 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
348 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
352 push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
353 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
354 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
356 /* the push must have SP out register */
357 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
358 set_ia32_flags(push, arch_irn_flags_ignore);
360 /* move esp to ebp */
361 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
362 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
363 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
364 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
366 /* beware: the copy must be done before any other sp use */
367 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
368 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
369 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
370 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
372 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
373 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
382 * Generate the routine epilogue.
383 * @param self The callback object.
384 * @param bl The block for the epilog
385 * @param mem A pointer to the mem node. Update this if you define new memory.
386 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
387 * @return The register which shall be used as a stack frame base.
389 * All nodes which define registers in @p reg_map must keep @p reg_map current.
391 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
393 ia32_abi_env_t *env = self;
394 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
395 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
397 if (env->flags.try_omit_fp) {
398 /* simply remove the stack frame here */
399 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
402 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
403 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
404 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
406 /* gcc always emits a leave at the end of a routine */
407 if (1 || ARCH_AMD(isa->opt_arch)) {
411 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
412 set_ia32_flags(leave, arch_irn_flags_ignore);
413 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
414 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
415 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
420 /* copy ebp to esp */
421 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
424 pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
425 set_ia32_flags(pop, arch_irn_flags_ignore);
426 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
427 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
428 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
430 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
431 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
434 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
435 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
439 * Produces the type which sits between the stack args and the locals on the stack.
440 * it will contain the return address and space to store the old base pointer.
441 * @return The Firm type modeling the ABI between type.
443 static ir_type *ia32_abi_get_between_type(void *self)
445 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
446 static ir_type *omit_fp_between_type = NULL;
447 static ir_type *between_type = NULL;
449 ia32_abi_env_t *env = self;
451 if ( !between_type) {
453 entity *ret_addr_ent;
454 entity *omit_fp_ret_addr_ent;
456 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_P);
457 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_P);
459 between_type = new_type_struct(IDENT("ia32_between_type"));
460 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
461 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
463 set_entity_offset_bytes(old_bp_ent, 0);
464 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
465 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
466 set_type_state(between_type, layout_fixed);
468 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
469 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
471 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
472 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
473 set_type_state(omit_fp_between_type, layout_fixed);
476 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
481 * Get the estimated cycle count for @p irn.
483 * @param self The this pointer.
484 * @param irn The node.
486 * @return The estimated cycle count for this operation
488 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
491 switch (get_ia32_irn_opcode(irn)) {
493 case iro_ia32_DivMod:
498 case iro_ia32_l_Load:
508 case iro_ia32_xStore:
509 case iro_ia32_l_Store:
511 case iro_ia32_Store8Bit:
519 case iro_ia32_l_MulS:
532 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
534 * @param irn The original operation
535 * @param i Index of the argument we want the inverse operation to yield
536 * @param inverse struct to be filled with the resulting inverse op
537 * @param obstack The obstack to use for allocation of the returned nodes array
538 * @return The inverse operation or NULL if operation invertible
540 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
543 ir_node *block, *noreg, *nomem;
546 /* we cannot invert non-ia32 irns */
547 if (! is_ia32_irn(irn))
550 /* operand must always be a real operand (not base, index or mem) */
551 if (i != 2 && i != 3)
554 /* we don't invert address mode operations */
555 if (get_ia32_op_type(irn) != ia32_Normal)
558 irg = get_irn_irg(irn);
559 block = get_nodes_block(irn);
560 mode = get_ia32_res_mode(irn);
561 noreg = get_irn_n(irn, 0);
562 nomem = new_r_NoMem(irg);
564 /* initialize structure */
565 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
569 switch (get_ia32_irn_opcode(irn)) {
571 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
572 /* we have an add with a const here */
573 /* invers == add with negated const */
574 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
575 pnc = pn_ia32_Add_res;
577 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
578 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
579 set_ia32_commutative(inverse->nodes[0]);
581 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
582 /* we have an add with a symconst here */
583 /* invers == sub with const */
584 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
585 pnc = pn_ia32_Sub_res;
587 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
590 /* normal add: inverse == sub */
591 ir_node *proj = ia32_get_res_proj(irn);
594 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
595 pnc = pn_ia32_Sub_res;
600 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
601 /* we have a sub with a const/symconst here */
602 /* invers == add with this const */
603 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
604 pnc = pn_ia32_Add_res;
605 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
606 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
610 ir_node *proj = ia32_get_res_proj(irn);
614 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
617 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
619 pnc = pn_ia32_Sub_res;
624 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
625 /* xor with const: inverse = xor */
626 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
627 pnc = pn_ia32_Eor_res;
628 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
629 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
633 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
634 pnc = pn_ia32_Eor_res;
639 ir_node *proj = ia32_get_res_proj(irn);
642 inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, proj, nomem);
643 pnc = pn_ia32_Not_res;
647 case iro_ia32_Minus: {
648 ir_node *proj = ia32_get_res_proj(irn);
651 inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, proj, nomem);
652 pnc = pn_ia32_Minus_res;
657 /* inverse operation not supported */
661 set_ia32_res_mode(inverse->nodes[0], mode);
662 inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
667 static const be_abi_callbacks_t ia32_abi_callbacks = {
670 ia32_abi_get_between_type,
671 ia32_abi_dont_save_regs,
676 /* fill register allocator interface */
678 static const arch_irn_ops_if_t ia32_irn_ops_if = {
679 ia32_get_irn_reg_req,
684 ia32_get_frame_entity,
687 ia32_get_op_estimated_cost
690 ia32_irn_ops_t ia32_irn_ops = {
697 /**************************************************
700 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
701 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
702 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
703 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
706 **************************************************/
709 * Transforms the standard firm graph into
712 static void ia32_prepare_graph(void *self) {
713 ia32_code_gen_t *cg = self;
714 dom_front_info_t *dom;
715 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
717 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
719 /* 1st: transform constants and psi condition trees */
720 ia32_pre_transform_phase(cg);
722 /* 2nd: transform all remaining nodes */
723 ia32_register_transformers();
724 dom = be_compute_dominance_frontiers(cg->irg);
725 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
726 be_free_dominance_frontiers(dom);
729 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
731 /* 3rd: optimize address mode */
732 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
733 ia32_optimize_addressmode(cg);
736 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
738 DEBUG_ONLY(cg->mod = old_mod;)
742 * Dummy functions for hooks we don't need but which must be filled.
744 static void ia32_before_sched(void *self) {
747 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
755 mode = get_irn_mode(irn);
757 /* check if we already saw this node or the node has more than one user */
758 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1)
761 /* mark irn visited */
762 bitset_add_irn(already_visited, irn);
764 /* non-Tuple nodes with one user: ok, return */
765 if (get_irn_n_edges(irn) >= 1 && mode != mode_T)
768 /* tuple node has one user which is not the mem proj-> ok */
769 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
770 mem_proj = get_proj_for_mode(irn, mode_M);
775 for (i = get_irn_arity(irn) - 1; i >= 0; i--) {
776 ir_node *pred = get_irn_n(irn, i);
778 /* do not follow memory edges or we will accidentally remove stores */
779 if (is_Proj(pred) && get_irn_mode(pred) == mode_M)
782 set_irn_n(irn, i, new_Bad());
785 The current node is about to be removed: if the predecessor
786 has only this node as user, it need to be removed as well.
788 if (get_irn_n_edges(pred) <= 1)
789 remove_unused_nodes(pred, already_visited);
792 if (sched_is_scheduled(irn))
796 static void remove_unused_loads_walker(ir_node *irn, void *env) {
797 bitset_t *already_visited = env;
798 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
799 remove_unused_nodes(irn, env);
803 * Called before the register allocator.
804 * Calculate a block schedule here. We need it for the x87
805 * simulator and the emitter.
807 static void ia32_before_ra(void *self) {
808 ia32_code_gen_t *cg = self;
809 bitset_t *already_visited = bitset_irg_malloc(cg->irg);
811 cg->blk_sched = sched_create_block_schedule(cg->irg);
815 There are sometimes unused loads, only pinned by memory.
816 We need to remove those Loads and all other nodes which won't be used
817 after removing the Load from schedule.
819 irg_walk_graph(cg->irg, remove_unused_loads_walker, NULL, already_visited);
820 bitset_free(already_visited);
825 * Transforms a be node into a Load.
827 static void transform_to_Load(ia32_transform_env_t *env) {
828 ir_node *irn = env->irn;
829 entity *ent = be_get_frame_entity(irn);
830 ir_mode *mode = env->mode;
831 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
832 ir_node *nomem = new_rd_NoMem(env->irg);
833 ir_node *sched_point = NULL;
834 ir_node *ptr = get_irn_n(irn, 0);
835 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
836 ir_node *new_op, *proj;
837 const arch_register_t *reg;
839 if (sched_is_scheduled(irn)) {
840 sched_point = sched_prev(irn);
843 if (mode_is_float(mode)) {
844 if (USE_SSE2(env->cg))
845 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
847 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
850 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
853 set_ia32_am_support(new_op, ia32_am_Source);
854 set_ia32_op_type(new_op, ia32_AddrModeS);
855 set_ia32_am_flavour(new_op, ia32_B);
856 set_ia32_ls_mode(new_op, mode);
857 set_ia32_frame_ent(new_op, ent);
858 set_ia32_use_frame(new_op);
860 DBG_OPT_RELOAD2LD(irn, new_op);
862 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
865 sched_add_after(sched_point, new_op);
866 sched_add_after(new_op, proj);
871 /* copy the register from the old node to the new Load */
872 reg = arch_get_irn_register(env->cg->arch_env, irn);
873 arch_set_irn_register(env->cg->arch_env, new_op, reg);
875 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
881 * Transforms a be node into a Store.
883 static void transform_to_Store(ia32_transform_env_t *env) {
884 ir_node *irn = env->irn;
885 entity *ent = be_get_frame_entity(irn);
886 ir_mode *mode = env->mode;
887 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
888 ir_node *nomem = new_rd_NoMem(env->irg);
889 ir_node *ptr = get_irn_n(irn, 0);
890 ir_node *val = get_irn_n(irn, 1);
891 ir_node *new_op, *proj;
892 ir_node *sched_point = NULL;
894 if (sched_is_scheduled(irn)) {
895 sched_point = sched_prev(irn);
898 if (mode_is_float(mode)) {
899 if (USE_SSE2(env->cg))
900 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
902 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
904 else if (get_mode_size_bits(mode) == 8) {
905 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
908 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
911 set_ia32_am_support(new_op, ia32_am_Dest);
912 set_ia32_op_type(new_op, ia32_AddrModeD);
913 set_ia32_am_flavour(new_op, ia32_B);
914 set_ia32_ls_mode(new_op, mode);
915 set_ia32_frame_ent(new_op, ent);
916 set_ia32_use_frame(new_op);
918 DBG_OPT_SPILL2ST(irn, new_op);
920 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
923 sched_add_after(sched_point, new_op);
927 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
933 * Fix the mode of Spill/Reload
935 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
937 if (mode_is_float(mode)) {
949 * Block-Walker: Calls the transform functions Spill and Reload.
951 static void ia32_after_ra_walker(ir_node *block, void *env) {
952 ir_node *node, *prev;
953 ia32_code_gen_t *cg = env;
954 ia32_transform_env_t tenv;
957 tenv.irg = current_ir_graph;
959 DEBUG_ONLY(tenv.mod = cg->mod;)
961 /* beware: the schedule is changed here */
962 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
963 prev = sched_prev(node);
964 if (be_is_Reload(node)) {
965 /* we always reload the whole register */
966 tenv.dbg = get_irn_dbg_info(node);
968 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
969 transform_to_Load(&tenv);
971 else if (be_is_Spill(node)) {
972 /* we always spill the whole register */
973 tenv.dbg = get_irn_dbg_info(node);
975 tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
976 transform_to_Store(&tenv);
982 * We transform Spill and Reload here. This needs to be done before
983 * stack biasing otherwise we would miss the corrected offset for these nodes.
985 * If x87 instruction should be emitted, run the x87 simulator and patch
986 * the virtual instructions. This must obviously be done after register allocation.
988 static void ia32_after_ra(void *self) {
989 ia32_code_gen_t *cg = self;
990 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
992 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
993 if (cg->used_fp == fp_x87 || cg->force_sim) {
994 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
1000 * Emits the code, closes the output file and frees
1001 * the code generator interface.
1003 static void ia32_codegen(void *self) {
1004 ia32_code_gen_t *cg = self;
1005 ir_graph *irg = cg->irg;
1007 ia32_finish_irg(irg, cg);
1009 be_dump(irg, "-finished", dump_ir_block_graph_sched);
1010 ia32_gen_routine(cg->isa->out, irg, cg);
1014 /* remove it from the isa */
1017 /* de-allocate code generator */
1018 del_set(cg->reg_set);
1023 static void *ia32_cg_init(const be_irg_t *birg);
1025 static const arch_code_generator_if_t ia32_code_gen_if = {
1027 NULL, /* before abi introduce hook */
1029 ia32_before_sched, /* before scheduling hook */
1030 ia32_before_ra, /* before register allocation hook */
1031 ia32_after_ra, /* after register allocation hook */
1032 ia32_codegen /* emit && done */
1036 * Initializes a IA32 code generator.
1038 static void *ia32_cg_init(const be_irg_t *birg) {
1039 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1040 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1042 cg->impl = &ia32_code_gen_if;
1043 cg->irg = birg->irg;
1044 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1045 cg->arch_env = birg->main_env->arch_env;
1048 cg->blk_sched = NULL;
1049 cg->fp_to_gp = NULL;
1050 cg->gp_to_fp = NULL;
1051 cg->fp_kind = isa->fp_kind;
1052 cg->used_fp = fp_none;
1053 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1055 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1057 /* copy optimizations from isa for easier access */
1059 cg->arch = isa->arch;
1060 cg->opt_arch = isa->opt_arch;
1066 if (isa->name_obst_size) {
1067 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
1068 isa->name_obst_size = 0;
1069 obstack_free(isa->name_obst, NULL);
1070 obstack_init(isa->name_obst);
1074 cur_reg_set = cg->reg_set;
1076 ia32_irn_ops.cg = cg;
1078 return (arch_code_generator_t *)cg;
1083 /*****************************************************************
1084 * ____ _ _ _____ _____
1085 * | _ \ | | | | |_ _|/ ____| /\
1086 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1087 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1088 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1089 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1091 *****************************************************************/
1094 * Set output modes for GCC
1096 static const tarval_mode_info mo_integer = {
1103 * set the tarval output mode to C-semantics
1105 static void set_tarval_output_modes(void)
1107 set_tarval_mode_output_option(get_modeLs(), &mo_integer);
1108 set_tarval_mode_output_option(get_modeLu(), &mo_integer);
1109 set_tarval_mode_output_option(get_modeIs(), &mo_integer);
1110 set_tarval_mode_output_option(get_modeIu(), &mo_integer);
1111 set_tarval_mode_output_option(get_modeHs(), &mo_integer);
1112 set_tarval_mode_output_option(get_modeHu(), &mo_integer);
1113 set_tarval_mode_output_option(get_modeBs(), &mo_integer);
1114 set_tarval_mode_output_option(get_modeBu(), &mo_integer);
1115 set_tarval_mode_output_option(get_modeC(), &mo_integer);
1116 set_tarval_mode_output_option(get_modeU(), &mo_integer);
1117 set_tarval_mode_output_option(get_modeIu(), &mo_integer);
1122 * The template that generates a new ISA object.
1123 * Note that this template can be changed by command line
1126 static ia32_isa_t ia32_isa_template = {
1128 &ia32_isa_if, /* isa interface implementation */
1129 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1130 &ia32_gp_regs[REG_EBP], /* base pointer register */
1131 -1, /* stack direction */
1133 NULL, /* 16bit register names */
1134 NULL, /* 8bit register names */
1138 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1139 IA32_OPT_DOAM | /* optimize address mode default: on */
1140 IA32_OPT_LEA | /* optimize for LEAs default: on */
1141 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1142 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1143 IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
1144 arch_pentium_4, /* instruction architecture */
1145 arch_pentium_4, /* optimize for architecture */
1146 fp_sse2, /* use sse2 unit */
1147 NULL, /* current code generator */
1149 NULL, /* name obstack */
1150 0 /* name obst size */
1155 * Initializes the backend ISA.
1157 static void *ia32_init(FILE *file_handle) {
1158 static int inited = 0;
1164 set_tarval_output_modes();
1166 isa = xmalloc(sizeof(*isa));
1167 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1169 ia32_register_init(isa);
1170 ia32_create_opcodes();
1172 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1173 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1174 /* no SSE2 for these cpu's */
1175 isa->fp_kind = fp_x87;
1177 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1178 /* Pentium 4 don't like inc and dec instructions */
1179 isa->opt &= ~IA32_OPT_INCDEC;
1182 isa->regs_16bit = pmap_create();
1183 isa->regs_8bit = pmap_create();
1184 isa->types = pmap_create();
1185 isa->tv_ent = pmap_create();
1186 isa->out = file_handle;
1188 ia32_build_16bit_reg_map(isa->regs_16bit);
1189 ia32_build_8bit_reg_map(isa->regs_8bit);
1191 /* patch register names of x87 registers */
1193 ia32_st_regs[0].name = "st";
1194 ia32_st_regs[1].name = "st(1)";
1195 ia32_st_regs[2].name = "st(2)";
1196 ia32_st_regs[3].name = "st(3)";
1197 ia32_st_regs[4].name = "st(4)";
1198 ia32_st_regs[5].name = "st(5)";
1199 ia32_st_regs[6].name = "st(6)";
1200 ia32_st_regs[7].name = "st(7)";
1204 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1205 obstack_init(isa->name_obst);
1206 isa->name_obst_size = 0;
1209 ia32_handle_intrinsics();
1210 ia32_switch_section(NULL, NO_SECTION);
1211 fprintf(isa->out, "\t.intel_syntax\n");
1221 * Closes the output file and frees the ISA structure.
1223 static void ia32_done(void *self) {
1224 ia32_isa_t *isa = self;
1226 /* emit now all global declarations */
1227 ia32_gen_decls(isa->out);
1229 pmap_destroy(isa->regs_16bit);
1230 pmap_destroy(isa->regs_8bit);
1231 pmap_destroy(isa->tv_ent);
1232 pmap_destroy(isa->types);
1235 //printf("name obst size = %d bytes\n", isa->name_obst_size);
1236 obstack_free(isa->name_obst, NULL);
1244 * Return the number of register classes for this architecture.
1245 * We report always these:
1246 * - the general purpose registers
1247 * - the SSE floating point register set
1248 * - the virtual floating point registers
1250 static int ia32_get_n_reg_class(const void *self) {
1255 * Return the register class for index i.
1257 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1258 const ia32_isa_t *isa = self;
1259 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1261 return &ia32_reg_classes[CLASS_ia32_gp];
1263 return &ia32_reg_classes[CLASS_ia32_xmm];
1265 return &ia32_reg_classes[CLASS_ia32_vfp];
1269 * Get the register class which shall be used to store a value of a given mode.
1270 * @param self The this pointer.
1271 * @param mode The mode in question.
1272 * @return A register class which can hold values of the given mode.
1274 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1275 const ia32_isa_t *isa = self;
1276 if (mode_is_float(mode)) {
1277 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1280 return &ia32_reg_classes[CLASS_ia32_gp];
1284 * Get the ABI restrictions for procedure calls.
1285 * @param self The this pointer.
1286 * @param method_type The type of the method (procedure) in question.
1287 * @param abi The abi object to be modified
1289 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1290 const ia32_isa_t *isa = self;
1293 unsigned cc = get_method_calling_convention(method_type);
1294 int n = get_method_n_params(method_type);
1297 int i, ignore_1, ignore_2;
1299 const arch_register_t *reg;
1300 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1302 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1304 /* set abi flags for calls */
1305 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1306 call_flags.bits.store_args_sequential = use_push;
1307 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1308 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1309 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1311 /* set stack parameter passing style */
1312 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1314 /* collect the mode for each type */
1315 modes = alloca(n * sizeof(modes[0]));
1317 for (i = 0; i < n; i++) {
1318 tp = get_method_param_type(method_type, i);
1319 modes[i] = get_type_mode(tp);
1322 /* set register parameters */
1323 if (cc & cc_reg_param) {
1324 /* determine the number of parameters passed via registers */
1325 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1327 /* loop over all parameters and set the register requirements */
1328 for (i = 0; i <= biggest_n; i++) {
1329 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1330 assert(reg && "kaputt");
1331 be_abi_call_param_reg(abi, i, reg);
1338 /* set stack parameters */
1339 for (i = stack_idx; i < n; i++) {
1340 be_abi_call_param_stack(abi, i, 1, 0, 0);
1344 /* set return registers */
1345 n = get_method_n_ress(method_type);
1347 assert(n <= 2 && "more than two results not supported");
1349 /* In case of 64bit returns, we will have two 32bit values */
1351 tp = get_method_res_type(method_type, 0);
1352 mode = get_type_mode(tp);
1354 assert(!mode_is_float(mode) && "two FP results not supported");
1356 tp = get_method_res_type(method_type, 1);
1357 mode = get_type_mode(tp);
1359 assert(!mode_is_float(mode) && "two FP results not supported");
1361 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1362 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1365 const arch_register_t *reg;
1367 tp = get_method_res_type(method_type, 0);
1368 assert(is_atomic_type(tp));
1369 mode = get_type_mode(tp);
1371 reg = mode_is_float(mode) ?
1372 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1373 &ia32_gp_regs[REG_EAX];
1375 be_abi_call_res_reg(abi, 0, reg);
1380 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1381 return &ia32_irn_ops;
1384 const arch_irn_handler_t ia32_irn_handler = {
1388 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1389 return &ia32_irn_handler;
1392 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1393 return is_ia32_irn(irn) ? 1 : -1;
1397 * Initializes the code generator interface.
1399 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1400 return &ia32_code_gen_if;
1403 list_sched_selector_t ia32_sched_selector;
1406 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1408 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1409 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1410 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1411 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1412 return &ia32_sched_selector;
1416 * Returns the necessary byte alignment for storing a register of given class.
1418 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1419 ir_mode *mode = arch_register_class_mode(cls);
1420 int bytes = get_mode_size_bytes(mode);
1422 if (mode_is_float(mode) && bytes > 8)
1427 static ia32_intrinsic_env_t intrinsic_env = { NULL, NULL };
1430 * Returns the libFirm configuration parameter for this backend.
1432 static const backend_params *ia32_get_libfirm_params(void) {
1433 static const arch_dep_params_t ad = {
1434 1, /* also use subs */
1435 4, /* maximum shifts */
1436 31, /* maximum shift amount */
1438 1, /* allow Mulhs */
1439 1, /* allow Mulus */
1440 32 /* Mulh allowed up to 32 bit */
1442 static backend_params p = {
1443 NULL, /* no additional opcodes */
1444 NULL, /* will be set later */
1445 1, /* need dword lowering */
1446 ia32_create_intrinsic_fkt,
1447 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1455 /* instruction set architectures. */
1456 static const lc_opt_enum_int_items_t arch_items[] = {
1457 { "386", arch_i386, },
1458 { "486", arch_i486, },
1459 { "pentium", arch_pentium, },
1460 { "586", arch_pentium, },
1461 { "pentiumpro", arch_pentium_pro, },
1462 { "686", arch_pentium_pro, },
1463 { "pentiummmx", arch_pentium_mmx, },
1464 { "pentium2", arch_pentium_2, },
1465 { "p2", arch_pentium_2, },
1466 { "pentium3", arch_pentium_3, },
1467 { "p3", arch_pentium_3, },
1468 { "pentium4", arch_pentium_4, },
1469 { "p4", arch_pentium_4, },
1470 { "pentiumm", arch_pentium_m, },
1471 { "pm", arch_pentium_m, },
1472 { "core", arch_core, },
1474 { "athlon", arch_athlon, },
1475 { "athlon64", arch_athlon_64, },
1476 { "opteron", arch_opteron, },
1480 static lc_opt_enum_int_var_t arch_var = {
1481 &ia32_isa_template.arch, arch_items
1484 static lc_opt_enum_int_var_t opt_arch_var = {
1485 &ia32_isa_template.opt_arch, arch_items
1488 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1490 { "sse2", fp_sse2 },
1494 static lc_opt_enum_int_var_t fp_unit_var = {
1495 &ia32_isa_template.fp_kind, fp_unit_items
1498 static const lc_opt_enum_int_items_t gas_items[] = {
1499 { "linux", ASM_LINUX_GAS },
1500 { "mingw", ASM_MINGW_GAS },
1504 static lc_opt_enum_int_var_t gas_var = {
1505 (int *)&asm_flavour, gas_items
1508 static const lc_opt_table_entry_t ia32_options[] = {
1509 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1510 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1511 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1512 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1513 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1514 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1515 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1516 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1517 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1522 * Register command line options for the ia32 backend.
1526 * ia32-arch=arch create instruction for arch
1527 * ia32-opt=arch optimize for run on arch
1528 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1529 * ia32-incdec optimize for inc/dec
1530 * ia32-noaddrmode do not use address mode
1531 * ia32-nolea do not optimize for LEAs
1532 * ia32-noplacecnst do not place constants,
1533 * ia32-noimmop no operations with immediates
1534 * ia32-noextbb do not use extended basic block scheduling
1535 * ia32-gasmode set the GAS compatibility mode
1537 static void ia32_register_options(lc_opt_entry_t *ent)
1539 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1540 lc_opt_add_table(be_grp_ia32, ia32_options);
1542 #endif /* WITH_LIBCORE */
1544 const arch_isa_if_t ia32_isa_if = {
1547 ia32_get_n_reg_class,
1549 ia32_get_reg_class_for_mode,
1551 ia32_get_irn_handler,
1552 ia32_get_code_generator_if,
1553 ia32_get_list_sched_selector,
1554 ia32_get_reg_class_alignment,
1555 ia32_get_libfirm_params,
1557 ia32_register_options