2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
30 #include <libcore/lc_opts.h>
31 #include <libcore/lc_opts_enum.h>
35 #include "pseudo_irg.h"
39 #include "iredges_t.h"
52 #include "../beirg_t.h"
53 #include "../benode_t.h"
54 #include "../belower.h"
55 #include "../besched_t.h"
58 #include "../beirgmod.h"
59 #include "../be_dbgout.h"
60 #include "../beblocksched.h"
61 #include "../bemachine.h"
62 #include "../beilpsched.h"
63 #include "../bespillslots.h"
64 #include "../bemodule.h"
65 #include "../begnuas.h"
66 #include "../bestate.h"
68 #include "bearch_ia32_t.h"
70 #include "ia32_new_nodes.h"
71 #include "gen_ia32_regalloc_if.h"
72 #include "gen_ia32_machine.h"
73 #include "ia32_transform.h"
74 #include "ia32_emitter.h"
75 #include "ia32_map_regs.h"
76 #include "ia32_optimize.h"
78 #include "ia32_dbg_stat.h"
79 #include "ia32_finish.h"
80 #include "ia32_util.h"
83 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
86 static set *cur_reg_set = NULL;
88 ir_mode *mode_fpcw = NULL;
90 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
92 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
93 create_const_node_func func,
94 const arch_register_t* reg)
101 block = get_irg_start_block(cg->irg);
102 res = func(NULL, cg->irg, block);
103 arch_set_irn_register(cg->arch_env, res, reg);
106 add_irn_dep(get_irg_end(cg->irg), res);
107 /* add_irn_dep(get_irg_start(cg->irg), res); */
112 /* Creates the unique per irg GP NoReg node. */
113 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
114 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
115 &ia32_gp_regs[REG_GP_NOREG]);
118 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
119 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
120 &ia32_vfp_regs[REG_VFP_NOREG]);
123 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
124 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
125 &ia32_xmm_regs[REG_XMM_NOREG]);
128 /* Creates the unique per irg FP NoReg node. */
129 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
130 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
133 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
134 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
135 &ia32_gp_regs[REG_GP_UKNWN]);
138 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
139 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
140 &ia32_vfp_regs[REG_VFP_UKNWN]);
143 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
144 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
145 &ia32_xmm_regs[REG_XMM_UKNWN]);
148 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
149 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
150 &ia32_fp_cw_regs[REG_FPCW]);
155 * Returns gp_noreg or fp_noreg, depending in input requirements.
157 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
158 const arch_register_req_t *req;
160 req = arch_get_register_req(cg->arch_env, irn, pos);
161 assert(req != NULL && "Missing register requirements");
162 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
163 return ia32_new_NoReg_gp(cg);
165 return ia32_new_NoReg_fp(cg);
168 /**************************************************
171 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
172 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
173 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
174 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
177 **************************************************/
180 * Return register requirements for an ia32 node.
181 * If the node returns a tuple (mode_T) then the proj's
182 * will be asked for this information.
184 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
187 long node_pos = pos == -1 ? 0 : pos;
188 ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
191 if (is_Block(node) || mode == mode_X) {
192 return arch_no_register_req;
195 if (mode == mode_T && pos < 0) {
196 return arch_no_register_req;
201 return arch_no_register_req;
204 return arch_no_register_req;
207 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
208 node = skip_Proj_const(node);
211 if (is_ia32_irn(node)) {
212 const arch_register_req_t *req;
214 req = get_ia32_in_req(node, pos);
216 req = get_ia32_out_req(node, node_pos);
223 /* unknowns should be transformed already */
224 assert(!is_Unknown(node));
226 return arch_no_register_req;
229 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
233 if (get_irn_mode(irn) == mode_X) {
238 pos = get_Proj_proj(irn);
239 irn = skip_Proj(irn);
242 if (is_ia32_irn(irn)) {
243 const arch_register_t **slots;
245 slots = get_ia32_slots(irn);
248 ia32_set_firm_reg(irn, reg, cur_reg_set);
252 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
254 const arch_register_t *reg = NULL;
259 if (get_irn_mode(irn) == mode_X) {
263 pos = get_Proj_proj(irn);
264 irn = skip_Proj_const(irn);
267 if (is_ia32_irn(irn)) {
268 const arch_register_t **slots;
269 slots = get_ia32_slots(irn);
272 reg = ia32_get_firm_reg(irn, cur_reg_set);
278 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
279 arch_irn_class_t classification = arch_irn_class_normal;
282 irn = skip_Proj_const(irn);
285 classification |= arch_irn_class_branch;
287 if (! is_ia32_irn(irn))
288 return classification & ~arch_irn_class_normal;
290 if (is_ia32_Cnst(irn))
291 classification |= arch_irn_class_const;
294 classification |= arch_irn_class_load;
297 classification |= arch_irn_class_store;
299 if (is_ia32_need_stackent(irn))
300 classification |= arch_irn_class_reload;
302 return classification;
305 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
306 arch_irn_flags_t flags = arch_irn_flags_none;
310 return arch_irn_flags_ignore;
312 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
313 ir_node *pred = get_Proj_pred(irn);
315 if(is_ia32_irn(pred)) {
316 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
322 if (is_ia32_irn(irn)) {
323 flags |= get_ia32_flags(irn);
330 * The IA32 ABI callback object.
333 be_abi_call_flags_bits_t flags; /**< The call flags. */
334 const arch_isa_t *isa; /**< The ISA handle. */
335 const arch_env_t *aenv; /**< The architecture environment. */
336 ir_graph *irg; /**< The associated graph. */
339 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
341 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
344 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
346 set_ia32_frame_ent(irn, ent);
349 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
350 const ia32_irn_ops_t *ops = self;
352 if (get_ia32_frame_ent(irn)) {
353 ia32_am_flavour_t am_flav;
355 if (is_ia32_Pop(irn)) {
356 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
358 /* Pop nodes modify the stack pointer before calculating the destination
359 * address, so fix this here
365 am_flav = get_ia32_am_flavour(irn);
367 set_ia32_am_flavour(irn, am_flav);
369 add_ia32_am_offs_int(irn, bias);
373 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
376 long proj = get_Proj_proj(irn);
377 ir_node *pred = get_Proj_pred(irn);
379 if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack)
381 if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack)
389 * Put all registers which are saved by the prologue/epilogue in a set.
391 * @param self The callback object.
392 * @param s The result set.
394 static void ia32_abi_dont_save_regs(void *self, pset *s)
396 ia32_abi_env_t *env = self;
397 if(env->flags.try_omit_fp)
398 pset_insert_ptr(s, env->isa->bp);
402 * Generate the routine prologue.
404 * @param self The callback object.
405 * @param mem A pointer to the mem node. Update this if you define new memory.
406 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
408 * @return The register which shall be used as a stack frame base.
410 * All nodes which define registers in @p reg_map must keep @p reg_map current.
412 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
414 ia32_abi_env_t *env = self;
415 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
416 ia32_code_gen_t *cg = isa->cg;
418 if (! env->flags.try_omit_fp) {
419 ir_node *bl = get_irg_start_block(env->irg);
420 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
421 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
422 ir_node *noreg = ia32_new_NoReg_gp(cg);
425 /* ALL nodes representing bp must be set to ignore. */
426 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
429 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
430 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
431 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
433 /* the push must have SP out register */
434 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
435 set_ia32_flags(push, arch_irn_flags_ignore);
437 /* move esp to ebp */
438 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
439 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
440 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
441 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
443 /* beware: the copy must be done before any other sp use */
444 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
445 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
446 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
447 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
449 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
450 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
459 * Generate the routine epilogue.
460 * @param self The callback object.
461 * @param bl The block for the epilog
462 * @param mem A pointer to the mem node. Update this if you define new memory.
463 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
464 * @return The register which shall be used as a stack frame base.
466 * All nodes which define registers in @p reg_map must keep @p reg_map current.
468 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
470 ia32_abi_env_t *env = self;
471 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
472 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
474 if (env->flags.try_omit_fp) {
475 /* simply remove the stack frame here */
476 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
477 add_irn_dep(curr_sp, *mem);
479 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
480 ia32_code_gen_t *cg = isa->cg;
481 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
483 /* gcc always emits a leave at the end of a routine */
484 if (1 || ARCH_AMD(isa->opt_arch)) {
488 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
489 set_ia32_flags(leave, arch_irn_flags_ignore);
490 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
491 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
493 ir_node *noreg = ia32_new_NoReg_gp(cg);
496 /* copy ebp to esp */
497 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
500 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
501 set_ia32_flags(pop, arch_irn_flags_ignore);
502 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
503 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
505 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
507 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
508 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
511 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
512 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
516 * Initialize the callback object.
517 * @param call The call object.
518 * @param aenv The architecture environment.
519 * @param irg The graph with the method.
520 * @return Some pointer. This pointer is passed to all other callback functions as self object.
522 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
524 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
525 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
526 env->flags = fl.bits;
529 env->isa = aenv->isa;
534 * Destroy the callback object.
535 * @param self The callback object.
537 static void ia32_abi_done(void *self) {
542 * Produces the type which sits between the stack args and the locals on the stack.
543 * it will contain the return address and space to store the old base pointer.
544 * @return The Firm type modeling the ABI between type.
546 static ir_type *ia32_abi_get_between_type(void *self)
548 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
549 static ir_type *omit_fp_between_type = NULL;
550 static ir_type *between_type = NULL;
552 ia32_abi_env_t *env = self;
554 if (! between_type) {
555 ir_entity *old_bp_ent;
556 ir_entity *ret_addr_ent;
557 ir_entity *omit_fp_ret_addr_ent;
559 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
560 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
562 between_type = new_type_struct(IDENT("ia32_between_type"));
563 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
564 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
566 set_entity_offset(old_bp_ent, 0);
567 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
568 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
569 set_type_state(between_type, layout_fixed);
571 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
572 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
574 set_entity_offset(omit_fp_ret_addr_ent, 0);
575 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
576 set_type_state(omit_fp_between_type, layout_fixed);
579 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
584 * Get the estimated cycle count for @p irn.
586 * @param self The this pointer.
587 * @param irn The node.
589 * @return The estimated cycle count for this operation
591 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
594 ia32_op_type_t op_tp;
595 const ia32_irn_ops_t *ops = self;
599 if (!is_ia32_irn(irn))
602 assert(is_ia32_irn(irn));
604 cost = get_ia32_latency(irn);
605 op_tp = get_ia32_op_type(irn);
607 if (is_ia32_CopyB(irn)) {
609 if (ARCH_INTEL(ops->cg->arch))
612 else if (is_ia32_CopyB_i(irn)) {
613 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
614 cost = 20 + (int)ceil((4/3) * size);
615 if (ARCH_INTEL(ops->cg->arch))
618 /* in case of address mode operations add additional cycles */
619 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
621 In case of stack access add 5 cycles (we assume stack is in cache),
622 other memory operations cost 20 cycles.
624 cost += is_ia32_use_frame(irn) ? 5 : 20;
631 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
633 * @param irn The original operation
634 * @param i Index of the argument we want the inverse operation to yield
635 * @param inverse struct to be filled with the resulting inverse op
636 * @param obstack The obstack to use for allocation of the returned nodes array
637 * @return The inverse operation or NULL if operation invertible
639 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
643 ir_node *block, *noreg, *nomem;
647 /* we cannot invert non-ia32 irns */
648 if (! is_ia32_irn(irn))
651 /* operand must always be a real operand (not base, index or mem) */
652 if (i != 2 && i != 3)
655 /* we don't invert address mode operations */
656 if (get_ia32_op_type(irn) != ia32_Normal)
659 irg = get_irn_irg(irn);
660 block = get_nodes_block(irn);
661 mode = get_irn_mode(irn);
662 irn_mode = get_irn_mode(irn);
663 noreg = get_irn_n(irn, 0);
664 nomem = new_r_NoMem(irg);
665 dbg = get_irn_dbg_info(irn);
667 /* initialize structure */
668 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
672 switch (get_ia32_irn_opcode(irn)) {
674 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
675 /* we have an add with a const here */
676 /* invers == add with negated const */
677 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
679 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
680 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
681 set_ia32_commutative(inverse->nodes[0]);
683 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
684 /* we have an add with a symconst here */
685 /* invers == sub with const */
686 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
688 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
691 /* normal add: inverse == sub */
692 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
697 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
698 /* we have a sub with a const/symconst here */
699 /* invers == add with this const */
700 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
701 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
702 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
707 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
710 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
716 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
717 /* xor with const: inverse = xor */
718 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
719 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
720 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
724 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
729 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
734 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
739 /* inverse operation not supported */
746 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
748 if(mode_is_float(mode))
755 * Get the mode that should be used for spilling value node
757 static ir_mode *get_spill_mode(const ir_node *node)
759 ir_mode *mode = get_irn_mode(node);
760 return get_spill_mode_mode(mode);
764 * Checks whether an addressmode reload for a node with mode mode is compatible
765 * with a spillslot of mode spill_mode
767 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
769 if(mode_is_float(mode)) {
770 return mode == spillmode;
777 * Check if irn can load it's operand at position i from memory (source addressmode).
778 * @param self Pointer to irn ops itself
779 * @param irn The irn to be checked
780 * @param i The operands position
781 * @return Non-Zero if operand can be loaded
783 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
784 ir_node *op = get_irn_n(irn, i);
785 const ir_mode *mode = get_irn_mode(op);
786 const ir_mode *spillmode = get_spill_mode(op);
789 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
790 get_irn_arity(irn) != 5 || /* must be a binary operation */
791 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
792 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
793 ! ia32_is_spillmode_compatible(mode, spillmode) ||
794 (i != 2 && i != 3) || /* a "real" operand position must be requested */
795 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
796 is_ia32_use_frame(irn)) /* must not already use frame */
802 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
803 const ia32_irn_ops_t *ops = self;
804 ia32_code_gen_t *cg = ops->cg;
806 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
809 ir_node *tmp = get_irn_n(irn, 3);
810 set_irn_n(irn, 3, get_irn_n(irn, 2));
811 set_irn_n(irn, 2, tmp);
814 set_ia32_am_support(irn, ia32_am_Source);
815 set_ia32_op_type(irn, ia32_AddrModeS);
816 set_ia32_am_flavour(irn, ia32_B);
817 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
818 set_ia32_use_frame(irn);
819 set_ia32_need_stackent(irn);
821 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
822 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
823 set_irn_n(irn, 4, spill);
825 //FIXME DBG_OPT_AM_S(reload, irn);
828 static const be_abi_callbacks_t ia32_abi_callbacks = {
831 ia32_abi_get_between_type,
832 ia32_abi_dont_save_regs,
837 /* fill register allocator interface */
839 static const arch_irn_ops_if_t ia32_irn_ops_if = {
840 ia32_get_irn_reg_req,
845 ia32_get_frame_entity,
846 ia32_set_frame_entity,
847 ia32_set_frame_offset,
850 ia32_get_op_estimated_cost,
851 ia32_possible_memory_operand,
852 ia32_perform_memory_operand,
855 ia32_irn_ops_t ia32_irn_ops = {
862 /**************************************************
865 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
866 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
867 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
868 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
871 **************************************************/
874 * Transforms the standard firm graph into
877 static void ia32_prepare_graph(void *self) {
878 ia32_code_gen_t *cg = self;
880 /* transform nodes into assembler instructions */
881 ia32_transform_graph(cg);
883 /* do local optimisations (mainly CSE) */
884 local_optimize_graph(cg->irg);
887 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
889 /* optimize address mode */
890 ia32_optimize_graph(cg);
893 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
895 /* do code placement, to optimize the position of constants */
899 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
903 * Dummy functions for hooks we don't need but which must be filled.
905 static void ia32_before_sched(void *self) {
910 * Called before the register allocator.
911 * Calculate a block schedule here. We need it for the x87
912 * simulator and the emitter.
914 static void ia32_before_ra(void *self) {
915 ia32_code_gen_t *cg = self;
917 /* setup fpu rounding modes */
918 ia32_setup_fpu_mode(cg);
923 * Transforms a be_Reload into a ia32 Load.
925 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
926 ir_graph *irg = get_irn_irg(node);
927 dbg_info *dbg = get_irn_dbg_info(node);
928 ir_node *block = get_nodes_block(node);
929 ir_entity *ent = be_get_frame_entity(node);
930 ir_mode *mode = get_irn_mode(node);
931 ir_mode *spillmode = get_spill_mode(node);
932 ir_node *noreg = ia32_new_NoReg_gp(cg);
933 ir_node *sched_point = NULL;
934 ir_node *ptr = get_irg_frame(irg);
935 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
936 ir_node *new_op, *proj;
937 const arch_register_t *reg;
939 if (sched_is_scheduled(node)) {
940 sched_point = sched_prev(node);
943 if (mode_is_float(spillmode)) {
945 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
947 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
949 else if (get_mode_size_bits(spillmode) == 128) {
950 // Reload 128 bit sse registers
951 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
954 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
956 set_ia32_am_support(new_op, ia32_am_Source);
957 set_ia32_op_type(new_op, ia32_AddrModeS);
958 set_ia32_am_flavour(new_op, ia32_B);
959 set_ia32_ls_mode(new_op, spillmode);
960 set_ia32_frame_ent(new_op, ent);
961 set_ia32_use_frame(new_op);
963 DBG_OPT_RELOAD2LD(node, new_op);
965 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
968 sched_add_after(sched_point, new_op);
969 #ifdef SCHEDULE_PROJS
970 sched_add_after(new_op, proj);
975 /* copy the register from the old node to the new Load */
976 reg = arch_get_irn_register(cg->arch_env, node);
977 arch_set_irn_register(cg->arch_env, new_op, reg);
979 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
981 exchange(node, proj);
985 * Transforms a be_Spill node into a ia32 Store.
987 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
988 ir_graph *irg = get_irn_irg(node);
989 dbg_info *dbg = get_irn_dbg_info(node);
990 ir_node *block = get_nodes_block(node);
991 ir_entity *ent = be_get_frame_entity(node);
992 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
993 ir_mode *mode = get_spill_mode(spillval);
994 ir_node *noreg = ia32_new_NoReg_gp(cg);
995 ir_node *nomem = new_rd_NoMem(irg);
996 ir_node *ptr = get_irg_frame(irg);
997 ir_node *val = get_irn_n(node, be_pos_Spill_val);
999 ir_node *sched_point = NULL;
1001 if (sched_is_scheduled(node)) {
1002 sched_point = sched_prev(node);
1005 /* No need to spill unknown values... */
1006 if(is_ia32_Unknown_GP(val) ||
1007 is_ia32_Unknown_VFP(val) ||
1008 is_ia32_Unknown_XMM(val)) {
1013 exchange(node, store);
1017 if (mode_is_float(mode)) {
1019 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
1021 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem, mode);
1022 } else if (get_mode_size_bits(mode) == 128) {
1023 // Spill 128 bit SSE registers
1024 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, val, nomem);
1025 } else if (get_mode_size_bits(mode) == 8) {
1026 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
1028 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
1031 set_ia32_am_support(store, ia32_am_Dest);
1032 set_ia32_op_type(store, ia32_AddrModeD);
1033 set_ia32_am_flavour(store, ia32_B);
1034 set_ia32_ls_mode(store, mode);
1035 set_ia32_frame_ent(store, ent);
1036 set_ia32_use_frame(store);
1037 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1038 DBG_OPT_SPILL2ST(node, store);
1041 sched_add_after(sched_point, store);
1045 exchange(node, store);
1048 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1049 ir_graph *irg = get_irn_irg(node);
1050 dbg_info *dbg = get_irn_dbg_info(node);
1051 ir_node *block = get_nodes_block(node);
1052 ir_node *noreg = ia32_new_NoReg_gp(cg);
1053 ir_node *frame = get_irg_frame(irg);
1055 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
1057 set_ia32_frame_ent(push, ent);
1058 set_ia32_use_frame(push);
1059 set_ia32_op_type(push, ia32_AddrModeS);
1060 set_ia32_am_flavour(push, ia32_B);
1061 set_ia32_ls_mode(push, mode_Is);
1063 sched_add_before(schedpoint, push);
1067 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1068 ir_graph *irg = get_irn_irg(node);
1069 dbg_info *dbg = get_irn_dbg_info(node);
1070 ir_node *block = get_nodes_block(node);
1071 ir_node *noreg = ia32_new_NoReg_gp(cg);
1072 ir_node *frame = get_irg_frame(irg);
1074 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
1076 set_ia32_frame_ent(pop, ent);
1077 set_ia32_use_frame(pop);
1078 set_ia32_op_type(pop, ia32_AddrModeD);
1079 set_ia32_am_flavour(pop, ia32_am_OB);
1080 set_ia32_ls_mode(pop, mode_Is);
1082 sched_add_before(schedpoint, pop);
1087 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos, ir_node *schedpoint) {
1088 ir_graph *irg = get_irn_irg(node);
1089 dbg_info *dbg = get_irn_dbg_info(node);
1090 ir_node *block = get_nodes_block(node);
1091 ir_mode *spmode = mode_Iu;
1092 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1095 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1096 arch_set_irn_register(cg->arch_env, sp, spreg);
1097 #ifdef SCHEDULE_PROJS
1098 sched_add_before(schedpoint, sp);
1105 * Transform memperm, currently we do this the ugly way and produce
1106 * push/pop into/from memory cascades. This is possible without using
1109 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1110 ir_graph *irg = get_irn_irg(node);
1111 ir_node *block = get_nodes_block(node);
1115 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1116 const ir_edge_t *edge;
1117 const ir_edge_t *next;
1120 arity = be_get_MemPerm_entity_arity(node);
1121 pops = alloca(arity * sizeof(pops[0]));
1124 for(i = 0; i < arity; ++i) {
1125 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1126 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1127 ir_type *enttype = get_entity_type(inent);
1128 int entbits = get_type_size_bits(enttype);
1129 int entbits2 = get_type_size_bits(get_entity_type(outent));
1130 ir_node *mem = get_irn_n(node, i + 1);
1133 /* work around cases where entities have different sizes */
1134 if(entbits2 < entbits)
1136 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1138 push = create_push(cg, node, node, sp, mem, inent);
1139 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1141 // add another push after the first one
1142 push = create_push(cg, node, node, sp, mem, inent);
1143 add_ia32_am_offs_int(push, 4);
1144 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1147 set_irn_n(node, i, new_Bad());
1151 for(i = arity - 1; i >= 0; --i) {
1152 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1153 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1154 ir_type *enttype = get_entity_type(outent);
1155 int entbits = get_type_size_bits(enttype);
1156 int entbits2 = get_type_size_bits(get_entity_type(inent));
1159 /* work around cases where entities have different sizes */
1160 if(entbits2 < entbits)
1162 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1164 pop = create_pop(cg, node, node, sp, outent);
1165 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1167 add_ia32_am_offs_int(pop, 4);
1169 // add another pop after the first one
1170 pop = create_pop(cg, node, node, sp, outent);
1171 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1178 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1179 sched_add_before(node, keep);
1181 // exchange memprojs
1182 foreach_out_edge_safe(node, edge, next) {
1183 ir_node *proj = get_edge_src_irn(edge);
1184 int p = get_Proj_proj(proj);
1188 set_Proj_pred(proj, pops[p]);
1189 set_Proj_proj(proj, pn_ia32_Pop_M);
1193 arity = get_irn_arity(node);
1194 for(i = 0; i < arity; ++i) {
1195 set_irn_n(node, i, new_Bad());
1201 * Block-Walker: Calls the transform functions Spill and Reload.
1203 static void ia32_after_ra_walker(ir_node *block, void *env) {
1204 ir_node *node, *prev;
1205 ia32_code_gen_t *cg = env;
1207 /* beware: the schedule is changed here */
1208 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1209 prev = sched_prev(node);
1211 if (be_is_Reload(node)) {
1212 transform_to_Load(cg, node);
1213 } else if (be_is_Spill(node)) {
1214 transform_to_Store(cg, node);
1215 } else if(be_is_MemPerm(node)) {
1216 transform_MemPerm(cg, node);
1222 * Collects nodes that need frame entities assigned.
1224 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1226 be_fec_env_t *env = data;
1228 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1229 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1230 int align = get_mode_size_bytes(mode);
1231 be_node_needs_frame_entity(env, node, mode, align);
1232 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1233 && is_ia32_use_frame(node)) {
1234 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1235 const ir_mode *mode = get_ia32_ls_mode(node);
1236 int align = get_mode_size_bytes(mode);
1237 be_node_needs_frame_entity(env, node, mode, align);
1238 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1239 || is_ia32_vfld(node)) {
1240 const ir_mode *mode = get_ia32_ls_mode(node);
1242 be_node_needs_frame_entity(env, node, mode, align);
1243 } else if(is_ia32_FldCW(node)) {
1244 const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
1246 be_node_needs_frame_entity(env, node, mode, align);
1247 } else if (is_ia32_SetST0(node)) {
1248 const ir_mode *mode = get_ia32_ls_mode(node);
1250 be_node_needs_frame_entity(env, node, mode, align);
1253 assert(is_ia32_St(node) ||
1254 is_ia32_xStoreSimple(node) ||
1255 is_ia32_vfst(node) ||
1256 is_ia32_vfist(node) ||
1257 is_ia32_GetST0(node) ||
1258 is_ia32_FnstCW(node));
1265 * We transform Spill and Reload here. This needs to be done before
1266 * stack biasing otherwise we would miss the corrected offset for these nodes.
1268 static void ia32_after_ra(void *self) {
1269 ia32_code_gen_t *cg = self;
1270 ir_graph *irg = cg->irg;
1271 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1273 /* create and coalesce frame entities */
1274 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1275 be_assign_entities(fec_env);
1276 be_free_frame_entity_coalescer(fec_env);
1278 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1280 ia32_finish_irg(irg, cg);
1284 * Last touchups for the graph before emit: x87 simulation to replace the
1285 * virtual with real x87 instructions, creating a block schedule and peephole
1288 static void ia32_finish(void *self) {
1289 ia32_code_gen_t *cg = self;
1290 ir_graph *irg = cg->irg;
1292 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1293 if (cg->used_fp == fp_x87 || cg->force_sim) {
1294 x87_simulate_graph(cg->arch_env, cg->birg);
1297 /* create block schedule, this also removes empty blocks which might
1298 * produce critical edges */
1299 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1301 /* do peephole optimisations */
1302 ia32_peephole_optimization(irg, cg);
1306 * Emits the code, closes the output file and frees
1307 * the code generator interface.
1309 static void ia32_codegen(void *self) {
1310 ia32_code_gen_t *cg = self;
1311 ir_graph *irg = cg->irg;
1313 ia32_gen_routine(cg, irg);
1317 /* remove it from the isa */
1320 /* de-allocate code generator */
1321 del_set(cg->reg_set);
1325 static void *ia32_cg_init(be_irg_t *birg);
1327 static const arch_code_generator_if_t ia32_code_gen_if = {
1329 NULL, /* before abi introduce hook */
1332 ia32_before_sched, /* before scheduling hook */
1333 ia32_before_ra, /* before register allocation hook */
1334 ia32_after_ra, /* after register allocation hook */
1335 ia32_finish, /* called before codegen */
1336 ia32_codegen /* emit && done */
1340 * Initializes a IA32 code generator.
1342 static void *ia32_cg_init(be_irg_t *birg) {
1343 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1344 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1346 cg->impl = &ia32_code_gen_if;
1347 cg->irg = birg->irg;
1348 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1349 cg->arch_env = birg->main_env->arch_env;
1352 cg->blk_sched = NULL;
1353 cg->fp_kind = isa->fp_kind;
1354 cg->used_fp = fp_none;
1355 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1357 /* copy optimizations from isa for easier access */
1359 cg->arch = isa->arch;
1360 cg->opt_arch = isa->opt_arch;
1366 if (isa->name_obst) {
1367 obstack_free(isa->name_obst, NULL);
1368 obstack_init(isa->name_obst);
1372 cur_reg_set = cg->reg_set;
1374 ia32_irn_ops.cg = cg;
1376 return (arch_code_generator_t *)cg;
1381 /*****************************************************************
1382 * ____ _ _ _____ _____
1383 * | _ \ | | | | |_ _|/ ____| /\
1384 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1385 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1386 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1387 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1389 *****************************************************************/
1392 * Set output modes for GCC
1394 static const tarval_mode_info mo_integer = {
1401 * set the tarval output mode of all integer modes to decimal
1403 static void set_tarval_output_modes(void)
1407 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1408 ir_mode *mode = get_irp_mode(i);
1410 if (mode_is_int(mode))
1411 set_tarval_mode_output_option(mode, &mo_integer);
1415 const arch_isa_if_t ia32_isa_if;
1418 * The template that generates a new ISA object.
1419 * Note that this template can be changed by command line
1422 static ia32_isa_t ia32_isa_template = {
1424 &ia32_isa_if, /* isa interface implementation */
1425 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1426 &ia32_gp_regs[REG_EBP], /* base pointer register */
1427 -1, /* stack direction */
1428 NULL, /* main environment */
1429 7, /* costs for a spill instruction */
1430 5, /* costs for a reload instruction */
1432 NULL_EMITTER, /* emitter environment */
1433 NULL, /* 16bit register names */
1434 NULL, /* 8bit register names */
1435 NULL, /* 8bit register names high */
1439 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1440 IA32_OPT_DOAM | /* optimize address mode default: on */
1441 IA32_OPT_LEA | /* optimize for LEAs default: on */
1442 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1443 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1444 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1445 arch_pentium_4, /* instruction architecture */
1446 arch_pentium_4, /* optimize for architecture */
1447 fp_x87, /* floating point mode */
1448 NULL, /* current code generator */
1450 NULL, /* name obstack */
1451 0 /* name obst size */
1456 * Initializes the backend ISA.
1458 static void *ia32_init(FILE *file_handle) {
1459 static int inited = 0;
1466 set_tarval_output_modes();
1468 isa = xmalloc(sizeof(*isa));
1469 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1471 if(mode_fpcw == NULL) {
1472 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1475 ia32_register_init();
1476 ia32_create_opcodes();
1477 ia32_register_copy_attr_func();
1479 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1480 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1481 /* no SSE2 for these cpu's */
1482 isa->fp_kind = fp_x87;
1484 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1485 /* Pentium 4 don't like inc and dec instructions */
1486 isa->opt &= ~IA32_OPT_INCDEC;
1489 be_emit_init_env(&isa->emit, file_handle);
1490 isa->regs_16bit = pmap_create();
1491 isa->regs_8bit = pmap_create();
1492 isa->regs_8bit_high = pmap_create();
1493 isa->types = pmap_create();
1494 isa->tv_ent = pmap_create();
1495 isa->cpu = ia32_init_machine_description();
1497 ia32_build_16bit_reg_map(isa->regs_16bit);
1498 ia32_build_8bit_reg_map(isa->regs_8bit);
1499 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1502 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1503 obstack_init(isa->name_obst);
1506 ia32_handle_intrinsics();
1508 /* needed for the debug support */
1509 be_gas_emit_switch_section(&isa->emit, GAS_SECTION_TEXT);
1510 be_emit_cstring(&isa->emit, ".Ltext0:\n");
1511 be_emit_write_line(&isa->emit);
1513 /* we mark referenced global entities, so we can only emit those which
1514 * are actually referenced. (Note: you mustn't use the type visited flag
1515 * elsewhere in the backend)
1517 inc_master_type_visited();
1525 * Closes the output file and frees the ISA structure.
1527 static void ia32_done(void *self) {
1528 ia32_isa_t *isa = self;
1530 /* emit now all global declarations */
1531 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
1533 pmap_destroy(isa->regs_16bit);
1534 pmap_destroy(isa->regs_8bit);
1535 pmap_destroy(isa->regs_8bit_high);
1536 pmap_destroy(isa->tv_ent);
1537 pmap_destroy(isa->types);
1540 obstack_free(isa->name_obst, NULL);
1543 be_emit_destroy_env(&isa->emit);
1550 * Return the number of register classes for this architecture.
1551 * We report always these:
1552 * - the general purpose registers
1553 * - the SSE floating point register set
1554 * - the virtual floating point registers
1555 * - the SSE vector register set
1557 static int ia32_get_n_reg_class(const void *self) {
1563 * Return the register class for index i.
1565 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i)
1568 assert(i >= 0 && i < N_CLASSES);
1569 return &ia32_reg_classes[i];
1573 * Get the register class which shall be used to store a value of a given mode.
1574 * @param self The this pointer.
1575 * @param mode The mode in question.
1576 * @return A register class which can hold values of the given mode.
1578 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1579 const ia32_isa_t *isa = self;
1580 if (mode_is_float(mode)) {
1581 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1584 return &ia32_reg_classes[CLASS_ia32_gp];
1588 * Get the ABI restrictions for procedure calls.
1589 * @param self The this pointer.
1590 * @param method_type The type of the method (procedure) in question.
1591 * @param abi The abi object to be modified
1593 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1594 const ia32_isa_t *isa = self;
1599 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1601 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1603 /* set abi flags for calls */
1604 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1605 call_flags.bits.store_args_sequential = use_push;
1606 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1607 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1608 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1610 /* set parameter passing style */
1611 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1613 cc = get_method_calling_convention(method_type);
1614 if (get_method_additional_properties(method_type) & mtp_property_private) {
1615 /* set the calling conventions to register parameter */
1616 cc = (cc & ~cc_bits) | cc_reg_param;
1618 n = get_method_n_params(method_type);
1619 for (i = regnum = 0; i < n; i++) {
1620 const ir_mode *mode;
1621 const arch_register_t *reg = NULL;
1623 tp = get_method_param_type(method_type, i);
1624 mode = get_type_mode(tp);
1626 reg = ia32_get_RegParam_reg(isa->cg, cc, regnum, mode);
1629 be_abi_call_param_reg(abi, i, reg);
1632 be_abi_call_param_stack(abi, i, 4, 0, 0);
1636 /* set return registers */
1637 n = get_method_n_ress(method_type);
1639 assert(n <= 2 && "more than two results not supported");
1641 /* In case of 64bit returns, we will have two 32bit values */
1643 tp = get_method_res_type(method_type, 0);
1644 mode = get_type_mode(tp);
1646 assert(!mode_is_float(mode) && "two FP results not supported");
1648 tp = get_method_res_type(method_type, 1);
1649 mode = get_type_mode(tp);
1651 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1653 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1654 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1657 const arch_register_t *reg;
1659 tp = get_method_res_type(method_type, 0);
1660 assert(is_atomic_type(tp));
1661 mode = get_type_mode(tp);
1663 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1665 be_abi_call_res_reg(abi, 0, reg);
1670 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
1675 return &ia32_irn_ops;
1678 const arch_irn_handler_t ia32_irn_handler = {
1682 const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
1685 return &ia32_irn_handler;
1688 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1692 if(!is_ia32_irn(irn)) {
1696 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1697 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1698 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1699 || is_ia32_Immediate(irn))
1706 * Initializes the code generator interface.
1708 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1711 return &ia32_code_gen_if;
1715 * Returns the estimated execution time of an ia32 irn.
1717 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1718 const arch_env_t *arch_env = env;
1719 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1722 list_sched_selector_t ia32_sched_selector;
1725 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1727 static const list_sched_selector_t *ia32_get_list_sched_selector(
1728 const void *self, list_sched_selector_t *selector)
1731 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1732 ia32_sched_selector.exectime = ia32_sched_exectime;
1733 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1734 return &ia32_sched_selector;
1737 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1744 * Returns the necessary byte alignment for storing a register of given class.
1746 static int ia32_get_reg_class_alignment(const void *self,
1747 const arch_register_class_t *cls)
1749 ir_mode *mode = arch_register_class_mode(cls);
1750 int bytes = get_mode_size_bytes(mode);
1753 if (mode_is_float(mode) && bytes > 8)
1758 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1759 const void *self, const ir_node *irn)
1761 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1762 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1763 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1766 static const be_execution_unit_t *_allowed_units_GP[] = {
1767 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1768 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1769 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1770 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1771 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1772 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1773 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1776 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1777 &be_machine_execution_units_DUMMY[0],
1780 static const be_execution_unit_t **_units_callret[] = {
1781 _allowed_units_BRANCH,
1784 static const be_execution_unit_t **_units_other[] = {
1788 static const be_execution_unit_t **_units_dummy[] = {
1789 _allowed_units_DUMMY,
1792 const be_execution_unit_t ***ret;
1795 if (is_ia32_irn(irn)) {
1796 ret = get_ia32_exec_units(irn);
1798 else if (is_be_node(irn)) {
1799 if (be_is_Call(irn) || be_is_Return(irn)) {
1800 ret = _units_callret;
1802 else if (be_is_Barrier(irn)) {
1817 * Return the abstract ia32 machine.
1819 static const be_machine_t *ia32_get_machine(const void *self) {
1820 const ia32_isa_t *isa = self;
1825 * Return irp irgs in the desired order.
1827 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1835 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1836 * @return 1 if allowed, 0 otherwise
1838 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1840 ir_node *cmp, *cmp_a, *phi;
1843 /* we don't want long long an floating point Psi */
1844 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
1846 if (get_irn_mode(sel) != mode_b)
1849 cmp = get_Proj_pred(sel);
1850 cmp_a = get_Cmp_left(cmp);
1851 mode = get_irn_mode(cmp_a);
1853 if (IS_BAD_PSI_MODE(mode))
1856 /* check the Phi nodes */
1857 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1858 ir_node *pred_i = get_irn_n(phi, i);
1859 ir_node *pred_j = get_irn_n(phi, j);
1860 ir_mode *mode_i = get_irn_mode(pred_i);
1861 ir_mode *mode_j = get_irn_mode(pred_j);
1863 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1867 #undef IS_BAD_PSI_MODE
1872 static ia32_intrinsic_env_t intrinsic_env = {
1873 NULL, /**< the irg, these entities belong to */
1874 NULL, /**< entity for first div operand (move into FPU) */
1875 NULL, /**< entity for second div operand (move into FPU) */
1876 NULL, /**< entity for converts ll -> d */
1877 NULL, /**< entity for converts d -> ll */
1881 * Returns the libFirm configuration parameter for this backend.
1883 static const backend_params *ia32_get_libfirm_params(void) {
1884 static const opt_if_conv_info_t ifconv = {
1885 4, /* maxdepth, doesn't matter for Psi-conversion */
1886 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
1888 static const arch_dep_params_t ad = {
1889 1, /* also use subs */
1890 4, /* maximum shifts */
1891 31, /* maximum shift amount */
1893 1, /* allow Mulhs */
1894 1, /* allow Mulus */
1895 32 /* Mulh allowed up to 32 bit */
1897 static backend_params p = {
1898 1, /* need dword lowering */
1899 1, /* support inline assembly */
1900 NULL, /* no additional opcodes */
1901 NULL, /* will be set later */
1902 ia32_create_intrinsic_fkt,
1903 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1904 NULL, /* will be set later */
1908 p.if_conv_info = &ifconv;
1912 /* instruction set architectures. */
1913 static const lc_opt_enum_int_items_t arch_items[] = {
1914 { "386", arch_i386, },
1915 { "486", arch_i486, },
1916 { "pentium", arch_pentium, },
1917 { "586", arch_pentium, },
1918 { "pentiumpro", arch_pentium_pro, },
1919 { "686", arch_pentium_pro, },
1920 { "pentiummmx", arch_pentium_mmx, },
1921 { "pentium2", arch_pentium_2, },
1922 { "p2", arch_pentium_2, },
1923 { "pentium3", arch_pentium_3, },
1924 { "p3", arch_pentium_3, },
1925 { "pentium4", arch_pentium_4, },
1926 { "p4", arch_pentium_4, },
1927 { "pentiumm", arch_pentium_m, },
1928 { "pm", arch_pentium_m, },
1929 { "core", arch_core, },
1931 { "athlon", arch_athlon, },
1932 { "athlon64", arch_athlon_64, },
1933 { "opteron", arch_opteron, },
1937 static lc_opt_enum_int_var_t arch_var = {
1938 &ia32_isa_template.arch, arch_items
1941 static lc_opt_enum_int_var_t opt_arch_var = {
1942 &ia32_isa_template.opt_arch, arch_items
1945 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1947 { "sse2", fp_sse2 },
1951 static lc_opt_enum_int_var_t fp_unit_var = {
1952 &ia32_isa_template.fp_kind, fp_unit_items
1955 static const lc_opt_enum_int_items_t gas_items[] = {
1956 { "normal", GAS_FLAVOUR_NORMAL },
1957 { "mingw", GAS_FLAVOUR_MINGW },
1961 static lc_opt_enum_int_var_t gas_var = {
1962 (int*) &be_gas_flavour, gas_items
1965 static const lc_opt_table_entry_t ia32_options[] = {
1966 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1967 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1968 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1969 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1970 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1971 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1972 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1973 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
1974 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1978 const arch_isa_if_t ia32_isa_if = {
1981 ia32_get_n_reg_class,
1983 ia32_get_reg_class_for_mode,
1985 ia32_get_irn_handler,
1986 ia32_get_code_generator_if,
1987 ia32_get_list_sched_selector,
1988 ia32_get_ilp_sched_selector,
1989 ia32_get_reg_class_alignment,
1990 ia32_get_libfirm_params,
1991 ia32_get_allowed_execution_units,
1996 void ia32_init_emitter(void);
1997 void ia32_init_finish(void);
1998 void ia32_init_optimize(void);
1999 void ia32_init_transform(void);
2000 void ia32_init_x87(void);
2002 void be_init_arch_ia32(void)
2004 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2005 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2007 lc_opt_add_table(ia32_grp, ia32_options);
2008 be_register_isa_if("ia32", &ia32_isa_if);
2010 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2012 ia32_init_emitter();
2014 ia32_init_optimize();
2015 ia32_init_transform();
2019 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);