2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
31 #include "lc_opts_enum.h"
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
53 #include "iroptimize.h"
54 #include "instrument.h"
57 #include "../beirg_t.h"
58 #include "../benode_t.h"
59 #include "../belower.h"
60 #include "../besched_t.h"
63 #include "../beirgmod.h"
64 #include "../be_dbgout.h"
65 #include "../beblocksched.h"
66 #include "../bemachine.h"
67 #include "../beilpsched.h"
68 #include "../bespillslots.h"
69 #include "../bemodule.h"
70 #include "../begnuas.h"
71 #include "../bestate.h"
72 #include "../beflags.h"
74 #include "bearch_ia32_t.h"
76 #include "ia32_new_nodes.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "gen_ia32_machine.h"
79 #include "ia32_common_transform.h"
80 #include "ia32_transform.h"
81 #include "ia32_emitter.h"
82 #include "ia32_map_regs.h"
83 #include "ia32_optimize.h"
85 #include "ia32_dbg_stat.h"
86 #include "ia32_finish.h"
87 #include "ia32_util.h"
89 #include "ia32_architecture.h"
92 #include "ia32_pbqp_transform.h"
95 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
98 static set *cur_reg_set = NULL;
100 ir_mode *mode_fpcw = NULL;
101 ia32_code_gen_t *ia32_current_cg = NULL;
104 * The environment for the intrinsic mapping.
106 static ia32_intrinsic_env_t intrinsic_env = {
108 NULL, /* the irg, these entities belong to */
109 NULL, /* entity for first div operand (move into FPU) */
110 NULL, /* entity for second div operand (move into FPU) */
111 NULL, /* entity for converts ll -> d */
112 NULL, /* entity for converts d -> ll */
113 NULL, /* entity for __divdi3 library call */
114 NULL, /* entity for __moddi3 library call */
115 NULL, /* entity for __udivdi3 library call */
116 NULL, /* entity for __umoddi3 library call */
117 NULL, /* bias value for conversion from float to unsigned 64 */
121 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
123 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
124 create_const_node_func func,
125 const arch_register_t* reg)
127 ir_node *block, *res;
132 block = get_irg_start_block(cg->irg);
133 res = func(NULL, cg->irg, block);
134 arch_set_irn_register(cg->arch_env, res, reg);
137 add_irn_dep(get_irg_end(cg->irg), res);
138 /* add_irn_dep(get_irg_start(cg->irg), res); */
143 /* Creates the unique per irg GP NoReg node. */
144 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
145 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
146 &ia32_gp_regs[REG_GP_NOREG]);
149 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
150 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
151 &ia32_vfp_regs[REG_VFP_NOREG]);
154 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
155 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
156 &ia32_xmm_regs[REG_XMM_NOREG]);
159 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
160 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
161 &ia32_gp_regs[REG_GP_UKNWN]);
164 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
165 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
166 &ia32_vfp_regs[REG_VFP_UKNWN]);
169 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
170 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
171 &ia32_xmm_regs[REG_XMM_UKNWN]);
174 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
175 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
176 &ia32_fp_cw_regs[REG_FPCW]);
181 * Returns the admissible noreg register node for input register pos of node irn.
183 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
184 const arch_register_req_t *req;
186 req = arch_get_register_req(cg->arch_env, irn, pos);
187 assert(req != NULL && "Missing register requirements");
188 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
189 return ia32_new_NoReg_gp(cg);
191 if (ia32_cg_config.use_sse2) {
192 return ia32_new_NoReg_xmm(cg);
194 return ia32_new_NoReg_vfp(cg);
198 /**************************************************
201 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
202 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
203 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
204 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
207 **************************************************/
210 * Return register requirements for an ia32 node.
211 * If the node returns a tuple (mode_T) then the proj's
212 * will be asked for this information.
214 static const arch_register_req_t *ia32_get_irn_reg_req(const ir_node *node,
217 ir_mode *mode = get_irn_mode(node);
220 if (mode == mode_X || is_Block(node)) {
221 return arch_no_register_req;
224 if (mode == mode_T && pos < 0) {
225 return arch_no_register_req;
228 node_pos = pos == -1 ? 0 : pos;
230 if (mode == mode_M || pos >= 0) {
231 return arch_no_register_req;
234 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
235 node = skip_Proj_const(node);
238 if (is_ia32_irn(node)) {
239 const arch_register_req_t *req;
241 req = get_ia32_in_req(node, pos);
243 req = get_ia32_out_req(node, node_pos);
250 /* unknowns should be transformed already */
251 assert(!is_Unknown(node));
252 return arch_no_register_req;
255 static void ia32_set_irn_reg(ir_node *irn, const arch_register_t *reg)
259 if (get_irn_mode(irn) == mode_X) {
264 pos = get_Proj_proj(irn);
265 irn = skip_Proj(irn);
268 if (is_ia32_irn(irn)) {
269 const arch_register_t **slots;
271 slots = get_ia32_slots(irn);
274 ia32_set_firm_reg(irn, reg, cur_reg_set);
278 static const arch_register_t *ia32_get_irn_reg(const ir_node *irn)
281 const arch_register_t *reg = NULL;
285 if (get_irn_mode(irn) == mode_X) {
289 pos = get_Proj_proj(irn);
290 irn = skip_Proj_const(irn);
293 if (is_ia32_irn(irn)) {
294 const arch_register_t **slots;
295 slots = get_ia32_slots(irn);
296 assert(pos < get_ia32_n_res(irn));
299 reg = ia32_get_firm_reg(irn, cur_reg_set);
305 static arch_irn_class_t ia32_classify(const ir_node *irn) {
306 arch_irn_class_t classification = arch_irn_class_normal;
308 irn = skip_Proj_const(irn);
311 classification |= arch_irn_class_branch;
313 if (! is_ia32_irn(irn))
314 return classification & ~arch_irn_class_normal;
317 classification |= arch_irn_class_load;
320 classification |= arch_irn_class_store;
322 if (is_ia32_need_stackent(irn))
323 classification |= arch_irn_class_reload;
325 return classification;
328 static arch_irn_flags_t ia32_get_flags(const ir_node *irn) {
329 arch_irn_flags_t flags = arch_irn_flags_none;
332 return arch_irn_flags_ignore;
334 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
335 ir_node *pred = get_Proj_pred(irn);
337 if(is_ia32_irn(pred)) {
338 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
344 if (is_ia32_irn(irn)) {
345 flags |= get_ia32_flags(irn);
352 * The IA32 ABI callback object.
355 be_abi_call_flags_bits_t flags; /**< The call flags. */
356 const arch_env_t *aenv; /**< The architecture environment. */
357 ir_graph *irg; /**< The associated graph. */
360 static ir_entity *ia32_get_frame_entity(const ir_node *irn) {
361 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
364 static void ia32_set_frame_entity(ir_node *irn, ir_entity *ent) {
365 set_ia32_frame_ent(irn, ent);
368 static void ia32_set_frame_offset(ir_node *irn, int bias)
370 if (get_ia32_frame_ent(irn) == NULL)
373 if (is_ia32_Pop(irn) || is_ia32_PopMem(irn)) {
374 ia32_code_gen_t *cg = ia32_current_cg;
375 int omit_fp = be_abi_omit_fp(cg->birg->abi);
377 /* Pop nodes modify the stack pointer before calculating the
378 * destination address, so fix this here
383 add_ia32_am_offs_int(irn, bias);
386 static int ia32_get_sp_bias(const ir_node *node)
388 if (is_ia32_Push(node))
391 if (is_ia32_Pop(node) || is_ia32_PopMem(node))
398 * Put all registers which are saved by the prologue/epilogue in a set.
400 * @param self The callback object.
401 * @param s The result set.
403 static void ia32_abi_dont_save_regs(void *self, pset *s)
405 ia32_abi_env_t *env = self;
406 if(env->flags.try_omit_fp)
407 pset_insert_ptr(s, env->aenv->bp);
411 * Generate the routine prologue.
413 * @param self The callback object.
414 * @param mem A pointer to the mem node. Update this if you define new memory.
415 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
417 * @return The register which shall be used as a stack frame base.
419 * All nodes which define registers in @p reg_map must keep @p reg_map current.
421 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
423 ia32_abi_env_t *env = self;
424 ia32_code_gen_t *cg = ia32_current_cg;
425 const arch_env_t *arch_env = env->aenv;
427 if (! env->flags.try_omit_fp) {
428 ir_graph *irg =env->irg;
429 ir_node *bl = get_irg_start_block(irg);
430 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
431 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
432 ir_node *noreg = ia32_new_NoReg_gp(cg);
435 /* ALL nodes representing bp must be set to ignore. */
436 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
439 push = new_rd_ia32_Push(NULL, irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
440 curr_sp = new_r_Proj(irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
441 *mem = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
443 /* the push must have SP out register */
444 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
445 set_ia32_flags(push, arch_irn_flags_ignore);
447 /* move esp to ebp */
448 curr_bp = be_new_Copy(arch_env->bp->reg_class, irg, bl, curr_sp);
449 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), arch_env->bp);
450 arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
451 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
453 /* beware: the copy must be done before any other sp use */
454 curr_sp = be_new_CopyKeep_single(arch_env->sp->reg_class, irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
455 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), arch_env->sp);
456 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
457 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
459 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
460 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
469 * Generate the routine epilogue.
470 * @param self The callback object.
471 * @param bl The block for the epilog
472 * @param mem A pointer to the mem node. Update this if you define new memory.
473 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
474 * @return The register which shall be used as a stack frame base.
476 * All nodes which define registers in @p reg_map must keep @p reg_map current.
478 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
480 ia32_abi_env_t *env = self;
481 const arch_env_t *arch_env = env->aenv;
482 ir_node *curr_sp = be_abi_reg_map_get(reg_map, arch_env->sp);
483 ir_node *curr_bp = be_abi_reg_map_get(reg_map, arch_env->bp);
484 ir_graph *irg = env->irg;
486 if (env->flags.try_omit_fp) {
487 /* simply remove the stack frame here */
488 curr_sp = be_new_IncSP(arch_env->sp, irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
489 add_irn_dep(curr_sp, *mem);
491 ir_mode *mode_bp = arch_env->bp->reg_class->mode;
493 if (ia32_cg_config.use_leave) {
497 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
498 set_ia32_flags(leave, arch_irn_flags_ignore);
499 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
500 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
504 /* the old SP is not needed anymore (kill the proj) */
505 assert(is_Proj(curr_sp));
508 /* copy ebp to esp */
509 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
510 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
511 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
514 pop = new_rd_ia32_Pop(NULL, env->irg, bl, *mem, curr_sp);
515 set_ia32_flags(pop, arch_irn_flags_ignore);
516 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
517 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
519 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
521 arch_set_irn_register(arch_env, curr_sp, arch_env->sp);
522 arch_set_irn_register(arch_env, curr_bp, arch_env->bp);
525 be_abi_reg_map_set(reg_map, arch_env->sp, curr_sp);
526 be_abi_reg_map_set(reg_map, arch_env->bp, curr_bp);
530 * Initialize the callback object.
531 * @param call The call object.
532 * @param aenv The architecture environment.
533 * @param irg The graph with the method.
534 * @return Some pointer. This pointer is passed to all other callback functions as self object.
536 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
538 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
539 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
540 env->flags = fl.bits;
547 * Destroy the callback object.
548 * @param self The callback object.
550 static void ia32_abi_done(void *self) {
555 * Produces the type which sits between the stack args and the locals on the stack.
556 * it will contain the return address and space to store the old base pointer.
557 * @return The Firm type modeling the ABI between type.
559 static ir_type *ia32_abi_get_between_type(void *self)
561 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
562 static ir_type *omit_fp_between_type = NULL;
563 static ir_type *between_type = NULL;
565 ia32_abi_env_t *env = self;
567 if (! between_type) {
568 ir_entity *old_bp_ent;
569 ir_entity *ret_addr_ent;
570 ir_entity *omit_fp_ret_addr_ent;
572 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
573 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
575 between_type = new_type_struct(IDENT("ia32_between_type"));
576 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
577 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
579 set_entity_offset(old_bp_ent, 0);
580 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
581 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
582 set_type_state(between_type, layout_fixed);
584 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
585 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
587 set_entity_offset(omit_fp_ret_addr_ent, 0);
588 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
589 set_type_state(omit_fp_between_type, layout_fixed);
592 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
597 * Get the estimated cycle count for @p irn.
599 * @param self The this pointer.
600 * @param irn The node.
602 * @return The estimated cycle count for this operation
604 static int ia32_get_op_estimated_cost(const ir_node *irn)
607 ia32_op_type_t op_tp;
611 if (!is_ia32_irn(irn))
614 assert(is_ia32_irn(irn));
616 cost = get_ia32_latency(irn);
617 op_tp = get_ia32_op_type(irn);
619 if (is_ia32_CopyB(irn)) {
622 else if (is_ia32_CopyB_i(irn)) {
623 int size = get_ia32_copyb_size(irn);
624 cost = 20 + (int)ceil((4/3) * size);
626 /* in case of address mode operations add additional cycles */
627 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
629 In case of stack access and access to fixed addresses add 5 cycles
630 (we assume they are in cache), other memory operations cost 20
633 if(is_ia32_use_frame(irn) ||
634 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
635 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
646 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
648 * @param irn The original operation
649 * @param i Index of the argument we want the inverse operation to yield
650 * @param inverse struct to be filled with the resulting inverse op
651 * @param obstack The obstack to use for allocation of the returned nodes array
652 * @return The inverse operation or NULL if operation invertible
654 static arch_inverse_t *ia32_get_inverse(const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
658 ir_node *block, *noreg, *nomem;
661 /* we cannot invert non-ia32 irns */
662 if (! is_ia32_irn(irn))
665 /* operand must always be a real operand (not base, index or mem) */
666 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
669 /* we don't invert address mode operations */
670 if (get_ia32_op_type(irn) != ia32_Normal)
673 /* TODO: adjust for new immediates... */
674 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
678 irg = get_irn_irg(irn);
679 block = get_nodes_block(irn);
680 mode = get_irn_mode(irn);
681 irn_mode = get_irn_mode(irn);
682 noreg = get_irn_n(irn, 0);
683 nomem = new_r_NoMem(irg);
684 dbg = get_irn_dbg_info(irn);
686 /* initialize structure */
687 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
691 switch (get_ia32_irn_opcode(irn)) {
694 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
695 /* we have an add with a const here */
696 /* invers == add with negated const */
697 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
699 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
700 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
701 set_ia32_commutative(inverse->nodes[0]);
703 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
704 /* we have an add with a symconst here */
705 /* invers == sub with const */
706 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
708 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
711 /* normal add: inverse == sub */
712 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
719 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
720 /* we have a sub with a const/symconst here */
721 /* invers == add with this const */
722 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
723 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
724 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
728 if (i == n_ia32_binary_left) {
729 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
732 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
740 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
741 /* xor with const: inverse = xor */
742 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
743 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
744 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
748 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
754 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
759 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
764 /* inverse operation not supported */
771 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
773 if(mode_is_float(mode))
780 * Get the mode that should be used for spilling value node
782 static ir_mode *get_spill_mode(const ir_node *node)
784 ir_mode *mode = get_irn_mode(node);
785 return get_spill_mode_mode(mode);
789 * Checks whether an addressmode reload for a node with mode mode is compatible
790 * with a spillslot of mode spill_mode
792 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
794 if(mode_is_float(mode)) {
795 return mode == spillmode;
802 * Check if irn can load its operand at position i from memory (source addressmode).
803 * @param self Pointer to irn ops itself
804 * @param irn The irn to be checked
805 * @param i The operands position
806 * @return Non-Zero if operand can be loaded
808 static int ia32_possible_memory_operand(const ir_node *irn, unsigned int i) {
809 ir_node *op = get_irn_n(irn, i);
810 const ir_mode *mode = get_irn_mode(op);
811 const ir_mode *spillmode = get_spill_mode(op);
814 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
815 ! is_ia32_irn(irn) || /* must be an ia32 irn */
816 get_ia32_am_arity(irn) != ia32_am_binary || /* must be a binary operation TODO is this necessary? */
817 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
818 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
819 ! ia32_is_spillmode_compatible(mode, spillmode) ||
820 is_ia32_use_frame(irn)) /* must not already use frame */
823 if (i == n_ia32_binary_left) {
824 const arch_register_req_t *req;
825 if(!is_ia32_commutative(irn))
827 /* we can't swap left/right for limited registers
828 * (As this (currently) breaks constraint handling copies)
830 req = get_ia32_in_req(irn, n_ia32_binary_left);
831 if (req->type & arch_register_req_type_limited) {
839 static void ia32_perform_memory_operand(ir_node *irn, ir_node *spill,
842 ia32_code_gen_t *cg = ia32_current_cg;
844 assert(ia32_possible_memory_operand(irn, i) && "Cannot perform memory operand change");
846 if (i == n_ia32_binary_left) {
847 ia32_swap_left_right(irn);
850 set_ia32_op_type(irn, ia32_AddrModeS);
851 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
852 set_ia32_use_frame(irn);
853 set_ia32_need_stackent(irn);
855 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
856 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
857 set_irn_n(irn, n_ia32_mem, spill);
859 /* immediates are only allowed on the right side */
860 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
861 ia32_swap_left_right(irn);
865 static const be_abi_callbacks_t ia32_abi_callbacks = {
868 ia32_abi_get_between_type,
869 ia32_abi_dont_save_regs,
874 /* fill register allocator interface */
876 static const arch_irn_ops_t ia32_irn_ops = {
877 ia32_get_irn_reg_req,
882 ia32_get_frame_entity,
883 ia32_set_frame_entity,
884 ia32_set_frame_offset,
887 ia32_get_op_estimated_cost,
888 ia32_possible_memory_operand,
889 ia32_perform_memory_operand,
892 /**************************************************
895 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
896 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
897 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
898 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
901 **************************************************/
903 static ir_entity *mcount = NULL;
905 #define ID(s) new_id_from_chars(s, sizeof(s) - 1)
907 static void ia32_before_abi(void *self) {
908 lower_mode_b_config_t lower_mode_b_config = {
909 mode_Iu, /* lowered mode */
910 mode_Bu, /* prefered mode for set */
911 0, /* don't lower direct compares */
913 ia32_code_gen_t *cg = self;
915 ir_lower_mode_b(cg->irg, &lower_mode_b_config);
917 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
919 if (mcount == NULL) {
920 ir_type *tp = new_type_method(ID("FKT.mcount"), 0, 0);
921 mcount = new_entity(get_glob_type(), ID("mcount"), tp);
922 /* FIXME: enter the right ld_ident here */
923 set_entity_ld_ident(mcount, get_entity_ident(mcount));
924 set_entity_visibility(mcount, visibility_external_allocated);
926 instrument_initcall(cg->irg, mcount);
930 transformer_t be_transformer = TRANSFORMER_DEFAULT;
933 * Transforms the standard firm graph into
936 static void ia32_prepare_graph(void *self) {
937 ia32_code_gen_t *cg = self;
939 /* do local optimizations */
940 optimize_graph_df(cg->irg);
942 /* TODO: we often have dead code reachable through out-edges here. So for
943 * now we rebuild edges (as we need correct user count for code selection)
946 edges_deactivate(cg->irg);
947 edges_activate(cg->irg);
951 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
953 switch (be_transformer) {
954 case TRANSFORMER_DEFAULT:
955 /* transform remaining nodes into assembler instructions */
956 ia32_transform_graph(cg);
960 case TRANSFORMER_PBQP:
961 // disable CSE, because of two-step node-construction
964 /* transform nodes into assembler instructions by PBQP magic */
965 ia32_transform_graph_by_pbqp(cg);
968 be_dump(cg->irg, "-after_pbqp_transform", dump_ir_block_graph_sched);
973 default: panic("invalid transformer");
976 /* do local optimizations (mainly CSE) */
977 optimize_graph_df(cg->irg);
980 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
982 /* optimize address mode */
983 ia32_optimize_graph(cg);
986 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
988 /* do code placement, to optimize the position of constants */
992 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
996 * Dummy functions for hooks we don't need but which must be filled.
998 static void ia32_before_sched(void *self) {
1002 static void turn_back_am(ir_node *node)
1004 ir_graph *irg = current_ir_graph;
1005 dbg_info *dbgi = get_irn_dbg_info(node);
1006 ir_node *block = get_nodes_block(node);
1007 ir_node *base = get_irn_n(node, n_ia32_base);
1008 ir_node *index = get_irn_n(node, n_ia32_index);
1009 ir_node *mem = get_irn_n(node, n_ia32_mem);
1010 ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
1014 const ir_edge_t *edge;
1016 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1017 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1019 ia32_copy_am_attrs(load, node);
1020 set_irn_n(node, n_ia32_mem, new_NoMem());
1022 switch (get_ia32_am_arity(node)) {
1024 set_irn_n(node, n_ia32_unary_op, load_res);
1027 case ia32_am_binary:
1028 if (is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
1029 assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node) ||
1030 is_ia32_Test(node) || is_ia32_Test8Bit(node));
1031 set_irn_n(node, n_ia32_binary_left, load_res);
1033 set_irn_n(node, n_ia32_binary_right, load_res);
1037 case ia32_am_ternary:
1038 set_irn_n(node, n_ia32_binary_right, load_res);
1043 set_irn_n(node, n_ia32_base, noreg);
1044 set_irn_n(node, n_ia32_index, noreg);
1045 set_ia32_am_offs_int(node, 0);
1046 set_ia32_am_sc(node, NULL);
1047 set_ia32_am_scale(node, 0);
1048 clear_ia32_am_sc_sign(node);
1050 /* rewire mem-proj */
1051 if (get_irn_mode(node) == mode_T) {
1053 foreach_out_edge(node, edge) {
1054 ir_node *out = get_edge_src_irn(edge);
1055 if(get_irn_mode(out) == mode_M) {
1056 assert(mem_proj == NULL);
1061 if(mem_proj != NULL) {
1062 set_Proj_pred(mem_proj, load);
1063 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1067 set_ia32_op_type(node, ia32_Normal);
1068 if (sched_is_scheduled(node))
1069 sched_add_before(node, load);
1072 static ir_node *flags_remat(ir_node *node, ir_node *after)
1074 /* we should turn back source address mode when rematerializing nodes */
1075 ia32_op_type_t type;
1079 if (is_Block(after)) {
1082 block = get_nodes_block(after);
1085 type = get_ia32_op_type(node);
1087 case ia32_AddrModeS:
1091 case ia32_AddrModeD:
1092 /* TODO implement this later... */
1093 panic("found DestAM with flag user %+F this should not happen", node);
1096 default: assert(type == ia32_Normal); break;
1099 copy = exact_copy(node);
1100 set_nodes_block(copy, block);
1101 sched_add_after(after, copy);
1107 * Called before the register allocator.
1108 * Calculate a block schedule here. We need it for the x87
1109 * simulator and the emitter.
1111 static void ia32_before_ra(void *self) {
1112 ia32_code_gen_t *cg = self;
1114 /* setup fpu rounding modes */
1115 ia32_setup_fpu_mode(cg);
1118 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1121 ia32_add_missing_keeps(cg);
1126 * Transforms a be_Reload into a ia32 Load.
1128 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1129 ir_graph *irg = get_irn_irg(node);
1130 dbg_info *dbg = get_irn_dbg_info(node);
1131 ir_node *block = get_nodes_block(node);
1132 ir_entity *ent = be_get_frame_entity(node);
1133 ir_mode *mode = get_irn_mode(node);
1134 ir_mode *spillmode = get_spill_mode(node);
1135 ir_node *noreg = ia32_new_NoReg_gp(cg);
1136 ir_node *sched_point = NULL;
1137 ir_node *ptr = get_irg_frame(irg);
1138 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1139 ir_node *new_op, *proj;
1140 const arch_register_t *reg;
1142 if (sched_is_scheduled(node)) {
1143 sched_point = sched_prev(node);
1146 if (mode_is_float(spillmode)) {
1147 if (ia32_cg_config.use_sse2)
1148 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1150 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1152 else if (get_mode_size_bits(spillmode) == 128) {
1153 /* Reload 128 bit SSE registers */
1154 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1157 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1159 set_ia32_op_type(new_op, ia32_AddrModeS);
1160 set_ia32_ls_mode(new_op, spillmode);
1161 set_ia32_frame_ent(new_op, ent);
1162 set_ia32_use_frame(new_op);
1164 DBG_OPT_RELOAD2LD(node, new_op);
1166 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1169 sched_add_after(sched_point, new_op);
1173 /* copy the register from the old node to the new Load */
1174 reg = arch_get_irn_register(cg->arch_env, node);
1175 arch_set_irn_register(cg->arch_env, new_op, reg);
1177 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1179 exchange(node, proj);
1183 * Transforms a be_Spill node into a ia32 Store.
1185 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1186 ir_graph *irg = get_irn_irg(node);
1187 dbg_info *dbg = get_irn_dbg_info(node);
1188 ir_node *block = get_nodes_block(node);
1189 ir_entity *ent = be_get_frame_entity(node);
1190 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1191 ir_mode *mode = get_spill_mode(spillval);
1192 ir_node *noreg = ia32_new_NoReg_gp(cg);
1193 ir_node *nomem = new_rd_NoMem(irg);
1194 ir_node *ptr = get_irg_frame(irg);
1195 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1197 ir_node *sched_point = NULL;
1199 if (sched_is_scheduled(node)) {
1200 sched_point = sched_prev(node);
1203 /* No need to spill unknown values... */
1204 if(is_ia32_Unknown_GP(val) ||
1205 is_ia32_Unknown_VFP(val) ||
1206 is_ia32_Unknown_XMM(val)) {
1211 exchange(node, store);
1215 if (mode_is_float(mode)) {
1216 if (ia32_cg_config.use_sse2)
1217 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1219 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1220 } else if (get_mode_size_bits(mode) == 128) {
1221 /* Spill 128 bit SSE registers */
1222 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1223 } else if (get_mode_size_bits(mode) == 8) {
1224 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1226 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1229 set_ia32_op_type(store, ia32_AddrModeD);
1230 set_ia32_ls_mode(store, mode);
1231 set_ia32_frame_ent(store, ent);
1232 set_ia32_use_frame(store);
1233 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1234 DBG_OPT_SPILL2ST(node, store);
1237 sched_add_after(sched_point, store);
1241 exchange(node, store);
1244 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1245 ir_graph *irg = get_irn_irg(node);
1246 dbg_info *dbg = get_irn_dbg_info(node);
1247 ir_node *block = get_nodes_block(node);
1248 ir_node *noreg = ia32_new_NoReg_gp(cg);
1249 ir_node *frame = get_irg_frame(irg);
1251 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
1253 set_ia32_frame_ent(push, ent);
1254 set_ia32_use_frame(push);
1255 set_ia32_op_type(push, ia32_AddrModeS);
1256 set_ia32_ls_mode(push, mode_Is);
1258 sched_add_before(schedpoint, push);
1262 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1263 ir_graph *irg = get_irn_irg(node);
1264 dbg_info *dbg = get_irn_dbg_info(node);
1265 ir_node *block = get_nodes_block(node);
1266 ir_node *noreg = ia32_new_NoReg_gp(cg);
1267 ir_node *frame = get_irg_frame(irg);
1269 ir_node *pop = new_rd_ia32_PopMem(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1271 set_ia32_frame_ent(pop, ent);
1272 set_ia32_use_frame(pop);
1273 set_ia32_op_type(pop, ia32_AddrModeD);
1274 set_ia32_ls_mode(pop, mode_Is);
1276 sched_add_before(schedpoint, pop);
1281 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1282 ir_graph *irg = get_irn_irg(node);
1283 dbg_info *dbg = get_irn_dbg_info(node);
1284 ir_node *block = get_nodes_block(node);
1285 ir_mode *spmode = mode_Iu;
1286 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1289 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1290 arch_set_irn_register(cg->arch_env, sp, spreg);
1296 * Transform MemPerm, currently we do this the ugly way and produce
1297 * push/pop into/from memory cascades. This is possible without using
1300 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1301 ir_graph *irg = get_irn_irg(node);
1302 ir_node *block = get_nodes_block(node);
1306 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1307 const ir_edge_t *edge;
1308 const ir_edge_t *next;
1311 arity = be_get_MemPerm_entity_arity(node);
1312 pops = alloca(arity * sizeof(pops[0]));
1315 for(i = 0; i < arity; ++i) {
1316 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1317 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1318 ir_type *enttype = get_entity_type(inent);
1319 unsigned entsize = get_type_size_bytes(enttype);
1320 unsigned entsize2 = get_type_size_bytes(get_entity_type(outent));
1321 ir_node *mem = get_irn_n(node, i + 1);
1324 /* work around cases where entities have different sizes */
1325 if(entsize2 < entsize)
1327 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1329 push = create_push(cg, node, node, sp, mem, inent);
1330 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1332 /* add another push after the first one */
1333 push = create_push(cg, node, node, sp, mem, inent);
1334 add_ia32_am_offs_int(push, 4);
1335 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1338 set_irn_n(node, i, new_Bad());
1342 for(i = arity - 1; i >= 0; --i) {
1343 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1344 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1345 ir_type *enttype = get_entity_type(outent);
1346 unsigned entsize = get_type_size_bytes(enttype);
1347 unsigned entsize2 = get_type_size_bytes(get_entity_type(inent));
1350 /* work around cases where entities have different sizes */
1351 if(entsize2 < entsize)
1353 assert( (entsize == 4 || entsize == 8) && "spillslot on x86 should be 32 or 64 bit");
1355 pop = create_pop(cg, node, node, sp, outent);
1356 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1358 add_ia32_am_offs_int(pop, 4);
1360 /* add another pop after the first one */
1361 pop = create_pop(cg, node, node, sp, outent);
1362 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1369 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1370 sched_add_before(node, keep);
1372 /* exchange memprojs */
1373 foreach_out_edge_safe(node, edge, next) {
1374 ir_node *proj = get_edge_src_irn(edge);
1375 int p = get_Proj_proj(proj);
1379 set_Proj_pred(proj, pops[p]);
1380 set_Proj_proj(proj, pn_ia32_Pop_M);
1383 /* remove memperm */
1384 arity = get_irn_arity(node);
1385 for(i = 0; i < arity; ++i) {
1386 set_irn_n(node, i, new_Bad());
1392 * Block-Walker: Calls the transform functions Spill and Reload.
1394 static void ia32_after_ra_walker(ir_node *block, void *env) {
1395 ir_node *node, *prev;
1396 ia32_code_gen_t *cg = env;
1398 /* beware: the schedule is changed here */
1399 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1400 prev = sched_prev(node);
1402 if (be_is_Reload(node)) {
1403 transform_to_Load(cg, node);
1404 } else if (be_is_Spill(node)) {
1405 transform_to_Store(cg, node);
1406 } else if (be_is_MemPerm(node)) {
1407 transform_MemPerm(cg, node);
1413 * Collects nodes that need frame entities assigned.
1415 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1417 be_fec_env_t *env = data;
1419 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1420 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1421 int align = get_mode_size_bytes(mode);
1422 be_node_needs_frame_entity(env, node, mode, align);
1423 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1424 && is_ia32_use_frame(node)) {
1425 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1426 const ir_mode *mode = get_ia32_ls_mode(node);
1427 const ia32_attr_t *attr = get_ia32_attr_const(node);
1428 int align = get_mode_size_bytes(mode);
1430 if(attr->data.need_64bit_stackent) {
1433 if(attr->data.need_32bit_stackent) {
1436 be_node_needs_frame_entity(env, node, mode, align);
1437 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1438 || is_ia32_vfld(node)) {
1439 const ir_mode *mode = get_ia32_ls_mode(node);
1441 be_node_needs_frame_entity(env, node, mode, align);
1442 } else if(is_ia32_FldCW(node)) {
1443 /* although 2 byte would be enough 4 byte performs best */
1444 const ir_mode *mode = mode_Iu;
1446 be_node_needs_frame_entity(env, node, mode, align);
1449 assert(is_ia32_St(node) ||
1450 is_ia32_xStoreSimple(node) ||
1451 is_ia32_vfst(node) ||
1452 is_ia32_vfist(node) ||
1453 is_ia32_vfisttp(node) ||
1454 is_ia32_FnstCW(node));
1461 * We transform Spill and Reload here. This needs to be done before
1462 * stack biasing otherwise we would miss the corrected offset for these nodes.
1464 static void ia32_after_ra(void *self) {
1465 ia32_code_gen_t *cg = self;
1466 ir_graph *irg = cg->irg;
1467 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1469 /* create and coalesce frame entities */
1470 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1471 be_assign_entities(fec_env);
1472 be_free_frame_entity_coalescer(fec_env);
1474 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1478 * Last touchups for the graph before emit: x87 simulation to replace the
1479 * virtual with real x87 instructions, creating a block schedule and peephole
1482 static void ia32_finish(void *self) {
1483 ia32_code_gen_t *cg = self;
1484 ir_graph *irg = cg->irg;
1486 ia32_finish_irg(irg, cg);
1488 /* we might have to rewrite x87 virtual registers */
1489 if (cg->do_x87_sim) {
1490 x87_simulate_graph(cg->arch_env, cg->birg);
1493 /* do peephole optimisations */
1494 ia32_peephole_optimization(cg);
1496 /* create block schedule, this also removes empty blocks which might
1497 * produce critical edges */
1498 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1502 * Emits the code, closes the output file and frees
1503 * the code generator interface.
1505 static void ia32_codegen(void *self) {
1506 ia32_code_gen_t *cg = self;
1507 ir_graph *irg = cg->irg;
1509 ia32_gen_routine(cg, irg);
1513 /* remove it from the isa */
1516 assert(ia32_current_cg == cg);
1517 ia32_current_cg = NULL;
1519 /* de-allocate code generator */
1520 del_set(cg->reg_set);
1525 * Returns the node representing the PIC base.
1527 static ir_node *ia32_get_pic_base(void *self) {
1529 ia32_code_gen_t *cg = self;
1530 ir_node *get_eip = cg->get_eip;
1531 if (get_eip != NULL)
1534 block = get_irg_start_block(cg->irg);
1535 get_eip = new_rd_ia32_GetEIP(NULL, cg->irg, block);
1536 cg->get_eip = get_eip;
1538 add_irn_dep(get_eip, get_irg_frame(cg->irg));
1543 static void *ia32_cg_init(be_irg_t *birg);
1545 static const arch_code_generator_if_t ia32_code_gen_if = {
1547 ia32_get_pic_base, /* return node used as base in pic code addresses */
1548 ia32_before_abi, /* before abi introduce hook */
1551 ia32_before_sched, /* before scheduling hook */
1552 ia32_before_ra, /* before register allocation hook */
1553 ia32_after_ra, /* after register allocation hook */
1554 ia32_finish, /* called before codegen */
1555 ia32_codegen /* emit && done */
1559 * Initializes a IA32 code generator.
1561 static void *ia32_cg_init(be_irg_t *birg) {
1562 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env;
1563 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1565 cg->impl = &ia32_code_gen_if;
1566 cg->irg = birg->irg;
1567 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1569 cg->arch_env = birg->main_env->arch_env;
1571 cg->blk_sched = NULL;
1572 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1573 cg->gprof = (birg->main_env->options->gprof) ? 1 : 0;
1576 /* Linux gprof implementation needs base pointer */
1577 birg->main_env->options->omit_fp = 0;
1584 if (isa->name_obst) {
1585 obstack_free(isa->name_obst, NULL);
1586 obstack_init(isa->name_obst);
1590 cur_reg_set = cg->reg_set;
1592 assert(ia32_current_cg == NULL);
1593 ia32_current_cg = cg;
1595 return (arch_code_generator_t *)cg;
1600 /*****************************************************************
1601 * ____ _ _ _____ _____
1602 * | _ \ | | | | |_ _|/ ____| /\
1603 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1604 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1605 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1606 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1608 *****************************************************************/
1611 * Set output modes for GCC
1613 static const tarval_mode_info mo_integer = {
1620 * set the tarval output mode of all integer modes to decimal
1622 static void set_tarval_output_modes(void)
1626 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1627 ir_mode *mode = get_irp_mode(i);
1629 if (mode_is_int(mode))
1630 set_tarval_mode_output_option(mode, &mo_integer);
1634 const arch_isa_if_t ia32_isa_if;
1637 * The template that generates a new ISA object.
1638 * Note that this template can be changed by command line
1641 static ia32_isa_t ia32_isa_template = {
1643 &ia32_isa_if, /* isa interface implementation */
1644 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1645 &ia32_gp_regs[REG_EBP], /* base pointer register */
1646 -1, /* stack direction */
1647 4, /* power of two stack alignment, 2^4 == 16 */
1648 NULL, /* main environment */
1649 7, /* costs for a spill instruction */
1650 5, /* costs for a reload instruction */
1652 NULL, /* 16bit register names */
1653 NULL, /* 8bit register names */
1654 NULL, /* 8bit register names high */
1657 NULL, /* current code generator */
1658 NULL, /* abstract machine */
1660 NULL, /* name obstack */
1664 static void init_asm_constraints(void)
1666 be_init_default_asm_constraint_flags();
1668 asm_constraint_flags['a'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1669 asm_constraint_flags['b'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1670 asm_constraint_flags['c'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1671 asm_constraint_flags['d'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1672 asm_constraint_flags['D'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1673 asm_constraint_flags['S'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1674 asm_constraint_flags['Q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1675 asm_constraint_flags['q'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1676 asm_constraint_flags['A'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1677 asm_constraint_flags['l'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1678 asm_constraint_flags['R'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1679 asm_constraint_flags['r'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1680 asm_constraint_flags['p'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1681 asm_constraint_flags['f'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1682 asm_constraint_flags['t'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1683 asm_constraint_flags['u'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1684 asm_constraint_flags['Y'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1685 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_SUPPORTS_REGISTER;
1686 asm_constraint_flags['n'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1687 asm_constraint_flags['g'] = ASM_CONSTRAINT_FLAG_SUPPORTS_IMMEDIATE;
1689 /* no support for autodecrement/autoincrement */
1690 asm_constraint_flags['<'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1691 asm_constraint_flags['>'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1692 /* no float consts */
1693 asm_constraint_flags['E'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1694 asm_constraint_flags['F'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1695 /* makes no sense on x86 */
1696 asm_constraint_flags['s'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1697 /* no support for sse consts yet */
1698 asm_constraint_flags['C'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1699 /* no support for x87 consts yet */
1700 asm_constraint_flags['G'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1701 /* no support for mmx registers yet */
1702 asm_constraint_flags['y'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1703 /* not available in 32bit mode */
1704 asm_constraint_flags['Z'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1705 asm_constraint_flags['e'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1707 /* no code yet to determine register class needed... */
1708 asm_constraint_flags['X'] = ASM_CONSTRAINT_FLAG_NO_SUPPORT;
1712 * Initializes the backend ISA.
1714 static arch_env_t *ia32_init(FILE *file_handle) {
1715 static int inited = 0;
1723 set_tarval_output_modes();
1725 isa = xmalloc(sizeof(*isa));
1726 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1728 if(mode_fpcw == NULL) {
1729 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1732 ia32_register_init();
1733 ia32_create_opcodes(&ia32_irn_ops);
1735 be_emit_init(file_handle);
1736 isa->regs_16bit = pmap_create();
1737 isa->regs_8bit = pmap_create();
1738 isa->regs_8bit_high = pmap_create();
1739 isa->types = pmap_create();
1740 isa->tv_ent = pmap_create();
1741 isa->cpu = ia32_init_machine_description();
1743 ia32_build_16bit_reg_map(isa->regs_16bit);
1744 ia32_build_8bit_reg_map(isa->regs_8bit);
1745 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1748 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1749 obstack_init(isa->name_obst);
1752 /* enter the ISA object into the intrinsic environment */
1753 intrinsic_env.isa = isa;
1754 ia32_handle_intrinsics();
1756 /* emit asm includes */
1757 n = get_irp_n_asms();
1758 for (i = 0; i < n; ++i) {
1759 be_emit_cstring("#APP\n");
1760 be_emit_ident(get_irp_asm(i));
1761 be_emit_cstring("\n#NO_APP\n");
1764 /* needed for the debug support */
1765 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1766 be_emit_cstring(".Ltext0:\n");
1767 be_emit_write_line();
1769 /* we mark referenced global entities, so we can only emit those which
1770 * are actually referenced. (Note: you mustn't use the type visited flag
1771 * elsewhere in the backend)
1773 inc_master_type_visited();
1775 return &isa->arch_env;
1781 * Closes the output file and frees the ISA structure.
1783 static void ia32_done(void *self) {
1784 ia32_isa_t *isa = self;
1786 /* emit now all global declarations */
1787 be_gas_emit_decls(isa->arch_env.main_env, 1);
1789 pmap_destroy(isa->regs_16bit);
1790 pmap_destroy(isa->regs_8bit);
1791 pmap_destroy(isa->regs_8bit_high);
1792 pmap_destroy(isa->tv_ent);
1793 pmap_destroy(isa->types);
1796 obstack_free(isa->name_obst, NULL);
1806 * Return the number of register classes for this architecture.
1807 * We report always these:
1808 * - the general purpose registers
1809 * - the SSE floating point register set
1810 * - the virtual floating point registers
1811 * - the SSE vector register set
1813 static unsigned ia32_get_n_reg_class(const void *self) {
1819 * Return the register class for index i.
1821 static const arch_register_class_t *ia32_get_reg_class(const void *self,
1825 assert(i < N_CLASSES);
1826 return &ia32_reg_classes[i];
1830 * Get the register class which shall be used to store a value of a given mode.
1831 * @param self The this pointer.
1832 * @param mode The mode in question.
1833 * @return A register class which can hold values of the given mode.
1835 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self,
1836 const ir_mode *mode)
1840 if (mode_is_float(mode)) {
1841 return ia32_cg_config.use_sse2 ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1844 return &ia32_reg_classes[CLASS_ia32_gp];
1848 * Get the ABI restrictions for procedure calls.
1849 * @param self The this pointer.
1850 * @param method_type The type of the method (procedure) in question.
1851 * @param abi The abi object to be modified
1853 static void ia32_get_call_abi(const void *self, ir_type *method_type,
1861 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1865 /* set abi flags for calls */
1866 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1867 call_flags.bits.store_args_sequential = 0;
1868 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1869 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1870 call_flags.bits.call_has_imm = 1; /* No call immediates, we handle this by ourselves */
1872 /* set parameter passing style */
1873 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1875 if (get_method_variadicity(method_type) == variadicity_variadic) {
1876 /* pass all parameters of a variadic function on the stack */
1879 cc = get_method_calling_convention(method_type);
1880 if (!(cc & cc_fixed) &&
1881 get_method_additional_properties(method_type) & mtp_property_private &&
1882 ia32_cg_config.optimize_cc) {
1883 /* set the calling conventions to register parameter */
1884 cc = (cc & ~cc_bits) | cc_reg_param;
1888 /* we have to pop the shadow parameter ourself for compound calls */
1889 if( (get_method_calling_convention(method_type) & cc_compound_ret)
1890 && !(cc & cc_reg_param)) {
1891 pop_amount += get_mode_size_bytes(mode_P_data);
1894 n = get_method_n_params(method_type);
1895 for (i = regnum = 0; i < n; i++) {
1897 const arch_register_t *reg = NULL;
1899 tp = get_method_param_type(method_type, i);
1900 mode = get_type_mode(tp);
1902 reg = ia32_get_RegParam_reg(cc, regnum, mode);
1905 be_abi_call_param_reg(abi, i, reg);
1908 /* Micro optimisation: if the mode is shorter than 4 bytes, load 4 bytes.
1909 * movl has a shorter opcode than mov[sz][bw]l */
1910 ir_mode *load_mode = mode;
1913 unsigned size = get_mode_size_bytes(mode);
1915 if (cc & cc_callee_clear_stk) {
1916 pop_amount += (size + 3U) & ~3U;
1919 if (size < 4) load_mode = mode_Iu;
1922 be_abi_call_param_stack(abi, i, load_mode, 4, 0, 0);
1926 be_abi_call_set_pop(abi, pop_amount);
1928 /* set return registers */
1929 n = get_method_n_ress(method_type);
1931 assert(n <= 2 && "more than two results not supported");
1933 /* In case of 64bit returns, we will have two 32bit values */
1935 tp = get_method_res_type(method_type, 0);
1936 mode = get_type_mode(tp);
1938 assert(!mode_is_float(mode) && "two FP results not supported");
1940 tp = get_method_res_type(method_type, 1);
1941 mode = get_type_mode(tp);
1943 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1945 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1946 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1949 const arch_register_t *reg;
1951 tp = get_method_res_type(method_type, 0);
1952 assert(is_atomic_type(tp));
1953 mode = get_type_mode(tp);
1955 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1957 be_abi_call_res_reg(abi, 0, reg);
1961 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1965 if(!is_ia32_irn(irn)) {
1969 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1970 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1971 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1972 || is_ia32_Immediate(irn))
1979 * Initializes the code generator interface.
1981 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1984 return &ia32_code_gen_if;
1988 * Returns the estimated execution time of an ia32 irn.
1990 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1992 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(irn) : 1;
1995 list_sched_selector_t ia32_sched_selector;
1998 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
2000 static const list_sched_selector_t *ia32_get_list_sched_selector(
2001 const void *self, list_sched_selector_t *selector)
2004 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
2005 ia32_sched_selector.exectime = ia32_sched_exectime;
2006 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
2007 return &ia32_sched_selector;
2010 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
2017 * Returns the necessary byte alignment for storing a register of given class.
2019 static int ia32_get_reg_class_alignment(const void *self,
2020 const arch_register_class_t *cls)
2022 ir_mode *mode = arch_register_class_mode(cls);
2023 int bytes = get_mode_size_bytes(mode);
2026 if (mode_is_float(mode) && bytes > 8)
2031 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
2032 const void *self, const ir_node *irn)
2034 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
2035 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
2036 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
2039 static const be_execution_unit_t *_allowed_units_GP[] = {
2040 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
2041 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
2042 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
2043 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
2044 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
2045 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
2046 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
2049 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
2050 &be_machine_execution_units_DUMMY[0],
2053 static const be_execution_unit_t **_units_callret[] = {
2054 _allowed_units_BRANCH,
2057 static const be_execution_unit_t **_units_other[] = {
2061 static const be_execution_unit_t **_units_dummy[] = {
2062 _allowed_units_DUMMY,
2065 const be_execution_unit_t ***ret;
2068 if (is_ia32_irn(irn)) {
2069 ret = get_ia32_exec_units(irn);
2071 else if (is_be_node(irn)) {
2072 if (be_is_Call(irn) || be_is_Return(irn)) {
2073 ret = _units_callret;
2075 else if (be_is_Barrier(irn)) {
2090 * Return the abstract ia32 machine.
2092 static const be_machine_t *ia32_get_machine(const void *self) {
2093 const ia32_isa_t *isa = self;
2098 * Return irp irgs in the desired order.
2100 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2108 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2109 * @return 1 if allowed, 0 otherwise
2111 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2114 ir_node *cmp = NULL;
2116 /* we can't handle psis with 64bit compares yet */
2118 cmp = get_Proj_pred(sel);
2120 ir_node *left = get_Cmp_left(cmp);
2121 ir_mode *cmp_mode = get_irn_mode(left);
2122 if (!mode_is_float(cmp_mode) && get_mode_size_bits(cmp_mode) > 32)
2129 if (ia32_cg_config.use_cmov) {
2130 if (ia32_cg_config.use_sse2 && cmp != NULL) {
2131 pn_Cmp pn = get_Proj_proj(sel);
2132 ir_node *cl = get_Cmp_left(cmp);
2133 ir_node *cr = get_Cmp_right(cmp);
2135 /* check the Phi nodes: no 64bit and no floating point cmov */
2136 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2137 ir_mode *mode = get_irn_mode(phi);
2139 if (mode_is_float(mode)) {
2140 /* check for Min, Max */
2141 ir_node *t = get_Phi_pred(phi, i);
2142 ir_node *f = get_Phi_pred(phi, j);
2145 /* SSE2 supports Min & Max */
2146 if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2147 if (cl == t && cr == f) {
2148 /* Psi(a <=/>= b, a, b) => MIN, MAX */
2150 } else if (cl == f && cr == t) {
2151 /* Psi(a <=/>= b, b, a) => MAX, MIN */
2158 } else if (get_mode_size_bits(mode) > 32)
2162 /* check the Phi nodes: no 64bit and no floating point cmov */
2163 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2164 ir_mode *mode = get_irn_mode(phi);
2166 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2176 /* No cmov, only some special cases */
2180 /* Now some supported cases here */
2181 pn = get_Proj_proj(sel);
2182 cl = get_Cmp_left(cmp);
2183 cr = get_Cmp_right(cmp);
2185 for (phi = phi_list; phi; phi = get_Phi_next(phi)) {
2186 ir_mode *mode = get_irn_mode(phi);
2190 t = get_Phi_pred(phi, i);
2191 f = get_Phi_pred(phi, j);
2193 /* no floating point and no 64bit yet */
2194 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2197 if (is_Const(t) && is_Const(f)) {
2198 if ((is_Const_null(t) && is_Const_one(f)) || (is_Const_one(t) && is_Const_null(f))) {
2199 /* always support Psi(x, C1, C2) */
2202 } else if (pn == pn_Cmp_Lt || pn == pn_Cmp_Le || pn == pn_Cmp_Ge || pn == pn_Cmp_Gt) {
2205 } else if (cl == t && cr == f) {
2206 /* Psi(a <=/>= b, a, b) => Min, Max */
2208 } else if (cl == f && cr == t) {
2209 /* Psi(a <=/>= b, b, a) => Max, Min */
2212 } else if ((pn & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2213 is_Const(f) && is_Const_null(f) && is_Sub(t) &&
2214 get_Sub_left(t) == cl && get_Sub_right(t) == cr) {
2215 /* Psi(a >=u b, a - b, 0) unsigned Doz */
2217 } else if ((pn & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2218 is_Const(t) && is_Const_null(t) && is_Sub(f) &&
2219 get_Sub_left(f) == cl && get_Sub_right(f) == cr) {
2220 /* Psi(a <=u b, 0, a - b) unsigned Doz */
2222 } else if (is_Const(cr) && is_Const_null(cr)) {
2223 if (cl == t && is_Minus(f) && get_Minus_op(f) == cl) {
2224 /* Psi(a <=/>= 0 ? a : -a) Nabs/Abs */
2226 } else if (cl == f && is_Minus(t) && get_Minus_op(t) == cl) {
2227 /* Psi(a <=/>= 0 ? -a : a) Abs/Nabs */
2235 /* all checks passed */
2241 static asm_constraint_flags_t ia32_parse_asm_constraint(const void *self, const char **c)
2246 /* we already added all our simple flags to the flags modifier list in
2247 * init, so this flag we don't know. */
2248 return ASM_CONSTRAINT_FLAG_INVALID;
2251 static int ia32_is_valid_clobber(const void *self, const char *clobber)
2255 return ia32_get_clobber_register(clobber) != NULL;
2259 * Returns the libFirm configuration parameter for this backend.
2261 static const backend_params *ia32_get_libfirm_params(void) {
2262 static const ir_settings_if_conv_t ifconv = {
2263 4, /* maxdepth, doesn't matter for Psi-conversion */
2264 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2266 static const ir_settings_arch_dep_t ad = {
2267 1, /* also use subs */
2268 4, /* maximum shifts */
2269 31, /* maximum shift amount */
2270 ia32_evaluate_insn, /* evaluate the instruction sequence */
2272 1, /* allow Mulhs */
2273 1, /* allow Mulus */
2274 32 /* Mulh allowed up to 32 bit */
2276 static backend_params p = {
2277 1, /* need dword lowering */
2278 1, /* support inline assembly */
2279 0, /* no immediate floating point mode. */
2280 NULL, /* no additional opcodes */
2281 NULL, /* will be set later */
2282 ia32_create_intrinsic_fkt,
2283 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2284 NULL, /* will be set below */
2285 NULL /* will be set below */
2288 ia32_setup_cg_config();
2290 /* doesn't really belong here, but this is the earliest place the backend
2292 init_asm_constraints();
2295 p.if_conv_info = &ifconv;
2299 static const lc_opt_enum_int_items_t gas_items[] = {
2300 { "elf", GAS_FLAVOUR_ELF },
2301 { "mingw", GAS_FLAVOUR_MINGW },
2302 { "yasm", GAS_FLAVOUR_YASM },
2303 { "macho", GAS_FLAVOUR_MACH_O },
2307 static lc_opt_enum_int_var_t gas_var = {
2308 (int*) &be_gas_flavour, gas_items
2311 static const lc_opt_enum_int_items_t transformer_items[] = {
2312 { "default", TRANSFORMER_DEFAULT },
2313 #ifdef FIRM_GRGEN_BE
2314 { "pbqp", TRANSFORMER_PBQP },
2319 static lc_opt_enum_int_var_t transformer_var = {
2320 (int*)&be_transformer, transformer_items
2323 static const lc_opt_table_entry_t ia32_options[] = {
2324 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2325 LC_OPT_ENT_ENUM_INT("transformer", "the transformer used for code selection", &transformer_var),
2326 LC_OPT_ENT_INT("stackalign", "set power of two stack alignment for calls",
2327 &ia32_isa_template.arch_env.stack_alignment),
2331 const arch_isa_if_t ia32_isa_if = {
2334 ia32_get_n_reg_class,
2336 ia32_get_reg_class_for_mode,
2338 ia32_get_code_generator_if,
2339 ia32_get_list_sched_selector,
2340 ia32_get_ilp_sched_selector,
2341 ia32_get_reg_class_alignment,
2342 ia32_get_libfirm_params,
2343 ia32_get_allowed_execution_units,
2346 ia32_parse_asm_constraint,
2347 ia32_is_valid_clobber
2350 void ia32_init_emitter(void);
2351 void ia32_init_finish(void);
2352 void ia32_init_optimize(void);
2353 void ia32_init_transform(void);
2354 void ia32_init_x87(void);
2356 void be_init_arch_ia32(void)
2358 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2359 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2361 lc_opt_add_table(ia32_grp, ia32_options);
2362 be_register_isa_if("ia32", &ia32_isa_if);
2364 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2366 ia32_init_emitter();
2368 ia32_init_optimize();
2369 ia32_init_transform();
2371 ia32_init_architecture();
2374 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);