5 #include "pseudo_irg.h"
14 #include "../bearch.h" /* the general register allocator interface */
15 #include "../benode_t.h"
16 #include "bearch_ia32_t.h"
18 #include "ia32_new_nodes.h" /* ia32 nodes interface */
19 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
20 #include "ia32_gen_decls.h" /* interface declaration emitter */
21 #include "ia32_transform.h"
22 #include "ia32_emitter.h"
23 #include "ia32_map_regs.h"
25 #define DEBUG_MODULE "ir.be.isa.ia32"
28 static set *cur_reg_set = NULL;
31 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
33 /**************************************************
36 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
37 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
38 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
39 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
42 **************************************************/
44 static ir_node *my_skip_proj(const ir_node *n) {
50 static int is_Call_Proj(const ir_node *n) {
52 is_Proj(get_Proj_pred(n)) &&
53 get_irn_mode(get_Proj_pred(n)) == mode_T &&
54 is_ia32_Call(get_Proj_pred(get_Proj_pred(n))))
62 static int is_Start_Proj(const ir_node *n) {
64 is_Proj(get_Proj_pred(n)) &&
65 get_irn_mode(get_Proj_pred(n)) == mode_T &&
66 is_Start(get_Proj_pred(get_Proj_pred(n))))
74 static int is_P_frame_base_Proj(const ir_node *n) {
77 get_Proj_proj(n) == pn_Start_P_frame_base)
85 static int is_used_by_Keep(const ir_node *n) {
86 return be_is_Keep(get_edge_src_irn(get_irn_out_edge_first(n)));
90 * Return register requirements for an ia32 node.
91 * If the node returns a tuple (mode_T) then the proj's
92 * will be asked for this information.
94 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
95 const ia32_register_req_t *irn_req;
96 long node_pos = pos == -1 ? 0 : pos;
97 ir_mode *mode = get_irn_mode(irn);
98 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
99 const ia32_irn_ops_t *ops = self;
101 if (mode == mode_T || mode == mode_M) {
102 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
106 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
109 if (is_Call_Proj(irn) && is_used_by_Keep(irn)) {
110 irn_req = ia32_projnum_reg_req_map[get_Proj_proj(irn)];
111 memcpy(req, &(irn_req->req), sizeof(*req));
114 else if (is_Start_Proj(irn)) {
115 irn_req = ops->cg->reg_param_req[get_Proj_proj(irn)];
116 assert(irn_req && "missing requirement for regparam");
117 memcpy(req, &(irn_req->req), sizeof(*req));
120 else if (is_Proj(irn)) {
122 node_pos = ia32_translate_proj_pos(irn);
128 irn = my_skip_proj(irn);
130 DBG((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
133 if (is_ia32_irn(irn)) {
135 irn_req = get_ia32_in_req(irn, pos);
138 irn_req = get_ia32_out_req(irn, node_pos);
141 DBG((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
143 memcpy(req, &(irn_req->req), sizeof(*req));
145 if (arch_register_req_is(&(irn_req->req), should_be_same) ||
146 arch_register_req_is(&(irn_req->req), should_be_different)) {
147 assert(irn_req->pos >= 0 && "should be same/different constraint for in -> out NYI");
148 req->other = get_irn_n(irn, irn_req->pos);
152 /* treat Phi like Const with default requirements */
154 DBG((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
155 if (mode_is_float(mode))
156 memcpy(req, &(ia32_default_req_ia32_floating_point.req), sizeof(*req));
157 else if (mode_is_int(mode) || mode_is_reference(mode))
158 memcpy(req, &(ia32_default_req_ia32_general_purpose.req), sizeof(*req));
159 else if (mode == mode_T || mode == mode_M) {
160 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
164 assert(0 && "unsupported Phi-Mode");
166 else if (is_Start(irn)) {
167 DBG((mod, LEVEL_1, "returning reqs none for ProjX -> Start (%+F )\n", irn));
169 case pn_Start_X_initial_exec:
170 case pn_Start_P_value_arg_base:
171 case pn_Start_P_globals:
172 case pn_Start_P_frame_base:
173 memcpy(req, &(ia32_default_req_none.req), sizeof(*req));
175 case pn_Start_T_args:
176 assert(0 && "ProjT(pn_Start_T_args) should not be asked");
179 else if (get_irn_op(irn) == op_Return && pos > 0) {
180 DBG((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
181 memcpy(req, &(ia32_default_req_ia32_general_purpose_eax.req), sizeof(*req));
184 DBG((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
192 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
195 if ((is_Call_Proj(irn) && is_used_by_Keep(irn)) ||
196 is_P_frame_base_Proj(irn) ||
199 /* don't skip the proj, we want to take the else below */
201 else if (is_Proj(irn)) {
202 pos = ia32_translate_proj_pos(irn);
203 irn = my_skip_proj(irn);
206 if (is_ia32_irn(irn)) {
207 const arch_register_t **slots;
209 slots = get_ia32_slots(irn);
213 ia32_set_firm_reg(irn, reg, cur_reg_set);
217 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
219 const arch_register_t *reg = NULL;
221 if ((is_Call_Proj(irn) && is_used_by_Keep(irn)) ||
222 is_P_frame_base_Proj(irn) ||
225 /* don't skip the proj, we want to take the else below */
227 else if (is_Proj(irn)) {
228 pos = ia32_translate_proj_pos(irn);
229 irn = my_skip_proj(irn);
232 if (is_ia32_irn(irn)) {
233 const arch_register_t **slots;
234 slots = get_ia32_slots(irn);
238 reg = ia32_get_firm_reg(irn, cur_reg_set);
244 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
245 irn = my_skip_proj(irn);
247 return arch_irn_class_branch;
248 else if (is_ia32_Call(irn))
249 return arch_irn_class_call;
250 else if (is_ia32_irn(irn))
251 return arch_irn_class_normal;
256 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
257 irn = my_skip_proj(irn);
258 if (is_ia32_irn(irn))
259 return get_ia32_flags(irn);
261 ir_printf("don't know flags of %+F\n", irn);
266 /* fill register allocator interface */
268 static const arch_irn_ops_if_t ia32_irn_ops_if = {
269 ia32_get_irn_reg_req,
276 ia32_irn_ops_t ia32_irn_ops = {
283 /**************************************************
286 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
287 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
288 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
289 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
292 **************************************************/
294 static void check_for_alloca(ir_node *irn, void *env) {
295 int *has_alloca = env;
297 if (get_irn_opcode(irn) == iro_Alloc) {
298 if (get_Alloc_where(irn) == stack_alloc) {
305 * Transforms the standard firm graph into
308 static void ia32_prepare_graph(void *self) {
309 ia32_code_gen_t *cg = self;
311 if (! is_pseudo_ir_graph(cg->irg)) {
312 /* If there is a alloca in the irg, we use %ebp for stack addressing */
313 /* instead of %esp, as alloca destroys %esp. */
317 /* check for alloca node */
318 irg_walk_blkwise_graph(cg->irg, check_for_alloca, NULL, &(cg->has_alloca));
320 if (cg->has_alloca) {
321 ia32_general_purpose_regs[REG_EBP].type = arch_register_type_ignore;
324 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
331 * Set the register for P_frame_base Proj to %esp.
333 static void ia32_set_P_frame_base_Proj_reg(ir_node *irn, void *env) {
334 ia32_code_gen_t *cg = env;
336 if (is_P_frame_base_Proj(irn)) {
337 arch_set_irn_register(cg->arch_env, irn, &ia32_general_purpose_regs[REG_ESP]);
342 * This function is the hook before_sched but more important: it is
343 * called after the dead node elimination. The dead node elimination changes
344 * the memory location of the nodes, which will change the hash key of
345 * the Proj_P_frame_base(Start) and this will fuck up the firm_node -> register
346 * hash map. So we need to insert the register for this node after the dead node
349 static void ia32_some_stuff_need_to_be_done_after_deadnode_elimination(void *self) {
350 ia32_code_gen_t *cg = self;
352 if (! is_pseudo_ir_graph(cg->irg))
353 irg_walk_blkwise_graph(cg->irg, NULL, ia32_set_P_frame_base_Proj_reg, cg);
359 * Dummy functions for hooks we don't need but which must be filled.
361 static void ia32_before_ra(void *self) {
367 * Emits the code, closes the output file and frees
368 * the code generator interface.
370 static void ia32_codegen(void *self) {
371 ia32_code_gen_t *cg = self;
372 ir_graph *irg = cg->irg;
375 if (cg->emit_decls) {
376 ia32_gen_decls(cg->out);
380 // ia32_finish_irg(irg);
381 ia32_gen_routine(out, irg, cg->arch_env);
385 /* de-allocate code generator */
386 del_set(cg->reg_set);
390 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env);
392 static const arch_code_generator_if_t ia32_code_gen_if = {
395 ia32_some_stuff_need_to_be_done_after_deadnode_elimination, /* before scheduling hook */
396 ia32_before_ra, /* before register allocation hook */
397 ia32_codegen /* emit && done */
401 * Initializes the code generator.
403 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env) {
404 ia32_isa_t *isa = (ia32_isa_t *)arch_env->isa;
405 ia32_code_gen_t *cg = malloc(sizeof(*cg));
407 cg->impl = &ia32_code_gen_if;
409 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
410 cg->mod = firm_dbg_register("be.transform.ia32");
412 cg->arch_env = arch_env;
416 if (isa->num_codegens > 1)
421 cur_reg_set = cg->reg_set;
423 ia32_irn_ops.cg = cg;
425 return (arch_code_generator_t *)cg;
430 /*****************************************************************
431 * ____ _ _ _____ _____
432 * | _ \ | | | | |_ _|/ ____| /\
433 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
434 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
435 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
436 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
438 *****************************************************************/
441 * Initializes the backend ISA and opens the output file.
443 static void *ia32_init(void) {
444 static int inited = 0;
445 ia32_isa_t *isa = malloc(sizeof(*isa));
447 isa->impl = &ia32_isa_if;
454 isa->num_codegens = 0;
455 isa->reg_projnum_map = new_set(ia32_cmp_reg_projnum_assoc, 1024);
457 ia32_register_init(isa);
458 ia32_create_opcodes();
466 * Closes the output file and frees the ISA structure.
468 static void ia32_done(void *self) {
474 static int ia32_get_n_reg_class(const void *self) {
478 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
479 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
480 return &ia32_reg_classes[i];
483 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
484 return &ia32_irn_ops;
487 const arch_irn_handler_t ia32_irn_handler = {
491 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
492 return &ia32_irn_handler;
495 long ia32_get_call_projnum_for_reg(const void *self, const arch_register_t *reg) {
496 ia32_isa_t *isa = (ia32_isa_t *)self;
497 return ia32_get_reg_projnum(reg, isa->reg_projnum_map);
500 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
501 return is_ia32_irn(irn);
505 * Initializes the code generator interface.
507 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
508 return &ia32_code_gen_if;
511 list_sched_selector_t ia32_sched_selector;
514 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
516 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
517 memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
518 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
519 return &ia32_sched_selector;
523 static void ia32_register_options(lc_opt_entry_t *ent)
526 #endif /* WITH_LIBCORE */
528 const arch_isa_if_t ia32_isa_if = {
530 ia32_register_options,
534 ia32_get_n_reg_class,
536 ia32_get_irn_handler,
537 ia32_get_code_generator_if,
538 ia32_get_list_sched_selector,
539 ia32_get_call_projnum_for_reg