2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
41 #include "bearch_ia32_t.h"
43 #include "ia32_new_nodes.h" /* ia32 nodes interface */
44 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
45 #include "ia32_gen_decls.h" /* interface declaration emitter */
46 #include "ia32_transform.h"
47 #include "ia32_emitter.h"
48 #include "ia32_map_regs.h"
49 #include "ia32_optimize.h"
51 #include "ia32_dbg_stat.h"
52 #include "ia32_finish.h"
53 #include "ia32_util.h"
55 #define DEBUG_MODULE "firm.be.ia32.isa"
58 static set *cur_reg_set = NULL;
61 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
63 /* Creates the unique per irg GP NoReg node. */
64 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
65 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
68 /* Creates the unique per irg FP NoReg node. */
69 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
70 return be_abi_get_callee_save_irn(cg->birg->abi,
71 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
74 /**************************************************
77 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
78 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
79 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
80 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
83 **************************************************/
85 static ir_node *my_skip_proj(const ir_node *n) {
93 * Return register requirements for an ia32 node.
94 * If the node returns a tuple (mode_T) then the proj's
95 * will be asked for this information.
97 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
98 const ia32_irn_ops_t *ops = self;
99 const ia32_register_req_t *irn_req;
100 long node_pos = pos == -1 ? 0 : pos;
101 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
102 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
104 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
105 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
109 if (mode == mode_T && pos < 0) {
110 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
114 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
118 node_pos = ia32_translate_proj_pos(irn);
124 irn = my_skip_proj(irn);
126 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
129 if (is_ia32_irn(irn)) {
131 irn_req = get_ia32_in_req(irn, pos);
134 irn_req = get_ia32_out_req(irn, node_pos);
137 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
139 memcpy(req, &(irn_req->req), sizeof(*req));
141 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
142 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
143 req->other_same = get_irn_n(irn, irn_req->same_pos);
146 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
147 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
148 req->other_different = get_irn_n(irn, irn_req->different_pos);
152 /* treat Unknowns like Const with default requirements */
153 if (is_Unknown(irn)) {
154 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
155 if (mode_is_float(mode)) {
156 if (USE_SSE2(ops->cg))
157 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
159 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
161 else if (mode_is_int(mode) || mode_is_reference(mode))
162 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
163 else if (mode == mode_T || mode == mode_M) {
164 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
168 assert(0 && "unsupported Unknown-Mode");
171 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
179 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
181 const ia32_irn_ops_t *ops = self;
183 if (get_irn_mode(irn) == mode_X) {
187 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
190 pos = ia32_translate_proj_pos(irn);
191 irn = my_skip_proj(irn);
194 if (is_ia32_irn(irn)) {
195 const arch_register_t **slots;
197 slots = get_ia32_slots(irn);
201 ia32_set_firm_reg(irn, reg, cur_reg_set);
205 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
207 const arch_register_t *reg = NULL;
211 if (get_irn_mode(irn) == mode_X) {
215 pos = ia32_translate_proj_pos(irn);
216 irn = my_skip_proj(irn);
219 if (is_ia32_irn(irn)) {
220 const arch_register_t **slots;
221 slots = get_ia32_slots(irn);
225 reg = ia32_get_firm_reg(irn, cur_reg_set);
231 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
232 irn = my_skip_proj(irn);
234 return arch_irn_class_branch;
235 else if (is_ia32_Cnst(irn))
236 return arch_irn_class_const;
237 else if (is_ia32_Ld(irn))
238 return arch_irn_class_load;
239 else if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
240 return arch_irn_class_store;
241 else if (is_ia32_irn(irn))
242 return arch_irn_class_normal;
247 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
248 irn = my_skip_proj(irn);
249 if (is_ia32_irn(irn))
250 return get_ia32_flags(irn);
253 return arch_irn_flags_ignore;
258 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
259 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
262 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
264 const ia32_irn_ops_t *ops = self;
266 if (get_ia32_frame_ent(irn)) {
267 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
269 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
270 snprintf(buf, sizeof(buf), "%d", bias);
272 if (get_ia32_op_type(irn) == ia32_Normal) {
273 set_ia32_cnst(irn, buf);
276 add_ia32_am_offs(irn, buf);
278 set_ia32_am_flavour(irn, am_flav);
284 be_abi_call_flags_bits_t flags;
285 const arch_isa_t *isa;
286 const arch_env_t *aenv;
290 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
292 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
293 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
294 env->flags = fl.bits;
297 env->isa = aenv->isa;
302 * Put all registers which are saved by the prologue/epilogue in a set.
304 * @param self The callback object.
305 * @param s The result set.
307 static void ia32_abi_dont_save_regs(void *self, pset *s)
309 ia32_abi_env_t *env = self;
310 if(env->flags.try_omit_fp)
311 pset_insert_ptr(s, env->isa->bp);
315 * Generate the routine prologue.
317 * @param self The callback object.
318 * @param mem A pointer to the mem node. Update this if you define new memory.
319 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
321 * @return The register which shall be used as a stack frame base.
323 * All nodes which define registers in @p reg_map must keep @p reg_map current.
325 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
327 ia32_abi_env_t *env = self;
329 if (!env->flags.try_omit_fp) {
330 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
331 ir_node *bl = get_irg_start_block(env->irg);
332 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
333 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
337 push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
338 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
339 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
341 /* the push must have SP out register */
342 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
343 set_ia32_flags(push, arch_irn_flags_ignore);
345 /* move esp to ebp */
346 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
347 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
348 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
349 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
351 /* beware: the copy must be done before any other sp use */
352 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
353 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
354 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
355 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
357 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
358 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
367 * Generate the routine epilogue.
368 * @param self The callback object.
369 * @param bl The block for the epilog
370 * @param mem A pointer to the mem node. Update this if you define new memory.
371 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
372 * @return The register which shall be used as a stack frame base.
374 * All nodes which define registers in @p reg_map must keep @p reg_map current.
376 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
378 ia32_abi_env_t *env = self;
379 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
380 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
382 if (env->flags.try_omit_fp) {
383 /* simply remove the stack frame here */
384 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
387 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
388 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
389 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
391 /* gcc always emits a leave at the end of a routine */
392 if (1 || ARCH_AMD(isa->opt_arch)) {
396 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
397 set_ia32_flags(leave, arch_irn_flags_ignore);
398 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
399 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
400 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
405 /* copy ebp to esp */
406 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
409 pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
410 set_ia32_flags(pop, arch_irn_flags_ignore);
411 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
412 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
413 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
415 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
416 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
419 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
420 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
424 * Produces the type which sits between the stack args and the locals on the stack.
425 * it will contain the return address and space to store the old base pointer.
426 * @return The Firm type modeling the ABI between type.
428 static ir_type *ia32_abi_get_between_type(void *self)
430 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
431 static ir_type *omit_fp_between_type = NULL;
432 static ir_type *between_type = NULL;
434 ia32_abi_env_t *env = self;
436 if ( !between_type) {
438 entity *ret_addr_ent;
439 entity *omit_fp_ret_addr_ent;
441 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_P);
442 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_P);
444 between_type = new_type_struct(IDENT("ia32_between_type"));
445 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
446 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
448 set_entity_offset_bytes(old_bp_ent, 0);
449 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
450 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
451 set_type_state(between_type, layout_fixed);
453 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
454 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
456 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
457 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
458 set_type_state(omit_fp_between_type, layout_fixed);
461 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
466 * Get the estimated cycle count for @p irn.
468 * @param self The this pointer.
469 * @param irn The node.
471 * @return The estimated cycle count for this operation
473 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
476 switch (get_ia32_irn_opcode(irn)) {
478 case iro_ia32_DivMod:
483 case iro_ia32_l_Load:
493 case iro_ia32_xStore:
494 case iro_ia32_l_Store:
496 case iro_ia32_Store8Bit:
504 case iro_ia32_l_MulS:
517 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
519 * @param irn The original operation
520 * @param i Index of the argument we want the inverse operation to yield
521 * @param inverse struct to be filled with the resulting inverse op
522 * @param obstack The obstack to use for allocation of the returned nodes array
523 * @return The inverse operation or NULL if operation invertible
525 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
528 ir_node *block, *noreg, *nomem;
531 /* we cannot invert non-ia32 irns */
532 if (! is_ia32_irn(irn))
535 /* operand must always be a real operand (not base, index or mem) */
536 if (i != 2 && i != 3)
539 /* we don't invert address mode operations */
540 if (get_ia32_op_type(irn) != ia32_Normal)
543 irg = get_irn_irg(irn);
544 block = get_nodes_block(irn);
545 mode = get_ia32_res_mode(irn);
546 noreg = get_irn_n(irn, 0);
547 nomem = new_r_NoMem(irg);
549 /* initialize structure */
550 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
554 switch (get_ia32_irn_opcode(irn)) {
556 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
557 /* we have an add with a const here */
558 /* invers == add with negated const */
559 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
560 pnc = pn_ia32_Add_res;
562 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
563 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
564 set_ia32_commutative(inverse->nodes[0]);
566 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
567 /* we have an add with a symconst here */
568 /* invers == sub with const */
569 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
570 pnc = pn_ia32_Sub_res;
572 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
575 /* normal add: inverse == sub */
576 ir_node *proj = ia32_get_res_proj(irn);
579 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
580 pnc = pn_ia32_Sub_res;
585 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
586 /* we have a sub with a const/symconst here */
587 /* invers == add with this const */
588 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
589 pnc = pn_ia32_Add_res;
590 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
591 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
595 ir_node *proj = ia32_get_res_proj(irn);
599 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
602 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
604 pnc = pn_ia32_Sub_res;
609 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
610 /* xor with const: inverse = xor */
611 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
612 pnc = pn_ia32_Eor_res;
613 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
614 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
618 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
619 pnc = pn_ia32_Eor_res;
624 ir_node *proj = ia32_get_res_proj(irn);
627 inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, proj, nomem);
628 pnc = pn_ia32_Not_res;
632 case iro_ia32_Minus: {
633 ir_node *proj = ia32_get_res_proj(irn);
636 inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, proj, nomem);
637 pnc = pn_ia32_Minus_res;
642 /* inverse operation not supported */
646 set_ia32_res_mode(inverse->nodes[0], mode);
647 inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
653 * Check if irn can load it's operand at position i from memory (source addressmode).
654 * @param self Pointer to irn ops itself
655 * @param irn The irn to be checked
656 * @param i The operands position
657 * @return Non-Zero if operand can be loaded
659 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
660 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
661 get_irn_arity(irn) != 5 || /* must be a binary operation */
662 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
663 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
664 (i != 2 && i != 3) || /* a "real" operand position must be requested */
665 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
666 is_ia32_use_frame(irn)) /* must not already use frame */
672 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *reload, unsigned int i) {
673 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
674 assert(get_nodes_block(reload) == get_nodes_block(irn) && "Reload must be in same block as irn.");
676 if (get_irn_n_edges(reload) > 1)
680 ir_node *tmp = get_irn_n(irn, 3);
681 set_irn_n(irn, 3, get_irn_n(irn, 2));
682 set_irn_n(irn, 2, tmp);
685 set_ia32_am_support(irn, ia32_am_Source);
686 set_ia32_op_type(irn, ia32_AddrModeS);
687 set_ia32_am_flavour(irn, ia32_B);
688 set_ia32_ls_mode(irn, get_irn_mode(reload));
689 set_ia32_frame_ent(irn, be_get_frame_entity(reload));
690 set_ia32_use_frame(irn);
692 set_irn_n(irn, 0, be_get_Reload_frame(reload));
693 set_irn_n(irn, 4, be_get_Reload_mem(reload));
696 Input at position one is index register, which is NoReg.
697 We would need cg object to get a real noreg, but we cannot
700 set_irn_n(irn, 3, get_irn_n(irn, 1));
703 static const be_abi_callbacks_t ia32_abi_callbacks = {
706 ia32_abi_get_between_type,
707 ia32_abi_dont_save_regs,
712 /* fill register allocator interface */
714 static const arch_irn_ops_if_t ia32_irn_ops_if = {
715 ia32_get_irn_reg_req,
720 ia32_get_frame_entity,
723 ia32_get_op_estimated_cost,
724 ia32_possible_memory_operand,
725 ia32_perform_memory_operand,
728 ia32_irn_ops_t ia32_irn_ops = {
735 /**************************************************
738 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
739 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
740 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
741 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
744 **************************************************/
747 * Transforms the standard firm graph into
750 static void ia32_prepare_graph(void *self) {
751 ia32_code_gen_t *cg = self;
752 dom_front_info_t *dom;
753 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
755 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
757 /* 1st: transform constants and psi condition trees */
758 ia32_pre_transform_phase(cg);
760 /* 2nd: transform all remaining nodes */
761 ia32_register_transformers();
762 dom = be_compute_dominance_frontiers(cg->irg);
763 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
764 be_free_dominance_frontiers(dom);
767 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
769 /* 3rd: optimize address mode */
770 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
771 ia32_optimize_addressmode(cg);
774 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
776 DEBUG_ONLY(cg->mod = old_mod;)
780 * Dummy functions for hooks we don't need but which must be filled.
782 static void ia32_before_sched(void *self) {
785 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
793 mode = get_irn_mode(irn);
795 /* check if we already saw this node or the node has more than one user */
796 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1)
799 /* mark irn visited */
800 bitset_add_irn(already_visited, irn);
802 /* non-Tuple nodes with one user: ok, return */
803 if (get_irn_n_edges(irn) >= 1 && mode != mode_T)
806 /* tuple node has one user which is not the mem proj-> ok */
807 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
808 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
813 for (i = get_irn_arity(irn) - 1; i >= 0; i--) {
814 ir_node *pred = get_irn_n(irn, i);
816 /* do not follow memory edges or we will accidentally remove stores */
817 if (is_Proj(pred) && get_irn_mode(pred) == mode_M)
820 set_irn_n(irn, i, new_Bad());
823 The current node is about to be removed: if the predecessor
824 has only this node as user, it need to be removed as well.
826 if (get_irn_n_edges(pred) <= 1)
827 remove_unused_nodes(pred, already_visited);
830 if (sched_is_scheduled(irn))
834 static void remove_unused_loads_walker(ir_node *irn, void *env) {
835 bitset_t *already_visited = env;
836 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
837 remove_unused_nodes(irn, env);
841 * Called before the register allocator.
842 * Calculate a block schedule here. We need it for the x87
843 * simulator and the emitter.
845 static void ia32_before_ra(void *self) {
846 ia32_code_gen_t *cg = self;
847 bitset_t *already_visited = bitset_irg_malloc(cg->irg);
849 cg->blk_sched = sched_create_block_schedule(cg->irg);
853 There are sometimes unused loads, only pinned by memory.
854 We need to remove those Loads and all other nodes which won't be used
855 after removing the Load from schedule.
857 irg_walk_graph(cg->irg, remove_unused_loads_walker, NULL, already_visited);
858 bitset_free(already_visited);
863 * Transforms a be node into a Load.
865 static void transform_to_Load(ia32_transform_env_t *env) {
866 ir_node *irn = env->irn;
867 entity *ent = be_get_frame_entity(irn);
868 ir_mode *mode = env->mode;
869 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
870 ir_node *nomem = new_rd_NoMem(env->irg);
871 ir_node *sched_point = NULL;
872 ir_node *ptr = get_irn_n(irn, 0);
873 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
874 ir_node *new_op, *proj;
875 const arch_register_t *reg;
877 if (sched_is_scheduled(irn)) {
878 sched_point = sched_prev(irn);
881 if (mode_is_float(mode)) {
882 if (USE_SSE2(env->cg))
883 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
885 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
888 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
891 set_ia32_am_support(new_op, ia32_am_Source);
892 set_ia32_op_type(new_op, ia32_AddrModeS);
893 set_ia32_am_flavour(new_op, ia32_B);
894 set_ia32_ls_mode(new_op, mode);
895 set_ia32_frame_ent(new_op, ent);
896 set_ia32_use_frame(new_op);
898 DBG_OPT_RELOAD2LD(irn, new_op);
900 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
903 sched_add_after(sched_point, new_op);
904 sched_add_after(new_op, proj);
909 /* copy the register from the old node to the new Load */
910 reg = arch_get_irn_register(env->cg->arch_env, irn);
911 arch_set_irn_register(env->cg->arch_env, new_op, reg);
913 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
919 * Transforms a be node into a Store.
921 static void transform_to_Store(ia32_transform_env_t *env) {
922 ir_node *irn = env->irn;
923 entity *ent = be_get_frame_entity(irn);
924 ir_mode *mode = env->mode;
925 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
926 ir_node *nomem = new_rd_NoMem(env->irg);
927 ir_node *ptr = get_irn_n(irn, 0);
928 ir_node *val = get_irn_n(irn, 1);
929 ir_node *new_op, *proj;
930 ir_node *sched_point = NULL;
932 if (sched_is_scheduled(irn)) {
933 sched_point = sched_prev(irn);
936 if (mode_is_float(mode)) {
937 if (USE_SSE2(env->cg))
938 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
940 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
942 else if (get_mode_size_bits(mode) == 8) {
943 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
946 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
949 set_ia32_am_support(new_op, ia32_am_Dest);
950 set_ia32_op_type(new_op, ia32_AddrModeD);
951 set_ia32_am_flavour(new_op, ia32_B);
952 set_ia32_ls_mode(new_op, mode);
953 set_ia32_frame_ent(new_op, ent);
954 set_ia32_use_frame(new_op);
956 DBG_OPT_SPILL2ST(irn, new_op);
958 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
961 sched_add_after(sched_point, new_op);
965 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
971 * Fix the mode of Spill/Reload
973 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
975 if (mode_is_float(mode)) {
987 * Block-Walker: Calls the transform functions Spill and Reload.
989 static void ia32_after_ra_walker(ir_node *block, void *env) {
990 ir_node *node, *prev;
991 ia32_code_gen_t *cg = env;
992 ia32_transform_env_t tenv;
995 tenv.irg = current_ir_graph;
997 DEBUG_ONLY(tenv.mod = cg->mod;)
999 /* beware: the schedule is changed here */
1000 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1001 prev = sched_prev(node);
1002 if (be_is_Reload(node)) {
1003 /* we always reload the whole register */
1004 tenv.dbg = get_irn_dbg_info(node);
1006 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
1007 transform_to_Load(&tenv);
1009 else if (be_is_Spill(node)) {
1010 /* we always spill the whole register */
1011 tenv.dbg = get_irn_dbg_info(node);
1013 tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
1014 transform_to_Store(&tenv);
1020 * We transform Spill and Reload here. This needs to be done before
1021 * stack biasing otherwise we would miss the corrected offset for these nodes.
1023 * If x87 instruction should be emitted, run the x87 simulator and patch
1024 * the virtual instructions. This must obviously be done after register allocation.
1026 static void ia32_after_ra(void *self) {
1027 ia32_code_gen_t *cg = self;
1029 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
1031 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1032 if (cg->used_fp == fp_x87 || cg->force_sim) {
1033 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
1039 * Emits the code, closes the output file and frees
1040 * the code generator interface.
1042 static void ia32_codegen(void *self) {
1043 ia32_code_gen_t *cg = self;
1044 ir_graph *irg = cg->irg;
1046 ia32_finish_irg(irg, cg);
1048 be_dump(irg, "-finished", dump_ir_block_graph_sched);
1049 ia32_gen_routine(cg->isa->out, irg, cg);
1053 /* remove it from the isa */
1056 /* de-allocate code generator */
1057 del_set(cg->reg_set);
1062 static void *ia32_cg_init(const be_irg_t *birg);
1064 static const arch_code_generator_if_t ia32_code_gen_if = {
1066 NULL, /* before abi introduce hook */
1068 ia32_before_sched, /* before scheduling hook */
1069 ia32_before_ra, /* before register allocation hook */
1070 ia32_after_ra, /* after register allocation hook */
1071 ia32_codegen /* emit && done */
1075 * Initializes a IA32 code generator.
1077 static void *ia32_cg_init(const be_irg_t *birg) {
1078 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1079 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1081 cg->impl = &ia32_code_gen_if;
1082 cg->irg = birg->irg;
1083 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1084 cg->arch_env = birg->main_env->arch_env;
1087 cg->blk_sched = NULL;
1088 cg->fp_to_gp = NULL;
1089 cg->gp_to_fp = NULL;
1090 cg->fp_kind = isa->fp_kind;
1091 cg->used_fp = fp_none;
1092 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1094 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1096 /* copy optimizations from isa for easier access */
1098 cg->arch = isa->arch;
1099 cg->opt_arch = isa->opt_arch;
1105 if (isa->name_obst_size) {
1106 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
1107 isa->name_obst_size = 0;
1108 obstack_free(isa->name_obst, NULL);
1109 obstack_init(isa->name_obst);
1113 cur_reg_set = cg->reg_set;
1115 ia32_irn_ops.cg = cg;
1117 return (arch_code_generator_t *)cg;
1122 /*****************************************************************
1123 * ____ _ _ _____ _____
1124 * | _ \ | | | | |_ _|/ ____| /\
1125 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1126 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1127 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1128 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1130 *****************************************************************/
1133 * Set output modes for GCC
1135 static const tarval_mode_info mo_integer = {
1142 * set the tarval output mode to C-semantics
1144 static void set_tarval_output_modes(void)
1146 set_tarval_mode_output_option(get_modeLs(), &mo_integer);
1147 set_tarval_mode_output_option(get_modeLu(), &mo_integer);
1148 set_tarval_mode_output_option(get_modeIs(), &mo_integer);
1149 set_tarval_mode_output_option(get_modeIu(), &mo_integer);
1150 set_tarval_mode_output_option(get_modeHs(), &mo_integer);
1151 set_tarval_mode_output_option(get_modeHu(), &mo_integer);
1152 set_tarval_mode_output_option(get_modeBs(), &mo_integer);
1153 set_tarval_mode_output_option(get_modeBu(), &mo_integer);
1154 set_tarval_mode_output_option(get_modeC(), &mo_integer);
1155 set_tarval_mode_output_option(get_modeU(), &mo_integer);
1156 set_tarval_mode_output_option(get_modeIu(), &mo_integer);
1161 * The template that generates a new ISA object.
1162 * Note that this template can be changed by command line
1165 static ia32_isa_t ia32_isa_template = {
1167 &ia32_isa_if, /* isa interface implementation */
1168 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1169 &ia32_gp_regs[REG_EBP], /* base pointer register */
1170 -1, /* stack direction */
1172 NULL, /* 16bit register names */
1173 NULL, /* 8bit register names */
1177 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1178 IA32_OPT_DOAM | /* optimize address mode default: on */
1179 IA32_OPT_LEA | /* optimize for LEAs default: on */
1180 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1181 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1182 IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
1183 arch_pentium_4, /* instruction architecture */
1184 arch_pentium_4, /* optimize for architecture */
1185 fp_sse2, /* use sse2 unit */
1186 NULL, /* current code generator */
1188 NULL, /* name obstack */
1189 0 /* name obst size */
1194 * Initializes the backend ISA.
1196 static void *ia32_init(FILE *file_handle) {
1197 static int inited = 0;
1203 set_tarval_output_modes();
1205 isa = xmalloc(sizeof(*isa));
1206 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1208 ia32_register_init(isa);
1209 ia32_create_opcodes();
1211 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1212 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1213 /* no SSE2 for these cpu's */
1214 isa->fp_kind = fp_x87;
1216 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1217 /* Pentium 4 don't like inc and dec instructions */
1218 isa->opt &= ~IA32_OPT_INCDEC;
1221 isa->regs_16bit = pmap_create();
1222 isa->regs_8bit = pmap_create();
1223 isa->types = pmap_create();
1224 isa->tv_ent = pmap_create();
1225 isa->out = file_handle;
1227 ia32_build_16bit_reg_map(isa->regs_16bit);
1228 ia32_build_8bit_reg_map(isa->regs_8bit);
1230 /* patch register names of x87 registers */
1232 ia32_st_regs[0].name = "st";
1233 ia32_st_regs[1].name = "st(1)";
1234 ia32_st_regs[2].name = "st(2)";
1235 ia32_st_regs[3].name = "st(3)";
1236 ia32_st_regs[4].name = "st(4)";
1237 ia32_st_regs[5].name = "st(5)";
1238 ia32_st_regs[6].name = "st(6)";
1239 ia32_st_regs[7].name = "st(7)";
1243 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1244 obstack_init(isa->name_obst);
1245 isa->name_obst_size = 0;
1248 ia32_handle_intrinsics();
1249 ia32_switch_section(NULL, NO_SECTION);
1250 fprintf(isa->out, "\t.intel_syntax\n");
1260 * Closes the output file and frees the ISA structure.
1262 static void ia32_done(void *self) {
1263 ia32_isa_t *isa = self;
1265 /* emit now all global declarations */
1266 ia32_gen_decls(isa->out);
1268 pmap_destroy(isa->regs_16bit);
1269 pmap_destroy(isa->regs_8bit);
1270 pmap_destroy(isa->tv_ent);
1271 pmap_destroy(isa->types);
1274 //printf("name obst size = %d bytes\n", isa->name_obst_size);
1275 obstack_free(isa->name_obst, NULL);
1283 * Return the number of register classes for this architecture.
1284 * We report always these:
1285 * - the general purpose registers
1286 * - the SSE floating point register set
1287 * - the virtual floating point registers
1289 static int ia32_get_n_reg_class(const void *self) {
1294 * Return the register class for index i.
1296 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1297 const ia32_isa_t *isa = self;
1298 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1300 return &ia32_reg_classes[CLASS_ia32_gp];
1302 return &ia32_reg_classes[CLASS_ia32_xmm];
1304 return &ia32_reg_classes[CLASS_ia32_vfp];
1308 * Get the register class which shall be used to store a value of a given mode.
1309 * @param self The this pointer.
1310 * @param mode The mode in question.
1311 * @return A register class which can hold values of the given mode.
1313 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1314 const ia32_isa_t *isa = self;
1315 if (mode_is_float(mode)) {
1316 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1319 return &ia32_reg_classes[CLASS_ia32_gp];
1323 * Get the ABI restrictions for procedure calls.
1324 * @param self The this pointer.
1325 * @param method_type The type of the method (procedure) in question.
1326 * @param abi The abi object to be modified
1328 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1329 const ia32_isa_t *isa = self;
1332 unsigned cc = get_method_calling_convention(method_type);
1333 int n = get_method_n_params(method_type);
1336 int i, ignore_1, ignore_2;
1338 const arch_register_t *reg;
1339 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1341 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1343 /* set abi flags for calls */
1344 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1345 call_flags.bits.store_args_sequential = use_push;
1346 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1347 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1348 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1350 /* set stack parameter passing style */
1351 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1353 /* collect the mode for each type */
1354 modes = alloca(n * sizeof(modes[0]));
1356 for (i = 0; i < n; i++) {
1357 tp = get_method_param_type(method_type, i);
1358 modes[i] = get_type_mode(tp);
1361 /* set register parameters */
1362 if (cc & cc_reg_param) {
1363 /* determine the number of parameters passed via registers */
1364 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1366 /* loop over all parameters and set the register requirements */
1367 for (i = 0; i <= biggest_n; i++) {
1368 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1369 assert(reg && "kaputt");
1370 be_abi_call_param_reg(abi, i, reg);
1377 /* set stack parameters */
1378 for (i = stack_idx; i < n; i++) {
1379 be_abi_call_param_stack(abi, i, 1, 0, 0);
1383 /* set return registers */
1384 n = get_method_n_ress(method_type);
1386 assert(n <= 2 && "more than two results not supported");
1388 /* In case of 64bit returns, we will have two 32bit values */
1390 tp = get_method_res_type(method_type, 0);
1391 mode = get_type_mode(tp);
1393 assert(!mode_is_float(mode) && "two FP results not supported");
1395 tp = get_method_res_type(method_type, 1);
1396 mode = get_type_mode(tp);
1398 assert(!mode_is_float(mode) && "two FP results not supported");
1400 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1401 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1404 const arch_register_t *reg;
1406 tp = get_method_res_type(method_type, 0);
1407 assert(is_atomic_type(tp));
1408 mode = get_type_mode(tp);
1410 reg = mode_is_float(mode) ?
1411 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1412 &ia32_gp_regs[REG_EAX];
1414 be_abi_call_res_reg(abi, 0, reg);
1419 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1420 return &ia32_irn_ops;
1423 const arch_irn_handler_t ia32_irn_handler = {
1427 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1428 return &ia32_irn_handler;
1431 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1432 return is_ia32_irn(irn) ? 1 : -1;
1436 * Initializes the code generator interface.
1438 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1439 return &ia32_code_gen_if;
1442 list_sched_selector_t ia32_sched_selector;
1445 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1447 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1448 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1449 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1450 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1451 return &ia32_sched_selector;
1455 * Returns the necessary byte alignment for storing a register of given class.
1457 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1458 ir_mode *mode = arch_register_class_mode(cls);
1459 int bytes = get_mode_size_bytes(mode);
1461 if (mode_is_float(mode) && bytes > 8)
1466 static ia32_intrinsic_env_t intrinsic_env = { NULL, NULL };
1469 * Returns the libFirm configuration parameter for this backend.
1471 static const backend_params *ia32_get_libfirm_params(void) {
1472 static const arch_dep_params_t ad = {
1473 1, /* also use subs */
1474 4, /* maximum shifts */
1475 31, /* maximum shift amount */
1477 1, /* allow Mulhs */
1478 1, /* allow Mulus */
1479 32 /* Mulh allowed up to 32 bit */
1481 static backend_params p = {
1482 NULL, /* no additional opcodes */
1483 NULL, /* will be set later */
1484 1, /* need dword lowering */
1485 ia32_create_intrinsic_fkt,
1486 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1494 /* instruction set architectures. */
1495 static const lc_opt_enum_int_items_t arch_items[] = {
1496 { "386", arch_i386, },
1497 { "486", arch_i486, },
1498 { "pentium", arch_pentium, },
1499 { "586", arch_pentium, },
1500 { "pentiumpro", arch_pentium_pro, },
1501 { "686", arch_pentium_pro, },
1502 { "pentiummmx", arch_pentium_mmx, },
1503 { "pentium2", arch_pentium_2, },
1504 { "p2", arch_pentium_2, },
1505 { "pentium3", arch_pentium_3, },
1506 { "p3", arch_pentium_3, },
1507 { "pentium4", arch_pentium_4, },
1508 { "p4", arch_pentium_4, },
1509 { "pentiumm", arch_pentium_m, },
1510 { "pm", arch_pentium_m, },
1511 { "core", arch_core, },
1513 { "athlon", arch_athlon, },
1514 { "athlon64", arch_athlon_64, },
1515 { "opteron", arch_opteron, },
1519 static lc_opt_enum_int_var_t arch_var = {
1520 &ia32_isa_template.arch, arch_items
1523 static lc_opt_enum_int_var_t opt_arch_var = {
1524 &ia32_isa_template.opt_arch, arch_items
1527 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1529 { "sse2", fp_sse2 },
1533 static lc_opt_enum_int_var_t fp_unit_var = {
1534 &ia32_isa_template.fp_kind, fp_unit_items
1537 static const lc_opt_enum_int_items_t gas_items[] = {
1538 { "linux", ASM_LINUX_GAS },
1539 { "mingw", ASM_MINGW_GAS },
1543 static lc_opt_enum_int_var_t gas_var = {
1544 (int *)&asm_flavour, gas_items
1547 static const lc_opt_table_entry_t ia32_options[] = {
1548 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1549 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1550 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1551 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1552 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1553 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1554 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1555 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1556 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1561 * Register command line options for the ia32 backend.
1565 * ia32-arch=arch create instruction for arch
1566 * ia32-opt=arch optimize for run on arch
1567 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1568 * ia32-incdec optimize for inc/dec
1569 * ia32-noaddrmode do not use address mode
1570 * ia32-nolea do not optimize for LEAs
1571 * ia32-noplacecnst do not place constants,
1572 * ia32-noimmop no operations with immediates
1573 * ia32-noextbb do not use extended basic block scheduling
1574 * ia32-gasmode set the GAS compatibility mode
1576 static void ia32_register_options(lc_opt_entry_t *ent)
1578 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1579 lc_opt_add_table(be_grp_ia32, ia32_options);
1581 #endif /* WITH_LIBCORE */
1583 const arch_isa_if_t ia32_isa_if = {
1586 ia32_get_n_reg_class,
1588 ia32_get_reg_class_for_mode,
1590 ia32_get_irn_handler,
1591 ia32_get_code_generator_if,
1592 ia32_get_list_sched_selector,
1593 ia32_get_reg_class_alignment,
1594 ia32_get_libfirm_params,
1596 ia32_register_options