2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
30 #include <libcore/lc_opts.h>
31 #include <libcore/lc_opts_enum.h>
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
54 #include "../beirg_t.h"
55 #include "../benode_t.h"
56 #include "../belower.h"
57 #include "../besched_t.h"
60 #include "../beirgmod.h"
61 #include "../be_dbgout.h"
62 #include "../beblocksched.h"
63 #include "../bemachine.h"
64 #include "../beilpsched.h"
65 #include "../bespillslots.h"
66 #include "../bemodule.h"
67 #include "../begnuas.h"
68 #include "../bestate.h"
69 #include "../beflags.h"
71 #include "bearch_ia32_t.h"
73 #include "ia32_new_nodes.h"
74 #include "gen_ia32_regalloc_if.h"
75 #include "gen_ia32_machine.h"
76 #include "ia32_transform.h"
77 #include "ia32_emitter.h"
78 #include "ia32_map_regs.h"
79 #include "ia32_optimize.h"
81 #include "ia32_dbg_stat.h"
82 #include "ia32_finish.h"
83 #include "ia32_util.h"
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 static set *cur_reg_set = NULL;
91 ir_mode *mode_fpcw = NULL;
92 ia32_code_gen_t *ia32_current_cg = NULL;
95 * The environment for the intrinsic mapping.
97 static ia32_intrinsic_env_t intrinsic_env = {
99 NULL, /* the irg, these entities belong to */
100 NULL, /* entity for first div operand (move into FPU) */
101 NULL, /* entity for second div operand (move into FPU) */
102 NULL, /* entity for converts ll -> d */
103 NULL, /* entity for converts d -> ll */
104 NULL, /* entity for __divdi3 library call */
105 NULL, /* entity for __moddi3 library call */
106 NULL, /* entity for __udivdi3 library call */
107 NULL, /* entity for __umoddi3 library call */
108 NULL, /* bias value for conversion from float to unsigned 64 */
112 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
114 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
115 create_const_node_func func,
116 const arch_register_t* reg)
118 ir_node *block, *res;
123 block = get_irg_start_block(cg->irg);
124 res = func(NULL, cg->irg, block);
125 arch_set_irn_register(cg->arch_env, res, reg);
128 add_irn_dep(get_irg_end(cg->irg), res);
129 /* add_irn_dep(get_irg_start(cg->irg), res); */
134 /* Creates the unique per irg GP NoReg node. */
135 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
136 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
137 &ia32_gp_regs[REG_GP_NOREG]);
140 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
141 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
142 &ia32_vfp_regs[REG_VFP_NOREG]);
145 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
146 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
147 &ia32_xmm_regs[REG_XMM_NOREG]);
150 /* Creates the unique per irg FP NoReg node. */
151 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
152 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
155 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
156 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
157 &ia32_gp_regs[REG_GP_UKNWN]);
160 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
161 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
162 &ia32_vfp_regs[REG_VFP_UKNWN]);
165 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
166 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
167 &ia32_xmm_regs[REG_XMM_UKNWN]);
170 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
171 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
172 &ia32_fp_cw_regs[REG_FPCW]);
177 * Returns gp_noreg or fp_noreg, depending in input requirements.
179 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
180 const arch_register_req_t *req;
182 req = arch_get_register_req(cg->arch_env, irn, pos);
183 assert(req != NULL && "Missing register requirements");
184 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
185 return ia32_new_NoReg_gp(cg);
187 return ia32_new_NoReg_fp(cg);
190 /**************************************************
193 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
194 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
195 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
196 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
199 **************************************************/
202 * Return register requirements for an ia32 node.
203 * If the node returns a tuple (mode_T) then the proj's
204 * will be asked for this information.
206 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
210 long node_pos = pos == -1 ? 0 : pos;
211 ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
214 if (is_Block(node) || mode == mode_X) {
215 return arch_no_register_req;
218 if (mode == mode_T && pos < 0) {
219 return arch_no_register_req;
224 return arch_no_register_req;
227 return arch_no_register_req;
230 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
231 node = skip_Proj_const(node);
234 if (is_ia32_irn(node)) {
235 const arch_register_req_t *req;
237 req = get_ia32_in_req(node, pos);
239 req = get_ia32_out_req(node, node_pos);
246 /* unknowns should be transformed already */
247 assert(!is_Unknown(node));
249 return arch_no_register_req;
252 static void ia32_set_irn_reg(const void *self, ir_node *irn,
253 const arch_register_t *reg)
258 if (get_irn_mode(irn) == mode_X) {
263 pos = get_Proj_proj(irn);
264 irn = skip_Proj(irn);
267 if (is_ia32_irn(irn)) {
268 const arch_register_t **slots;
270 slots = get_ia32_slots(irn);
273 ia32_set_firm_reg(irn, reg, cur_reg_set);
277 static const arch_register_t *ia32_get_irn_reg(const void *self,
281 const arch_register_t *reg = NULL;
286 if (get_irn_mode(irn) == mode_X) {
290 pos = get_Proj_proj(irn);
291 irn = skip_Proj_const(irn);
294 if (is_ia32_irn(irn)) {
295 const arch_register_t **slots;
296 slots = get_ia32_slots(irn);
299 reg = ia32_get_firm_reg(irn, cur_reg_set);
305 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
306 arch_irn_class_t classification = arch_irn_class_normal;
309 irn = skip_Proj_const(irn);
312 classification |= arch_irn_class_branch;
314 if (! is_ia32_irn(irn))
315 return classification & ~arch_irn_class_normal;
318 classification |= arch_irn_class_load;
321 classification |= arch_irn_class_store;
323 if (is_ia32_need_stackent(irn))
324 classification |= arch_irn_class_reload;
326 return classification;
329 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
330 arch_irn_flags_t flags = arch_irn_flags_none;
334 return arch_irn_flags_ignore;
336 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
337 ir_node *pred = get_Proj_pred(irn);
339 if(is_ia32_irn(pred)) {
340 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
346 if (is_ia32_irn(irn)) {
347 flags |= get_ia32_flags(irn);
354 * The IA32 ABI callback object.
357 be_abi_call_flags_bits_t flags; /**< The call flags. */
358 const arch_isa_t *isa; /**< The ISA handle. */
359 const arch_env_t *aenv; /**< The architecture environment. */
360 ir_graph *irg; /**< The associated graph. */
363 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
365 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
368 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
370 set_ia32_frame_ent(irn, ent);
373 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
374 const ia32_irn_ops_t *ops = self;
376 if (get_ia32_frame_ent(irn)) {
377 if (is_ia32_Pop(irn)) {
378 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
380 /* Pop nodes modify the stack pointer before calculating the destination
381 * address, so fix this here
387 add_ia32_am_offs_int(irn, bias);
391 static int ia32_get_sp_bias(const void *self, const ir_node *node)
395 if (is_ia32_Push(node))
398 if (is_ia32_Pop(node))
405 * Put all registers which are saved by the prologue/epilogue in a set.
407 * @param self The callback object.
408 * @param s The result set.
410 static void ia32_abi_dont_save_regs(void *self, pset *s)
412 ia32_abi_env_t *env = self;
413 if(env->flags.try_omit_fp)
414 pset_insert_ptr(s, env->isa->bp);
418 * Generate the routine prologue.
420 * @param self The callback object.
421 * @param mem A pointer to the mem node. Update this if you define new memory.
422 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
424 * @return The register which shall be used as a stack frame base.
426 * All nodes which define registers in @p reg_map must keep @p reg_map current.
428 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
430 ia32_abi_env_t *env = self;
431 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
432 ia32_code_gen_t *cg = isa->cg;
434 if (! env->flags.try_omit_fp) {
435 ir_node *bl = get_irg_start_block(env->irg);
436 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
437 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
438 ir_node *noreg = ia32_new_NoReg_gp(cg);
441 /* ALL nodes representing bp must be set to ignore. */
442 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
445 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
446 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
447 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
449 /* the push must have SP out register */
450 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
451 set_ia32_flags(push, arch_irn_flags_ignore);
453 /* move esp to ebp */
454 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
455 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
456 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
457 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
459 /* beware: the copy must be done before any other sp use */
460 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
461 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
462 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
463 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
465 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
466 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
475 * Generate the routine epilogue.
476 * @param self The callback object.
477 * @param bl The block for the epilog
478 * @param mem A pointer to the mem node. Update this if you define new memory.
479 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
480 * @return The register which shall be used as a stack frame base.
482 * All nodes which define registers in @p reg_map must keep @p reg_map current.
484 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
486 ia32_abi_env_t *env = self;
487 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
488 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
490 if (env->flags.try_omit_fp) {
491 /* simply remove the stack frame here */
492 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
493 add_irn_dep(curr_sp, *mem);
495 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
496 ia32_code_gen_t *cg = isa->cg;
497 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
499 /* gcc always emits a leave at the end of a routine */
500 if (1 || ARCH_AMD(isa->opt_arch)) {
504 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
505 set_ia32_flags(leave, arch_irn_flags_ignore);
506 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
507 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
509 ir_node *noreg = ia32_new_NoReg_gp(cg);
512 /* copy ebp to esp */
513 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
516 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp);
517 set_ia32_flags(pop, arch_irn_flags_ignore);
518 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
519 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
521 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
523 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
524 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
527 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
528 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
532 * Initialize the callback object.
533 * @param call The call object.
534 * @param aenv The architecture environment.
535 * @param irg The graph with the method.
536 * @return Some pointer. This pointer is passed to all other callback functions as self object.
538 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
540 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
541 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
542 env->flags = fl.bits;
545 env->isa = aenv->isa;
550 * Destroy the callback object.
551 * @param self The callback object.
553 static void ia32_abi_done(void *self) {
558 * Produces the type which sits between the stack args and the locals on the stack.
559 * it will contain the return address and space to store the old base pointer.
560 * @return The Firm type modeling the ABI between type.
562 static ir_type *ia32_abi_get_between_type(void *self)
564 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
565 static ir_type *omit_fp_between_type = NULL;
566 static ir_type *between_type = NULL;
568 ia32_abi_env_t *env = self;
570 if (! between_type) {
571 ir_entity *old_bp_ent;
572 ir_entity *ret_addr_ent;
573 ir_entity *omit_fp_ret_addr_ent;
575 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
576 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
578 between_type = new_type_struct(IDENT("ia32_between_type"));
579 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
580 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
582 set_entity_offset(old_bp_ent, 0);
583 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
584 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
585 set_type_state(between_type, layout_fixed);
587 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
588 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
590 set_entity_offset(omit_fp_ret_addr_ent, 0);
591 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
592 set_type_state(omit_fp_between_type, layout_fixed);
595 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
600 * Get the estimated cycle count for @p irn.
602 * @param self The this pointer.
603 * @param irn The node.
605 * @return The estimated cycle count for this operation
607 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
610 ia32_op_type_t op_tp;
611 const ia32_irn_ops_t *ops = self;
615 if (!is_ia32_irn(irn))
618 assert(is_ia32_irn(irn));
620 cost = get_ia32_latency(irn);
621 op_tp = get_ia32_op_type(irn);
623 if (is_ia32_CopyB(irn)) {
625 if (ARCH_INTEL(ops->cg->arch))
628 else if (is_ia32_CopyB_i(irn)) {
629 int size = get_ia32_pncode(irn);
630 cost = 20 + (int)ceil((4/3) * size);
631 if (ARCH_INTEL(ops->cg->arch))
634 /* in case of address mode operations add additional cycles */
635 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
637 In case of stack access and access to fixed addresses add 5 cycles
638 (we assume they are in cache), other memory operations cost 20
641 if(is_ia32_use_frame(irn) ||
642 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
643 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
654 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
656 * @param irn The original operation
657 * @param i Index of the argument we want the inverse operation to yield
658 * @param inverse struct to be filled with the resulting inverse op
659 * @param obstack The obstack to use for allocation of the returned nodes array
660 * @return The inverse operation or NULL if operation invertible
662 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
666 ir_node *block, *noreg, *nomem;
670 /* we cannot invert non-ia32 irns */
671 if (! is_ia32_irn(irn))
674 /* operand must always be a real operand (not base, index or mem) */
675 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
678 /* we don't invert address mode operations */
679 if (get_ia32_op_type(irn) != ia32_Normal)
682 /* TODO: adjust for new immediates... */
683 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
687 irg = get_irn_irg(irn);
688 block = get_nodes_block(irn);
689 mode = get_irn_mode(irn);
690 irn_mode = get_irn_mode(irn);
691 noreg = get_irn_n(irn, 0);
692 nomem = new_r_NoMem(irg);
693 dbg = get_irn_dbg_info(irn);
695 /* initialize structure */
696 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
700 switch (get_ia32_irn_opcode(irn)) {
703 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
704 /* we have an add with a const here */
705 /* invers == add with negated const */
706 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
708 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
709 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
710 set_ia32_commutative(inverse->nodes[0]);
712 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
713 /* we have an add with a symconst here */
714 /* invers == sub with const */
715 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
717 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
720 /* normal add: inverse == sub */
721 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
728 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
729 /* we have a sub with a const/symconst here */
730 /* invers == add with this const */
731 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
732 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
733 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
737 if (i == n_ia32_binary_left) {
738 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
741 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
749 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
750 /* xor with const: inverse = xor */
751 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
752 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
753 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
757 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
763 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
768 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
773 /* inverse operation not supported */
780 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
782 if(mode_is_float(mode))
789 * Get the mode that should be used for spilling value node
791 static ir_mode *get_spill_mode(const ir_node *node)
793 ir_mode *mode = get_irn_mode(node);
794 return get_spill_mode_mode(mode);
798 * Checks whether an addressmode reload for a node with mode mode is compatible
799 * with a spillslot of mode spill_mode
801 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
803 if(mode_is_float(mode)) {
804 return mode == spillmode;
811 * Check if irn can load it's operand at position i from memory (source addressmode).
812 * @param self Pointer to irn ops itself
813 * @param irn The irn to be checked
814 * @param i The operands position
815 * @return Non-Zero if operand can be loaded
817 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
818 ir_node *op = get_irn_n(irn, i);
819 const ir_mode *mode = get_irn_mode(op);
820 const ir_mode *spillmode = get_spill_mode(op);
823 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
824 get_ia32_am_arity(irn) != 2 || /* must be a binary operation TODO is this necessary? */
825 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
826 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
827 ! ia32_is_spillmode_compatible(mode, spillmode) ||
828 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
829 is_ia32_use_frame(irn)) /* must not already use frame */
832 if (i == n_ia32_binary_left) {
833 const arch_register_req_t *req;
834 if(!is_ia32_commutative(irn))
836 /* we can't swap left/right for limited registers
837 * (As this (currently) breaks constraint handling copies)
839 req = get_ia32_in_req(irn, n_ia32_binary_left);
840 if(req->type & arch_register_req_type_limited) {
848 static void ia32_perform_memory_operand(const void *self, ir_node *irn,
849 ir_node *spill, unsigned int i)
851 const ia32_irn_ops_t *ops = self;
852 ia32_code_gen_t *cg = ops->cg;
854 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
856 if (i == n_ia32_binary_left) {
857 ia32_swap_left_right(irn);
860 set_ia32_op_type(irn, ia32_AddrModeS);
861 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
862 set_ia32_use_frame(irn);
863 set_ia32_need_stackent(irn);
865 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
866 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
867 set_irn_n(irn, n_ia32_mem, spill);
869 /* immediates are only allowed on the right side */
870 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
871 ia32_swap_left_right(irn);
875 static const be_abi_callbacks_t ia32_abi_callbacks = {
878 ia32_abi_get_between_type,
879 ia32_abi_dont_save_regs,
884 /* fill register allocator interface */
886 static const arch_irn_ops_if_t ia32_irn_ops_if = {
887 ia32_get_irn_reg_req,
892 ia32_get_frame_entity,
893 ia32_set_frame_entity,
894 ia32_set_frame_offset,
897 ia32_get_op_estimated_cost,
898 ia32_possible_memory_operand,
899 ia32_perform_memory_operand,
902 ia32_irn_ops_t ia32_irn_ops = {
909 /**************************************************
912 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
913 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
914 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
915 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
918 **************************************************/
920 static void ia32_before_abi(void *self) {
921 ia32_code_gen_t *cg = self;
923 ir_lower_mode_b(cg->irg, mode_Iu, 0);
924 /* do local optimisations */
925 optimize_graph_df(cg->irg);
927 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
931 * Transforms the standard firm graph into
934 static void ia32_prepare_graph(void *self) {
935 ia32_code_gen_t *cg = self;
937 /* TODO: we often have dead code reachable through out-edges here. So for
938 * now we rebuild edges (as we need correct user count for code selection)
941 edges_deactivate(cg->irg);
942 edges_activate(cg->irg);
945 /* transform nodes into assembler instructions */
946 ia32_transform_graph(cg);
948 /* do local optimisations (mainly CSE) */
949 optimize_graph_df(cg->irg);
952 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
954 /* optimize address mode */
955 ia32_optimize_graph(cg);
958 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
960 /* do code placement, (optimize position of constants and argument loads) */
964 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
968 * Dummy functions for hooks we don't need but which must be filled.
970 static void ia32_before_sched(void *self) {
974 static void turn_back_am(ir_node *node)
976 ir_graph *irg = current_ir_graph;
977 dbg_info *dbgi = get_irn_dbg_info(node);
978 ir_node *block = get_nodes_block(node);
979 ir_node *base = get_irn_n(node, n_ia32_base);
980 ir_node *index = get_irn_n(node, n_ia32_index);
981 ir_node *mem = get_irn_n(node, n_ia32_mem);
985 const ir_edge_t *edge;
987 ir_fprintf(stderr, "truning back AM in %+F\n", node);
989 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
990 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
992 ia32_copy_am_attrs(load, node);
993 set_irn_n(node, n_ia32_mem, new_NoMem());
995 if(get_ia32_am_arity(node) == ia32_am_unary) {
996 set_irn_n(node, n_ia32_unary_op, load_res);
997 } else if(get_ia32_am_arity(node) == ia32_am_binary) {
998 set_irn_n(node, n_ia32_binary_right, load_res);
999 } else if(get_ia32_am_arity(node) == ia32_am_ternary) {
1000 set_irn_n(node, n_ia32_binary_right, load_res);
1003 /* rewire mem-proj */
1004 if(get_irn_mode(node) == mode_T) {
1006 foreach_out_edge(node, edge) {
1007 ir_node *out = get_edge_src_irn(edge);
1008 if(get_Proj_proj(out) == pn_ia32_mem) {
1014 if(mem_proj != NULL) {
1015 set_Proj_pred(mem_proj, load);
1016 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1020 set_ia32_op_type(node, ia32_Normal);
1021 if(sched_is_scheduled(node))
1022 sched_add_before(node, load);
1025 static ir_node *flags_remat(ir_node *node, ir_node *after)
1027 /* we should turn back source address mode when rematerializing nodes */
1028 ia32_op_type_t type = get_ia32_op_type(node);
1031 if (type == ia32_AddrModeS) {
1033 } else if (type == ia32_AddrModeD) {
1034 /* TODO implement this later... */
1035 panic("found DestAM with flag user %+F this should not happen", node);
1037 assert(type == ia32_Normal);
1040 copy = exact_copy(node);
1041 sched_add_after(after, copy);
1047 * Called before the register allocator.
1048 * Calculate a block schedule here. We need it for the x87
1049 * simulator and the emitter.
1051 static void ia32_before_ra(void *self) {
1052 ia32_code_gen_t *cg = self;
1054 /* setup fpu rounding modes */
1055 ia32_setup_fpu_mode(cg);
1058 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1061 ia32_add_missing_keeps(cg);
1066 * Transforms a be_Reload into a ia32 Load.
1068 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1069 ir_graph *irg = get_irn_irg(node);
1070 dbg_info *dbg = get_irn_dbg_info(node);
1071 ir_node *block = get_nodes_block(node);
1072 ir_entity *ent = be_get_frame_entity(node);
1073 ir_mode *mode = get_irn_mode(node);
1074 ir_mode *spillmode = get_spill_mode(node);
1075 ir_node *noreg = ia32_new_NoReg_gp(cg);
1076 ir_node *sched_point = NULL;
1077 ir_node *ptr = get_irg_frame(irg);
1078 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1079 ir_node *new_op, *proj;
1080 const arch_register_t *reg;
1082 if (sched_is_scheduled(node)) {
1083 sched_point = sched_prev(node);
1086 if (mode_is_float(spillmode)) {
1088 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1090 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1092 else if (get_mode_size_bits(spillmode) == 128) {
1093 // Reload 128 bit sse registers
1094 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1097 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1099 set_ia32_op_type(new_op, ia32_AddrModeS);
1100 set_ia32_ls_mode(new_op, spillmode);
1101 set_ia32_frame_ent(new_op, ent);
1102 set_ia32_use_frame(new_op);
1104 DBG_OPT_RELOAD2LD(node, new_op);
1106 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1109 sched_add_after(sched_point, new_op);
1113 /* copy the register from the old node to the new Load */
1114 reg = arch_get_irn_register(cg->arch_env, node);
1115 arch_set_irn_register(cg->arch_env, new_op, reg);
1117 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1119 exchange(node, proj);
1123 * Transforms a be_Spill node into a ia32 Store.
1125 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1126 ir_graph *irg = get_irn_irg(node);
1127 dbg_info *dbg = get_irn_dbg_info(node);
1128 ir_node *block = get_nodes_block(node);
1129 ir_entity *ent = be_get_frame_entity(node);
1130 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1131 ir_mode *mode = get_spill_mode(spillval);
1132 ir_node *noreg = ia32_new_NoReg_gp(cg);
1133 ir_node *nomem = new_rd_NoMem(irg);
1134 ir_node *ptr = get_irg_frame(irg);
1135 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1137 ir_node *sched_point = NULL;
1139 if (sched_is_scheduled(node)) {
1140 sched_point = sched_prev(node);
1143 /* No need to spill unknown values... */
1144 if(is_ia32_Unknown_GP(val) ||
1145 is_ia32_Unknown_VFP(val) ||
1146 is_ia32_Unknown_XMM(val)) {
1151 exchange(node, store);
1155 if (mode_is_float(mode)) {
1157 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1159 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1160 } else if (get_mode_size_bits(mode) == 128) {
1161 // Spill 128 bit SSE registers
1162 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1163 } else if (get_mode_size_bits(mode) == 8) {
1164 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1166 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1169 set_ia32_op_type(store, ia32_AddrModeD);
1170 set_ia32_ls_mode(store, mode);
1171 set_ia32_frame_ent(store, ent);
1172 set_ia32_use_frame(store);
1173 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1174 DBG_OPT_SPILL2ST(node, store);
1177 sched_add_after(sched_point, store);
1181 exchange(node, store);
1184 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1185 ir_graph *irg = get_irn_irg(node);
1186 dbg_info *dbg = get_irn_dbg_info(node);
1187 ir_node *block = get_nodes_block(node);
1188 ir_node *noreg = ia32_new_NoReg_gp(cg);
1189 ir_node *frame = get_irg_frame(irg);
1191 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
1193 set_ia32_frame_ent(push, ent);
1194 set_ia32_use_frame(push);
1195 set_ia32_op_type(push, ia32_AddrModeS);
1196 set_ia32_ls_mode(push, mode_Is);
1198 sched_add_before(schedpoint, push);
1202 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1203 ir_graph *irg = get_irn_irg(node);
1204 dbg_info *dbg = get_irn_dbg_info(node);
1205 ir_node *block = get_nodes_block(node);
1206 ir_node *noreg = ia32_new_NoReg_gp(cg);
1207 ir_node *frame = get_irg_frame(irg);
1209 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1211 set_ia32_frame_ent(pop, ent);
1212 set_ia32_use_frame(pop);
1213 set_ia32_op_type(pop, ia32_AddrModeD);
1214 set_ia32_ls_mode(pop, mode_Is);
1216 sched_add_before(schedpoint, pop);
1221 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1222 ir_graph *irg = get_irn_irg(node);
1223 dbg_info *dbg = get_irn_dbg_info(node);
1224 ir_node *block = get_nodes_block(node);
1225 ir_mode *spmode = mode_Iu;
1226 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1229 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1230 arch_set_irn_register(cg->arch_env, sp, spreg);
1236 * Transform memperm, currently we do this the ugly way and produce
1237 * push/pop into/from memory cascades. This is possible without using
1240 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1241 ir_graph *irg = get_irn_irg(node);
1242 ir_node *block = get_nodes_block(node);
1246 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1247 const ir_edge_t *edge;
1248 const ir_edge_t *next;
1251 arity = be_get_MemPerm_entity_arity(node);
1252 pops = alloca(arity * sizeof(pops[0]));
1255 for(i = 0; i < arity; ++i) {
1256 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1257 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1258 ir_type *enttype = get_entity_type(inent);
1259 int entbits = get_type_size_bits(enttype);
1260 int entbits2 = get_type_size_bits(get_entity_type(outent));
1261 ir_node *mem = get_irn_n(node, i + 1);
1264 /* work around cases where entities have different sizes */
1265 if(entbits2 < entbits)
1267 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1269 push = create_push(cg, node, node, sp, mem, inent);
1270 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1272 // add another push after the first one
1273 push = create_push(cg, node, node, sp, mem, inent);
1274 add_ia32_am_offs_int(push, 4);
1275 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1278 set_irn_n(node, i, new_Bad());
1282 for(i = arity - 1; i >= 0; --i) {
1283 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1284 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1285 ir_type *enttype = get_entity_type(outent);
1286 int entbits = get_type_size_bits(enttype);
1287 int entbits2 = get_type_size_bits(get_entity_type(inent));
1290 /* work around cases where entities have different sizes */
1291 if(entbits2 < entbits)
1293 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1295 pop = create_pop(cg, node, node, sp, outent);
1296 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1298 add_ia32_am_offs_int(pop, 4);
1300 // add another pop after the first one
1301 pop = create_pop(cg, node, node, sp, outent);
1302 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1309 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1310 sched_add_before(node, keep);
1312 // exchange memprojs
1313 foreach_out_edge_safe(node, edge, next) {
1314 ir_node *proj = get_edge_src_irn(edge);
1315 int p = get_Proj_proj(proj);
1319 set_Proj_pred(proj, pops[p]);
1320 set_Proj_proj(proj, pn_ia32_Pop_M);
1324 arity = get_irn_arity(node);
1325 for(i = 0; i < arity; ++i) {
1326 set_irn_n(node, i, new_Bad());
1332 * Block-Walker: Calls the transform functions Spill and Reload.
1334 static void ia32_after_ra_walker(ir_node *block, void *env) {
1335 ir_node *node, *prev;
1336 ia32_code_gen_t *cg = env;
1338 /* beware: the schedule is changed here */
1339 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1340 prev = sched_prev(node);
1342 if (be_is_Reload(node)) {
1343 transform_to_Load(cg, node);
1344 } else if (be_is_Spill(node)) {
1345 transform_to_Store(cg, node);
1346 } else if(be_is_MemPerm(node)) {
1347 transform_MemPerm(cg, node);
1353 * Collects nodes that need frame entities assigned.
1355 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1357 be_fec_env_t *env = data;
1359 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1360 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1361 int align = get_mode_size_bytes(mode);
1362 be_node_needs_frame_entity(env, node, mode, align);
1363 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1364 && is_ia32_use_frame(node)) {
1365 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1366 const ir_mode *mode = get_ia32_ls_mode(node);
1367 const ia32_attr_t *attr = get_ia32_attr_const(node);
1368 int align = get_mode_size_bytes(mode);
1370 if(attr->data.need_64bit_stackent) {
1373 if(attr->data.need_32bit_stackent) {
1376 be_node_needs_frame_entity(env, node, mode, align);
1377 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1378 || is_ia32_vfld(node)) {
1379 const ir_mode *mode = get_ia32_ls_mode(node);
1381 be_node_needs_frame_entity(env, node, mode, align);
1382 } else if(is_ia32_FldCW(node)) {
1383 const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
1385 be_node_needs_frame_entity(env, node, mode, align);
1388 assert(is_ia32_St(node) ||
1389 is_ia32_xStoreSimple(node) ||
1390 is_ia32_vfst(node) ||
1391 is_ia32_vfist(node) ||
1392 is_ia32_FnstCW(node));
1399 * We transform Spill and Reload here. This needs to be done before
1400 * stack biasing otherwise we would miss the corrected offset for these nodes.
1402 static void ia32_after_ra(void *self) {
1403 ia32_code_gen_t *cg = self;
1404 ir_graph *irg = cg->irg;
1405 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1407 /* create and coalesce frame entities */
1408 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1409 be_assign_entities(fec_env);
1410 be_free_frame_entity_coalescer(fec_env);
1412 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1416 * Last touchups for the graph before emit: x87 simulation to replace the
1417 * virtual with real x87 instructions, creating a block schedule and peephole
1420 static void ia32_finish(void *self) {
1421 ia32_code_gen_t *cg = self;
1422 ir_graph *irg = cg->irg;
1424 ia32_finish_irg(irg, cg);
1426 /* we might have to rewrite x87 virtual registers */
1427 if (cg->do_x87_sim) {
1428 x87_simulate_graph(cg->arch_env, cg->birg);
1431 /* create block schedule, this also removes empty blocks which might
1432 * produce critical edges */
1433 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1435 /* do peephole optimisations */
1436 ia32_peephole_optimization(irg, cg);
1440 * Emits the code, closes the output file and frees
1441 * the code generator interface.
1443 static void ia32_codegen(void *self) {
1444 ia32_code_gen_t *cg = self;
1445 ir_graph *irg = cg->irg;
1447 ia32_gen_routine(cg, irg);
1451 /* remove it from the isa */
1454 assert(ia32_current_cg == cg);
1455 ia32_current_cg = NULL;
1457 /* de-allocate code generator */
1458 del_set(cg->reg_set);
1462 static void *ia32_cg_init(be_irg_t *birg);
1464 static const arch_code_generator_if_t ia32_code_gen_if = {
1466 ia32_before_abi, /* before abi introduce hook */
1469 ia32_before_sched, /* before scheduling hook */
1470 ia32_before_ra, /* before register allocation hook */
1471 ia32_after_ra, /* after register allocation hook */
1472 ia32_finish, /* called before codegen */
1473 ia32_codegen /* emit && done */
1477 * Initializes a IA32 code generator.
1479 static void *ia32_cg_init(be_irg_t *birg) {
1480 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1481 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1483 cg->impl = &ia32_code_gen_if;
1484 cg->irg = birg->irg;
1485 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1486 cg->arch_env = birg->main_env->arch_env;
1489 cg->blk_sched = NULL;
1490 cg->fp_kind = isa->fp_kind;
1491 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1493 /* copy optimizations from isa for easier access */
1495 cg->arch = isa->arch;
1496 cg->opt_arch = isa->opt_arch;
1502 if (isa->name_obst) {
1503 obstack_free(isa->name_obst, NULL);
1504 obstack_init(isa->name_obst);
1508 cur_reg_set = cg->reg_set;
1510 ia32_irn_ops.cg = cg;
1512 assert(ia32_current_cg == NULL);
1513 ia32_current_cg = cg;
1515 return (arch_code_generator_t *)cg;
1520 /*****************************************************************
1521 * ____ _ _ _____ _____
1522 * | _ \ | | | | |_ _|/ ____| /\
1523 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1524 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1525 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1526 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1528 *****************************************************************/
1531 * Set output modes for GCC
1533 static const tarval_mode_info mo_integer = {
1540 * set the tarval output mode of all integer modes to decimal
1542 static void set_tarval_output_modes(void)
1546 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1547 ir_mode *mode = get_irp_mode(i);
1549 if (mode_is_int(mode))
1550 set_tarval_mode_output_option(mode, &mo_integer);
1554 const arch_isa_if_t ia32_isa_if;
1557 * The template that generates a new ISA object.
1558 * Note that this template can be changed by command line
1561 static ia32_isa_t ia32_isa_template = {
1563 &ia32_isa_if, /* isa interface implementation */
1564 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1565 &ia32_gp_regs[REG_EBP], /* base pointer register */
1566 -1, /* stack direction */
1567 NULL, /* main environment */
1568 7, /* costs for a spill instruction */
1569 5, /* costs for a reload instruction */
1571 NULL_EMITTER, /* emitter environment */
1572 NULL, /* 16bit register names */
1573 NULL, /* 8bit register names */
1574 NULL, /* 8bit register names high */
1578 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1579 IA32_OPT_DOAM | /* optimize address mode default: on */
1580 IA32_OPT_LEA | /* optimize for LEAs default: on */
1581 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1582 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1583 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1584 arch_pentium_4, /* instruction architecture */
1585 arch_pentium_4, /* optimize for architecture */
1586 fp_x87, /* floating point mode */
1587 NULL, /* current code generator */
1589 NULL, /* name obstack */
1590 0 /* name obst size */
1594 static void set_arch_costs(enum cpu_support arch);
1597 * Initializes the backend ISA.
1599 static void *ia32_init(FILE *file_handle) {
1600 static int inited = 0;
1607 set_tarval_output_modes();
1609 isa = xmalloc(sizeof(*isa));
1610 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1612 if(mode_fpcw == NULL) {
1613 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1616 ia32_register_init();
1617 ia32_create_opcodes();
1619 set_arch_costs(isa->opt_arch);
1621 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1622 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1623 /* no SSE2 for these cpu's */
1624 isa->fp_kind = fp_x87;
1626 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1627 /* Pentium 4 don't like inc and dec instructions */
1628 isa->opt &= ~IA32_OPT_INCDEC;
1631 be_emit_init_env(&isa->emit, file_handle);
1632 isa->regs_16bit = pmap_create();
1633 isa->regs_8bit = pmap_create();
1634 isa->regs_8bit_high = pmap_create();
1635 isa->types = pmap_create();
1636 isa->tv_ent = pmap_create();
1637 isa->cpu = ia32_init_machine_description();
1639 ia32_build_16bit_reg_map(isa->regs_16bit);
1640 ia32_build_8bit_reg_map(isa->regs_8bit);
1641 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1644 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1645 obstack_init(isa->name_obst);
1648 /* enter the ISA object into the intrinsic environment */
1649 intrinsic_env.isa = isa;
1650 ia32_handle_intrinsics();
1652 /* needed for the debug support */
1653 be_gas_emit_switch_section(&isa->emit, GAS_SECTION_TEXT);
1654 be_emit_cstring(&isa->emit, ".Ltext0:\n");
1655 be_emit_write_line(&isa->emit);
1657 /* we mark referenced global entities, so we can only emit those which
1658 * are actually referenced. (Note: you mustn't use the type visited flag
1659 * elsewhere in the backend)
1661 inc_master_type_visited();
1669 * Closes the output file and frees the ISA structure.
1671 static void ia32_done(void *self) {
1672 ia32_isa_t *isa = self;
1674 /* emit now all global declarations */
1675 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
1677 pmap_destroy(isa->regs_16bit);
1678 pmap_destroy(isa->regs_8bit);
1679 pmap_destroy(isa->regs_8bit_high);
1680 pmap_destroy(isa->tv_ent);
1681 pmap_destroy(isa->types);
1684 obstack_free(isa->name_obst, NULL);
1687 be_emit_destroy_env(&isa->emit);
1694 * Return the number of register classes for this architecture.
1695 * We report always these:
1696 * - the general purpose registers
1697 * - the SSE floating point register set
1698 * - the virtual floating point registers
1699 * - the SSE vector register set
1701 static int ia32_get_n_reg_class(const void *self) {
1707 * Return the register class for index i.
1709 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i)
1712 assert(i >= 0 && i < N_CLASSES);
1713 return &ia32_reg_classes[i];
1717 * Get the register class which shall be used to store a value of a given mode.
1718 * @param self The this pointer.
1719 * @param mode The mode in question.
1720 * @return A register class which can hold values of the given mode.
1722 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1723 const ia32_isa_t *isa = self;
1724 if (mode_is_float(mode)) {
1725 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1728 return &ia32_reg_classes[CLASS_ia32_gp];
1732 * Get the ABI restrictions for procedure calls.
1733 * @param self The this pointer.
1734 * @param method_type The type of the method (procedure) in question.
1735 * @param abi The abi object to be modified
1737 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1738 const ia32_isa_t *isa = self;
1743 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1745 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1747 /* set abi flags for calls */
1748 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1749 call_flags.bits.store_args_sequential = use_push;
1750 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1751 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1752 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1754 /* set parameter passing style */
1755 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1757 if (get_method_variadicity(method_type) == variadicity_variadic) {
1758 /* pass all parameters of a variadic function on the stack */
1761 cc = get_method_calling_convention(method_type);
1762 if (get_method_additional_properties(method_type) & mtp_property_private) {
1763 /* set the calling conventions to register parameter */
1764 cc = (cc & ~cc_bits) | cc_reg_param;
1767 n = get_method_n_params(method_type);
1768 for (i = regnum = 0; i < n; i++) {
1769 const ir_mode *mode;
1770 const arch_register_t *reg = NULL;
1772 tp = get_method_param_type(method_type, i);
1773 mode = get_type_mode(tp);
1775 reg = ia32_get_RegParam_reg(isa->cg, cc, regnum, mode);
1778 be_abi_call_param_reg(abi, i, reg);
1781 be_abi_call_param_stack(abi, i, 4, 0, 0);
1785 /* set return registers */
1786 n = get_method_n_ress(method_type);
1788 assert(n <= 2 && "more than two results not supported");
1790 /* In case of 64bit returns, we will have two 32bit values */
1792 tp = get_method_res_type(method_type, 0);
1793 mode = get_type_mode(tp);
1795 assert(!mode_is_float(mode) && "two FP results not supported");
1797 tp = get_method_res_type(method_type, 1);
1798 mode = get_type_mode(tp);
1800 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1802 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1803 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1806 const arch_register_t *reg;
1808 tp = get_method_res_type(method_type, 0);
1809 assert(is_atomic_type(tp));
1810 mode = get_type_mode(tp);
1812 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1814 be_abi_call_res_reg(abi, 0, reg);
1819 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
1824 return &ia32_irn_ops;
1827 const arch_irn_handler_t ia32_irn_handler = {
1831 const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
1834 return &ia32_irn_handler;
1837 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1841 if(!is_ia32_irn(irn)) {
1845 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1846 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1847 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1848 || is_ia32_Immediate(irn))
1855 * Initializes the code generator interface.
1857 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1860 return &ia32_code_gen_if;
1864 * Returns the estimated execution time of an ia32 irn.
1866 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1867 const arch_env_t *arch_env = env;
1868 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1871 list_sched_selector_t ia32_sched_selector;
1874 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1876 static const list_sched_selector_t *ia32_get_list_sched_selector(
1877 const void *self, list_sched_selector_t *selector)
1880 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1881 ia32_sched_selector.exectime = ia32_sched_exectime;
1882 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1883 return &ia32_sched_selector;
1886 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1893 * Returns the necessary byte alignment for storing a register of given class.
1895 static int ia32_get_reg_class_alignment(const void *self,
1896 const arch_register_class_t *cls)
1898 ir_mode *mode = arch_register_class_mode(cls);
1899 int bytes = get_mode_size_bytes(mode);
1902 if (mode_is_float(mode) && bytes > 8)
1907 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1908 const void *self, const ir_node *irn)
1910 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1911 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1912 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1915 static const be_execution_unit_t *_allowed_units_GP[] = {
1916 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1917 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1918 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1919 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1920 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1921 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1922 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1925 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1926 &be_machine_execution_units_DUMMY[0],
1929 static const be_execution_unit_t **_units_callret[] = {
1930 _allowed_units_BRANCH,
1933 static const be_execution_unit_t **_units_other[] = {
1937 static const be_execution_unit_t **_units_dummy[] = {
1938 _allowed_units_DUMMY,
1941 const be_execution_unit_t ***ret;
1944 if (is_ia32_irn(irn)) {
1945 ret = get_ia32_exec_units(irn);
1947 else if (is_be_node(irn)) {
1948 if (be_is_Call(irn) || be_is_Return(irn)) {
1949 ret = _units_callret;
1951 else if (be_is_Barrier(irn)) {
1966 * Return the abstract ia32 machine.
1968 static const be_machine_t *ia32_get_machine(const void *self) {
1969 const ia32_isa_t *isa = self;
1974 * Return irp irgs in the desired order.
1976 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
1984 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1985 * @return 1 if allowed, 0 otherwise
1987 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1997 ir_node *pred = get_Proj_pred(sel);
1999 ir_node *left = get_Cmp_left(pred);
2000 ir_mode *cmp_mode = get_irn_mode(left);
2001 if(mode_is_float(cmp_mode))
2007 /* check the Phi nodes */
2008 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2009 ir_mode *mode = get_irn_mode(phi);
2011 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2018 typedef struct insn_const {
2019 int add_cost; /**< cost of an add instruction */
2020 int lea_cost; /**< cost of a lea instruction */
2021 int const_shf_cost; /**< cost of a constant shift instruction */
2022 int cost_mul_start; /**< starting cost of a multiply instruction */
2023 int cost_mul_bit; /**< cost of multiply for every set bit */
2026 /* costs for the i386 */
2027 static const insn_const i386_cost = {
2028 1, /* cost of an add instruction */
2029 1, /* cost of a lea instruction */
2030 2, /* cost of a constant shift instruction */
2031 6, /* starting cost of a multiply instruction */
2032 1 /* cost of multiply for every set bit */
2035 /* costs for the i486 */
2036 static const insn_const i486_cost = {
2037 1, /* cost of an add instruction */
2038 1, /* cost of a lea instruction */
2039 2, /* cost of a constant shift instruction */
2040 12, /* starting cost of a multiply instruction */
2041 1 /* cost of multiply for every set bit */
2044 /* costs for the Pentium */
2045 static const insn_const pentium_cost = {
2046 1, /* cost of an add instruction */
2047 1, /* cost of a lea instruction */
2048 1, /* cost of a constant shift instruction */
2049 11, /* starting cost of a multiply instruction */
2050 0 /* cost of multiply for every set bit */
2053 /* costs for the Pentium Pro */
2054 static const insn_const pentiumpro_cost = {
2055 1, /* cost of an add instruction */
2056 1, /* cost of a lea instruction */
2057 1, /* cost of a constant shift instruction */
2058 4, /* starting cost of a multiply instruction */
2059 0 /* cost of multiply for every set bit */
2062 /* costs for the K6 */
2063 static const insn_const k6_cost = {
2064 1, /* cost of an add instruction */
2065 2, /* cost of a lea instruction */
2066 1, /* cost of a constant shift instruction */
2067 3, /* starting cost of a multiply instruction */
2068 0 /* cost of multiply for every set bit */
2071 /* costs for the Athlon */
2072 static const insn_const athlon_cost = {
2073 1, /* cost of an add instruction */
2074 2, /* cost of a lea instruction */
2075 1, /* cost of a constant shift instruction */
2076 5, /* starting cost of a multiply instruction */
2077 0 /* cost of multiply for every set bit */
2080 /* costs for the Pentium 4 */
2081 static const insn_const pentium4_cost = {
2082 1, /* cost of an add instruction */
2083 3, /* cost of a lea instruction */
2084 4, /* cost of a constant shift instruction */
2085 15, /* starting cost of a multiply instruction */
2086 0 /* cost of multiply for every set bit */
2089 /* costs for the Core */
2090 static const insn_const core_cost = {
2091 1, /* cost of an add instruction */
2092 1, /* cost of a lea instruction */
2093 1, /* cost of a constant shift instruction */
2094 10, /* starting cost of a multiply instruction */
2095 0 /* cost of multiply for every set bit */
2098 /* costs for the generic */
2099 static const insn_const generic_cost = {
2100 1, /* cost of an add instruction */
2101 2, /* cost of a lea instruction */
2102 1, /* cost of a constant shift instruction */
2103 4, /* starting cost of a multiply instruction */
2104 0 /* cost of multiply for every set bit */
2107 static const insn_const *arch_costs = &generic_cost;
2109 static void set_arch_costs(enum cpu_support arch) {
2112 arch_costs = &i386_cost;
2115 arch_costs = &i486_cost;
2118 case arch_pentium_mmx:
2119 arch_costs = &pentium_cost;
2121 case arch_pentium_pro:
2122 case arch_pentium_2:
2123 case arch_pentium_3:
2124 arch_costs = &pentiumpro_cost;
2126 case arch_pentium_4:
2127 arch_costs = &pentium4_cost;
2129 case arch_pentium_m:
2130 arch_costs = &pentiumpro_cost;
2133 arch_costs = &core_cost;
2136 arch_costs = &k6_cost;
2139 case arch_athlon_64:
2141 arch_costs = &athlon_cost;
2145 arch_costs = &generic_cost;
2150 * Evaluate a given simple instruction.
2152 static int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
2157 cost = arch_costs->cost_mul_start;
2158 if (arch_costs->cost_mul_bit > 0) {
2159 char *bitstr = get_tarval_bitpattern(tv);
2162 for (i = 0; bitstr[i] != '\0'; ++i) {
2163 if (bitstr[i] == '1') {
2164 cost += arch_costs->cost_mul_bit;
2171 return arch_costs->lea_cost;
2174 return arch_costs->add_cost;
2176 return arch_costs->const_shf_cost;
2178 return arch_costs->add_cost;
2185 * Returns the libFirm configuration parameter for this backend.
2187 static const backend_params *ia32_get_libfirm_params(void) {
2188 static const ir_settings_if_conv_t ifconv = {
2189 4, /* maxdepth, doesn't matter for Psi-conversion */
2190 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2192 static const ir_settings_arch_dep_t ad = {
2193 1, /* also use subs */
2194 4, /* maximum shifts */
2195 31, /* maximum shift amount */
2196 ia32_evaluate_insn, /* evaluate the instruction sequence */
2198 1, /* allow Mulhs */
2199 1, /* allow Mulus */
2200 32 /* Mulh allowed up to 32 bit */
2202 static backend_params p = {
2203 1, /* need dword lowering */
2204 1, /* support inline assembly */
2205 NULL, /* no additional opcodes */
2206 NULL, /* will be set later */
2207 ia32_create_intrinsic_fkt,
2208 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2209 NULL, /* will be set below */
2213 p.if_conv_info = &ifconv;
2217 /* instruction set architectures. */
2218 static const lc_opt_enum_int_items_t arch_items[] = {
2219 { "386", arch_i386, },
2220 { "486", arch_i486, },
2221 { "pentium", arch_pentium, },
2222 { "586", arch_pentium, },
2223 { "pentiumpro", arch_pentium_pro, },
2224 { "686", arch_pentium_pro, },
2225 { "pentiummmx", arch_pentium_mmx, },
2226 { "pentium2", arch_pentium_2, },
2227 { "p2", arch_pentium_2, },
2228 { "pentium3", arch_pentium_3, },
2229 { "p3", arch_pentium_3, },
2230 { "pentium4", arch_pentium_4, },
2231 { "p4", arch_pentium_4, },
2232 { "pentiumm", arch_pentium_m, },
2233 { "pm", arch_pentium_m, },
2234 { "core", arch_core, },
2236 { "athlon", arch_athlon, },
2237 { "athlon64", arch_athlon_64, },
2238 { "opteron", arch_opteron, },
2239 { "generic", arch_generic, },
2243 static lc_opt_enum_int_var_t arch_var = {
2244 &ia32_isa_template.arch, arch_items
2247 static lc_opt_enum_int_var_t opt_arch_var = {
2248 &ia32_isa_template.opt_arch, arch_items
2251 static const lc_opt_enum_int_items_t fp_unit_items[] = {
2253 { "sse2", fp_sse2 },
2257 static lc_opt_enum_int_var_t fp_unit_var = {
2258 &ia32_isa_template.fp_kind, fp_unit_items
2261 static const lc_opt_enum_int_items_t gas_items[] = {
2262 { "normal", GAS_FLAVOUR_NORMAL },
2263 { "mingw", GAS_FLAVOUR_MINGW },
2267 static lc_opt_enum_int_var_t gas_var = {
2268 (int*) &be_gas_flavour, gas_items
2271 static const lc_opt_table_entry_t ia32_options[] = {
2272 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
2273 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
2274 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
2275 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
2276 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
2277 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
2278 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
2279 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
2280 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2284 const arch_isa_if_t ia32_isa_if = {
2287 ia32_get_n_reg_class,
2289 ia32_get_reg_class_for_mode,
2291 ia32_get_irn_handler,
2292 ia32_get_code_generator_if,
2293 ia32_get_list_sched_selector,
2294 ia32_get_ilp_sched_selector,
2295 ia32_get_reg_class_alignment,
2296 ia32_get_libfirm_params,
2297 ia32_get_allowed_execution_units,
2302 void ia32_init_emitter(void);
2303 void ia32_init_finish(void);
2304 void ia32_init_optimize(void);
2305 void ia32_init_transform(void);
2306 void ia32_init_x87(void);
2308 void be_init_arch_ia32(void)
2310 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2311 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2313 lc_opt_add_table(ia32_grp, ia32_options);
2314 be_register_isa_if("ia32", &ia32_isa_if);
2316 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2318 ia32_init_emitter();
2320 ia32_init_optimize();
2321 ia32_init_transform();
2325 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);