2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This is the main ia32 firm backend driver.
23 * @author Christian Wuerdig
30 #include <libcore/lc_opts.h>
31 #include <libcore/lc_opts_enum.h>
35 #include "pseudo_irg.h"
40 #include "iredges_t.h"
54 #include "../beirg_t.h"
55 #include "../benode_t.h"
56 #include "../belower.h"
57 #include "../besched_t.h"
60 #include "../beirgmod.h"
61 #include "../be_dbgout.h"
62 #include "../beblocksched.h"
63 #include "../bemachine.h"
64 #include "../beilpsched.h"
65 #include "../bespillslots.h"
66 #include "../bemodule.h"
67 #include "../begnuas.h"
68 #include "../bestate.h"
69 #include "../beflags.h"
71 #include "bearch_ia32_t.h"
73 #include "ia32_new_nodes.h"
74 #include "gen_ia32_regalloc_if.h"
75 #include "gen_ia32_machine.h"
76 #include "ia32_transform.h"
77 #include "ia32_emitter.h"
78 #include "ia32_map_regs.h"
79 #include "ia32_optimize.h"
81 #include "ia32_dbg_stat.h"
82 #include "ia32_finish.h"
83 #include "ia32_util.h"
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 static set *cur_reg_set = NULL;
91 ir_mode *mode_fpcw = NULL;
92 ia32_code_gen_t *ia32_current_cg = NULL;
95 * The environment for the intrinsic mapping.
97 static ia32_intrinsic_env_t intrinsic_env = {
99 NULL, /* the irg, these entities belong to */
100 NULL, /* entity for first div operand (move into FPU) */
101 NULL, /* entity for second div operand (move into FPU) */
102 NULL, /* entity for converts ll -> d */
103 NULL, /* entity for converts d -> ll */
104 NULL, /* entity for __divdi3 library call */
105 NULL, /* entity for __moddi3 library call */
106 NULL, /* entity for __udivdi3 library call */
107 NULL, /* entity for __umoddi3 library call */
108 NULL, /* bias value for conversion from float to unsigned 64 */
112 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
114 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
115 create_const_node_func func,
116 const arch_register_t* reg)
118 ir_node *block, *res;
123 block = get_irg_start_block(cg->irg);
124 res = func(NULL, cg->irg, block);
125 arch_set_irn_register(cg->arch_env, res, reg);
128 add_irn_dep(get_irg_end(cg->irg), res);
129 /* add_irn_dep(get_irg_start(cg->irg), res); */
134 /* Creates the unique per irg GP NoReg node. */
135 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
136 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
137 &ia32_gp_regs[REG_GP_NOREG]);
140 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
141 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
142 &ia32_vfp_regs[REG_VFP_NOREG]);
145 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
146 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
147 &ia32_xmm_regs[REG_XMM_NOREG]);
150 /* Creates the unique per irg FP NoReg node. */
151 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
152 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
155 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
156 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
157 &ia32_gp_regs[REG_GP_UKNWN]);
160 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
161 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
162 &ia32_vfp_regs[REG_VFP_UKNWN]);
165 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
166 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
167 &ia32_xmm_regs[REG_XMM_UKNWN]);
170 ir_node *ia32_new_Fpu_truncate(ia32_code_gen_t *cg) {
171 return create_const(cg, &cg->fpu_trunc_mode, new_rd_ia32_ChangeCW,
172 &ia32_fp_cw_regs[REG_FPCW]);
177 * Returns gp_noreg or fp_noreg, depending in input requirements.
179 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
180 const arch_register_req_t *req;
182 req = arch_get_register_req(cg->arch_env, irn, pos);
183 assert(req != NULL && "Missing register requirements");
184 if (req->cls == &ia32_reg_classes[CLASS_ia32_gp])
185 return ia32_new_NoReg_gp(cg);
187 return ia32_new_NoReg_fp(cg);
190 /**************************************************
193 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
194 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
195 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
196 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
199 **************************************************/
202 * Return register requirements for an ia32 node.
203 * If the node returns a tuple (mode_T) then the proj's
204 * will be asked for this information.
206 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self,
210 long node_pos = pos == -1 ? 0 : pos;
211 ir_mode *mode = is_Block(node) ? NULL : get_irn_mode(node);
214 if (is_Block(node) || mode == mode_X) {
215 return arch_no_register_req;
218 if (mode == mode_T && pos < 0) {
219 return arch_no_register_req;
224 return arch_no_register_req;
227 return arch_no_register_req;
230 node_pos = (pos == -1) ? get_Proj_proj(node) : pos;
231 node = skip_Proj_const(node);
234 if (is_ia32_irn(node)) {
235 const arch_register_req_t *req;
237 req = get_ia32_in_req(node, pos);
239 req = get_ia32_out_req(node, node_pos);
246 /* unknowns should be transformed already */
247 assert(!is_Unknown(node));
249 return arch_no_register_req;
252 static void ia32_set_irn_reg(const void *self, ir_node *irn,
253 const arch_register_t *reg)
258 if (get_irn_mode(irn) == mode_X) {
263 pos = get_Proj_proj(irn);
264 irn = skip_Proj(irn);
267 if (is_ia32_irn(irn)) {
268 const arch_register_t **slots;
270 slots = get_ia32_slots(irn);
273 ia32_set_firm_reg(irn, reg, cur_reg_set);
277 static const arch_register_t *ia32_get_irn_reg(const void *self,
281 const arch_register_t *reg = NULL;
286 if (get_irn_mode(irn) == mode_X) {
290 pos = get_Proj_proj(irn);
291 irn = skip_Proj_const(irn);
294 if (is_ia32_irn(irn)) {
295 const arch_register_t **slots;
296 slots = get_ia32_slots(irn);
299 reg = ia32_get_firm_reg(irn, cur_reg_set);
305 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
306 arch_irn_class_t classification = arch_irn_class_normal;
309 irn = skip_Proj_const(irn);
312 classification |= arch_irn_class_branch;
314 if (! is_ia32_irn(irn))
315 return classification & ~arch_irn_class_normal;
318 classification |= arch_irn_class_load;
321 classification |= arch_irn_class_store;
323 if (is_ia32_need_stackent(irn))
324 classification |= arch_irn_class_reload;
326 return classification;
329 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
330 arch_irn_flags_t flags = arch_irn_flags_none;
334 return arch_irn_flags_ignore;
336 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
337 ir_node *pred = get_Proj_pred(irn);
339 if(is_ia32_irn(pred)) {
340 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
346 if (is_ia32_irn(irn)) {
347 flags |= get_ia32_flags(irn);
354 * The IA32 ABI callback object.
357 be_abi_call_flags_bits_t flags; /**< The call flags. */
358 const arch_isa_t *isa; /**< The ISA handle. */
359 const arch_env_t *aenv; /**< The architecture environment. */
360 ir_graph *irg; /**< The associated graph. */
363 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
365 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
368 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
370 set_ia32_frame_ent(irn, ent);
373 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
374 const ia32_irn_ops_t *ops = self;
376 if (get_ia32_frame_ent(irn)) {
377 if (is_ia32_Pop(irn)) {
378 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
380 /* Pop nodes modify the stack pointer before calculating the destination
381 * address, so fix this here
387 add_ia32_am_offs_int(irn, bias);
391 static int ia32_get_sp_bias(const void *self, const ir_node *node)
395 if (is_ia32_Push(node))
398 if (is_ia32_Pop(node))
405 * Put all registers which are saved by the prologue/epilogue in a set.
407 * @param self The callback object.
408 * @param s The result set.
410 static void ia32_abi_dont_save_regs(void *self, pset *s)
412 ia32_abi_env_t *env = self;
413 if(env->flags.try_omit_fp)
414 pset_insert_ptr(s, env->isa->bp);
418 * Generate the routine prologue.
420 * @param self The callback object.
421 * @param mem A pointer to the mem node. Update this if you define new memory.
422 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
424 * @return The register which shall be used as a stack frame base.
426 * All nodes which define registers in @p reg_map must keep @p reg_map current.
428 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
430 ia32_abi_env_t *env = self;
431 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
432 ia32_code_gen_t *cg = isa->cg;
434 if (! env->flags.try_omit_fp) {
435 ir_node *bl = get_irg_start_block(env->irg);
436 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
437 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
438 ir_node *noreg = ia32_new_NoReg_gp(cg);
441 /* ALL nodes representing bp must be set to ignore. */
442 be_node_set_flags(get_Proj_pred(curr_bp), BE_OUT_POS(get_Proj_proj(curr_bp)), arch_irn_flags_ignore);
445 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, *mem, curr_bp, curr_sp);
446 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
447 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
449 /* the push must have SP out register */
450 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
451 set_ia32_flags(push, arch_irn_flags_ignore);
453 /* move esp to ebp */
454 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
455 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
456 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
457 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
459 /* beware: the copy must be done before any other sp use */
460 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
461 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
462 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
463 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
465 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
466 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
475 * Generate the routine epilogue.
476 * @param self The callback object.
477 * @param bl The block for the epilog
478 * @param mem A pointer to the mem node. Update this if you define new memory.
479 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
480 * @return The register which shall be used as a stack frame base.
482 * All nodes which define registers in @p reg_map must keep @p reg_map current.
484 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
486 ia32_abi_env_t *env = self;
487 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
488 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
490 if (env->flags.try_omit_fp) {
491 /* simply remove the stack frame here */
492 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
493 add_irn_dep(curr_sp, *mem);
495 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
496 ia32_code_gen_t *cg = isa->cg;
497 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
498 ir_graph *irg = current_ir_graph;
500 if (ARCH_AMD(isa->opt_arch)) {
504 leave = new_rd_ia32_Leave(NULL, irg, bl, curr_sp, curr_bp);
505 set_ia32_flags(leave, arch_irn_flags_ignore);
506 curr_bp = new_r_Proj(irg, bl, leave, mode_bp, pn_ia32_Leave_frame);
507 curr_sp = new_r_Proj(irg, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
509 ir_node *noreg = ia32_new_NoReg_gp(cg);
512 /* the old SP is not needed anymore (kill the proj) */
513 assert(is_Proj(curr_sp));
514 be_kill_node(curr_sp);
516 /* copy ebp to esp */
517 curr_sp = be_new_Copy(&ia32_reg_classes[CLASS_ia32_gp], irg, bl, curr_bp);
518 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
519 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
522 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, *mem, curr_sp);
523 set_ia32_flags(pop, arch_irn_flags_ignore);
524 curr_bp = new_r_Proj(irg, bl, pop, mode_bp, pn_ia32_Pop_res);
525 curr_sp = new_r_Proj(irg, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
527 *mem = new_r_Proj(irg, bl, pop, mode_M, pn_ia32_Pop_M);
529 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
530 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
533 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
534 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
538 * Initialize the callback object.
539 * @param call The call object.
540 * @param aenv The architecture environment.
541 * @param irg The graph with the method.
542 * @return Some pointer. This pointer is passed to all other callback functions as self object.
544 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
546 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
547 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
548 env->flags = fl.bits;
551 env->isa = aenv->isa;
556 * Destroy the callback object.
557 * @param self The callback object.
559 static void ia32_abi_done(void *self) {
564 * Produces the type which sits between the stack args and the locals on the stack.
565 * it will contain the return address and space to store the old base pointer.
566 * @return The Firm type modeling the ABI between type.
568 static ir_type *ia32_abi_get_between_type(void *self)
570 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
571 static ir_type *omit_fp_between_type = NULL;
572 static ir_type *between_type = NULL;
574 ia32_abi_env_t *env = self;
576 if (! between_type) {
577 ir_entity *old_bp_ent;
578 ir_entity *ret_addr_ent;
579 ir_entity *omit_fp_ret_addr_ent;
581 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
582 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
584 between_type = new_type_struct(IDENT("ia32_between_type"));
585 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
586 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
588 set_entity_offset(old_bp_ent, 0);
589 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
590 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
591 set_type_state(between_type, layout_fixed);
593 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
594 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
596 set_entity_offset(omit_fp_ret_addr_ent, 0);
597 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
598 set_type_state(omit_fp_between_type, layout_fixed);
601 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
606 * Get the estimated cycle count for @p irn.
608 * @param self The this pointer.
609 * @param irn The node.
611 * @return The estimated cycle count for this operation
613 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
616 ia32_op_type_t op_tp;
617 const ia32_irn_ops_t *ops = self;
621 if (!is_ia32_irn(irn))
624 assert(is_ia32_irn(irn));
626 cost = get_ia32_latency(irn);
627 op_tp = get_ia32_op_type(irn);
629 if (is_ia32_CopyB(irn)) {
631 if (ARCH_INTEL(ops->cg->arch))
634 else if (is_ia32_CopyB_i(irn)) {
635 int size = get_ia32_pncode(irn);
636 cost = 20 + (int)ceil((4/3) * size);
637 if (ARCH_INTEL(ops->cg->arch))
640 /* in case of address mode operations add additional cycles */
641 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
643 In case of stack access and access to fixed addresses add 5 cycles
644 (we assume they are in cache), other memory operations cost 20
647 if(is_ia32_use_frame(irn) ||
648 (is_ia32_NoReg_GP(get_irn_n(irn, 0)) &&
649 is_ia32_NoReg_GP(get_irn_n(irn, 1)))) {
660 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
662 * @param irn The original operation
663 * @param i Index of the argument we want the inverse operation to yield
664 * @param inverse struct to be filled with the resulting inverse op
665 * @param obstack The obstack to use for allocation of the returned nodes array
666 * @return The inverse operation or NULL if operation invertible
668 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
672 ir_node *block, *noreg, *nomem;
676 /* we cannot invert non-ia32 irns */
677 if (! is_ia32_irn(irn))
680 /* operand must always be a real operand (not base, index or mem) */
681 if (i != n_ia32_binary_left && i != n_ia32_binary_right)
684 /* we don't invert address mode operations */
685 if (get_ia32_op_type(irn) != ia32_Normal)
688 /* TODO: adjust for new immediates... */
689 ir_fprintf(stderr, "TODO: fix get_inverse for new immediates (%+F)\n",
693 irg = get_irn_irg(irn);
694 block = get_nodes_block(irn);
695 mode = get_irn_mode(irn);
696 irn_mode = get_irn_mode(irn);
697 noreg = get_irn_n(irn, 0);
698 nomem = new_r_NoMem(irg);
699 dbg = get_irn_dbg_info(irn);
701 /* initialize structure */
702 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
706 switch (get_ia32_irn_opcode(irn)) {
709 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
710 /* we have an add with a const here */
711 /* invers == add with negated const */
712 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
714 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
715 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
716 set_ia32_commutative(inverse->nodes[0]);
718 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
719 /* we have an add with a symconst here */
720 /* invers == sub with const */
721 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
723 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
726 /* normal add: inverse == sub */
727 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, i ^ 1));
734 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
735 /* we have a sub with a const/symconst here */
736 /* invers == add with this const */
737 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
738 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
739 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
743 if (i == n_ia32_binary_left) {
744 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, nomem, (ir_node*) irn, get_irn_n(irn, 3));
747 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, n_ia32_binary_left), (ir_node*) irn);
755 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
756 /* xor with const: inverse = xor */
757 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, get_irn_n(irn, i), noreg);
758 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
759 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
763 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, nomem, (ir_node *) irn, get_irn_n(irn, i));
769 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, (ir_node*) irn);
774 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, (ir_node*) irn);
779 /* inverse operation not supported */
786 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
788 if(mode_is_float(mode))
795 * Get the mode that should be used for spilling value node
797 static ir_mode *get_spill_mode(const ir_node *node)
799 ir_mode *mode = get_irn_mode(node);
800 return get_spill_mode_mode(mode);
804 * Checks whether an addressmode reload for a node with mode mode is compatible
805 * with a spillslot of mode spill_mode
807 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
809 if(mode_is_float(mode)) {
810 return mode == spillmode;
817 * Check if irn can load it's operand at position i from memory (source addressmode).
818 * @param self Pointer to irn ops itself
819 * @param irn The irn to be checked
820 * @param i The operands position
821 * @return Non-Zero if operand can be loaded
823 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
824 ir_node *op = get_irn_n(irn, i);
825 const ir_mode *mode = get_irn_mode(op);
826 const ir_mode *spillmode = get_spill_mode(op);
829 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
830 get_ia32_am_arity(irn) != 2 || /* must be a binary operation TODO is this necessary? */
831 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
832 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
833 ! ia32_is_spillmode_compatible(mode, spillmode) ||
834 (i != n_ia32_binary_left && i != n_ia32_binary_right) || /* a "real" operand position must be requested */
835 is_ia32_use_frame(irn)) /* must not already use frame */
838 if (i == n_ia32_binary_left) {
839 const arch_register_req_t *req;
840 if(!is_ia32_commutative(irn))
842 /* we can't swap left/right for limited registers
843 * (As this (currently) breaks constraint handling copies)
845 req = get_ia32_in_req(irn, n_ia32_binary_left);
846 if(req->type & arch_register_req_type_limited) {
854 static void ia32_perform_memory_operand(const void *self, ir_node *irn,
855 ir_node *spill, unsigned int i)
857 const ia32_irn_ops_t *ops = self;
858 ia32_code_gen_t *cg = ops->cg;
860 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
862 if (i == n_ia32_binary_left) {
863 ia32_swap_left_right(irn);
866 set_ia32_op_type(irn, ia32_AddrModeS);
867 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
868 set_ia32_use_frame(irn);
869 set_ia32_need_stackent(irn);
871 set_irn_n(irn, n_ia32_base, get_irg_frame(get_irn_irg(irn)));
872 set_irn_n(irn, n_ia32_binary_right, ia32_get_admissible_noreg(cg, irn, n_ia32_binary_right));
873 set_irn_n(irn, n_ia32_mem, spill);
875 /* immediates are only allowed on the right side */
876 if (i == n_ia32_binary_left && is_ia32_Immediate(get_irn_n(irn, n_ia32_binary_left))) {
877 ia32_swap_left_right(irn);
881 static const be_abi_callbacks_t ia32_abi_callbacks = {
884 ia32_abi_get_between_type,
885 ia32_abi_dont_save_regs,
890 /* fill register allocator interface */
892 static const arch_irn_ops_if_t ia32_irn_ops_if = {
893 ia32_get_irn_reg_req,
898 ia32_get_frame_entity,
899 ia32_set_frame_entity,
900 ia32_set_frame_offset,
903 ia32_get_op_estimated_cost,
904 ia32_possible_memory_operand,
905 ia32_perform_memory_operand,
908 ia32_irn_ops_t ia32_irn_ops = {
915 /**************************************************
918 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
919 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
920 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
921 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
924 **************************************************/
926 static void ia32_before_abi(void *self) {
927 ia32_code_gen_t *cg = self;
929 ir_lower_mode_b(cg->irg, mode_Iu, 0);
931 be_dump(cg->irg, "-lower_modeb", dump_ir_block_graph_sched);
935 * Transforms the standard firm graph into
938 static void ia32_prepare_graph(void *self) {
939 ia32_code_gen_t *cg = self;
941 /* do local optimisations */
942 optimize_graph_df(cg->irg);
944 /* TODO: we often have dead code reachable through out-edges here. So for
945 * now we rebuild edges (as we need correct user count for code selection)
948 edges_deactivate(cg->irg);
949 edges_activate(cg->irg);
953 be_dump(cg->irg, "-pre_transform", dump_ir_block_graph_sched);
955 /* transform nodes into assembler instructions */
956 ia32_transform_graph(cg);
958 /* do local optimisations (mainly CSE) */
959 optimize_graph_df(cg->irg);
962 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
964 /* optimize address mode */
965 ia32_optimize_graph(cg);
968 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
970 /* do code placement, to optimize the position of constants */
974 be_dump(cg->irg, "-place", dump_ir_block_graph_sched);
978 * Dummy functions for hooks we don't need but which must be filled.
980 static void ia32_before_sched(void *self) {
984 static void turn_back_am(ir_node *node)
986 ir_graph *irg = current_ir_graph;
987 dbg_info *dbgi = get_irn_dbg_info(node);
988 ir_node *block = get_nodes_block(node);
989 ir_node *base = get_irn_n(node, n_ia32_base);
990 ir_node *index = get_irn_n(node, n_ia32_index);
991 ir_node *mem = get_irn_n(node, n_ia32_mem);
992 ir_node *noreg = ia32_new_NoReg_gp(ia32_current_cg);
996 const ir_edge_t *edge;
998 ir_fprintf(stderr, "truning back AM in %+F\n", node);
1000 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1001 load_res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1003 ia32_copy_am_attrs(load, node);
1004 set_irn_n(node, n_ia32_mem, new_NoMem());
1006 if(get_ia32_am_arity(node) == ia32_am_unary) {
1007 set_irn_n(node, n_ia32_unary_op, load_res);
1008 } else if(get_ia32_am_arity(node) == ia32_am_binary) {
1009 if(is_ia32_Immediate(get_irn_n(node, n_ia32_Cmp_right))) {
1010 assert(is_ia32_Cmp(node) || is_ia32_Cmp8Bit(node)
1011 || is_ia32_Test(node) || is_ia32_Test8Bit(node));
1012 set_irn_n(node, n_ia32_binary_left, load_res);
1014 set_irn_n(node, n_ia32_binary_right, load_res);
1016 } else if(get_ia32_am_arity(node) == ia32_am_ternary) {
1017 set_irn_n(node, n_ia32_binary_right, load_res);
1019 set_irn_n(node, n_ia32_base, noreg);
1020 set_irn_n(node, n_ia32_index, noreg);
1021 set_ia32_am_offs_int(node, 0);
1022 set_ia32_am_sc(node, NULL);
1023 set_ia32_am_scale(node, 0);
1024 clear_ia32_am_sc_sign(node);
1026 /* rewire mem-proj */
1027 if(get_irn_mode(node) == mode_T) {
1029 foreach_out_edge(node, edge) {
1030 ir_node *out = get_edge_src_irn(edge);
1031 if(get_Proj_proj(out) == pn_ia32_mem) {
1037 if(mem_proj != NULL) {
1038 set_Proj_pred(mem_proj, load);
1039 set_Proj_proj(mem_proj, pn_ia32_Load_M);
1043 set_ia32_op_type(node, ia32_Normal);
1044 if(sched_is_scheduled(node))
1045 sched_add_before(node, load);
1048 static ir_node *flags_remat(ir_node *node, ir_node *after)
1050 /* we should turn back source address mode when rematerializing nodes */
1051 ia32_op_type_t type = get_ia32_op_type(node);
1055 if(is_Block(after)) {
1058 block = get_nodes_block(after);
1061 if (type == ia32_AddrModeS) {
1063 } else if (type == ia32_AddrModeD) {
1064 /* TODO implement this later... */
1065 panic("found DestAM with flag user %+F this should not happen", node);
1067 assert(type == ia32_Normal);
1070 copy = exact_copy(node);
1071 ir_fprintf(stderr, "Remated: %+F\n", copy);
1072 set_nodes_block(copy, block);
1073 sched_add_after(after, copy);
1079 * Called before the register allocator.
1080 * Calculate a block schedule here. We need it for the x87
1081 * simulator and the emitter.
1083 static void ia32_before_ra(void *self) {
1084 ia32_code_gen_t *cg = self;
1086 /* setup fpu rounding modes */
1087 ia32_setup_fpu_mode(cg);
1090 be_sched_fix_flags(cg->birg, &ia32_reg_classes[CLASS_ia32_flags],
1093 ia32_add_missing_keeps(cg);
1098 * Transforms a be_Reload into a ia32 Load.
1100 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1101 ir_graph *irg = get_irn_irg(node);
1102 dbg_info *dbg = get_irn_dbg_info(node);
1103 ir_node *block = get_nodes_block(node);
1104 ir_entity *ent = be_get_frame_entity(node);
1105 ir_mode *mode = get_irn_mode(node);
1106 ir_mode *spillmode = get_spill_mode(node);
1107 ir_node *noreg = ia32_new_NoReg_gp(cg);
1108 ir_node *sched_point = NULL;
1109 ir_node *ptr = get_irg_frame(irg);
1110 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1111 ir_node *new_op, *proj;
1112 const arch_register_t *reg;
1114 if (sched_is_scheduled(node)) {
1115 sched_point = sched_prev(node);
1118 if (mode_is_float(spillmode)) {
1120 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem, spillmode);
1122 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem, spillmode);
1124 else if (get_mode_size_bits(spillmode) == 128) {
1125 // Reload 128 bit sse registers
1126 new_op = new_rd_ia32_xxLoad(dbg, irg, block, ptr, noreg, mem);
1129 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1131 set_ia32_op_type(new_op, ia32_AddrModeS);
1132 set_ia32_ls_mode(new_op, spillmode);
1133 set_ia32_frame_ent(new_op, ent);
1134 set_ia32_use_frame(new_op);
1136 DBG_OPT_RELOAD2LD(node, new_op);
1138 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1141 sched_add_after(sched_point, new_op);
1145 /* copy the register from the old node to the new Load */
1146 reg = arch_get_irn_register(cg->arch_env, node);
1147 arch_set_irn_register(cg->arch_env, new_op, reg);
1149 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1151 exchange(node, proj);
1155 * Transforms a be_Spill node into a ia32 Store.
1157 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1158 ir_graph *irg = get_irn_irg(node);
1159 dbg_info *dbg = get_irn_dbg_info(node);
1160 ir_node *block = get_nodes_block(node);
1161 ir_entity *ent = be_get_frame_entity(node);
1162 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1163 ir_mode *mode = get_spill_mode(spillval);
1164 ir_node *noreg = ia32_new_NoReg_gp(cg);
1165 ir_node *nomem = new_rd_NoMem(irg);
1166 ir_node *ptr = get_irg_frame(irg);
1167 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1169 ir_node *sched_point = NULL;
1171 if (sched_is_scheduled(node)) {
1172 sched_point = sched_prev(node);
1175 /* No need to spill unknown values... */
1176 if(is_ia32_Unknown_GP(val) ||
1177 is_ia32_Unknown_VFP(val) ||
1178 is_ia32_Unknown_XMM(val)) {
1183 exchange(node, store);
1187 if (mode_is_float(mode)) {
1189 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, nomem, val);
1191 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, nomem, val, mode);
1192 } else if (get_mode_size_bits(mode) == 128) {
1193 // Spill 128 bit SSE registers
1194 store = new_rd_ia32_xxStore(dbg, irg, block, ptr, noreg, nomem, val);
1195 } else if (get_mode_size_bits(mode) == 8) {
1196 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, nomem, val);
1198 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, nomem, val);
1201 set_ia32_op_type(store, ia32_AddrModeD);
1202 set_ia32_ls_mode(store, mode);
1203 set_ia32_frame_ent(store, ent);
1204 set_ia32_use_frame(store);
1205 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1206 DBG_OPT_SPILL2ST(node, store);
1209 sched_add_after(sched_point, store);
1213 exchange(node, store);
1216 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1217 ir_graph *irg = get_irn_irg(node);
1218 dbg_info *dbg = get_irn_dbg_info(node);
1219 ir_node *block = get_nodes_block(node);
1220 ir_node *noreg = ia32_new_NoReg_gp(cg);
1221 ir_node *frame = get_irg_frame(irg);
1223 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, mem, noreg, sp);
1225 set_ia32_frame_ent(push, ent);
1226 set_ia32_use_frame(push);
1227 set_ia32_op_type(push, ia32_AddrModeS);
1228 set_ia32_ls_mode(push, mode_Is);
1230 sched_add_before(schedpoint, push);
1234 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1235 ir_graph *irg = get_irn_irg(node);
1236 dbg_info *dbg = get_irn_dbg_info(node);
1237 ir_node *block = get_nodes_block(node);
1238 ir_node *noreg = ia32_new_NoReg_gp(cg);
1239 ir_node *frame = get_irg_frame(irg);
1241 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, new_NoMem(), sp);
1243 set_ia32_frame_ent(pop, ent);
1244 set_ia32_use_frame(pop);
1245 set_ia32_op_type(pop, ia32_AddrModeD);
1246 set_ia32_ls_mode(pop, mode_Is);
1248 sched_add_before(schedpoint, pop);
1253 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos) {
1254 ir_graph *irg = get_irn_irg(node);
1255 dbg_info *dbg = get_irn_dbg_info(node);
1256 ir_node *block = get_nodes_block(node);
1257 ir_mode *spmode = mode_Iu;
1258 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1261 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1262 arch_set_irn_register(cg->arch_env, sp, spreg);
1268 * Transform memperm, currently we do this the ugly way and produce
1269 * push/pop into/from memory cascades. This is possible without using
1272 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1273 ir_graph *irg = get_irn_irg(node);
1274 ir_node *block = get_nodes_block(node);
1278 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1279 const ir_edge_t *edge;
1280 const ir_edge_t *next;
1283 arity = be_get_MemPerm_entity_arity(node);
1284 pops = alloca(arity * sizeof(pops[0]));
1287 for(i = 0; i < arity; ++i) {
1288 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1289 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1290 ir_type *enttype = get_entity_type(inent);
1291 int entbits = get_type_size_bits(enttype);
1292 int entbits2 = get_type_size_bits(get_entity_type(outent));
1293 ir_node *mem = get_irn_n(node, i + 1);
1296 /* work around cases where entities have different sizes */
1297 if(entbits2 < entbits)
1299 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1301 push = create_push(cg, node, node, sp, mem, inent);
1302 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1304 // add another push after the first one
1305 push = create_push(cg, node, node, sp, mem, inent);
1306 add_ia32_am_offs_int(push, 4);
1307 sp = create_spproj(cg, node, push, pn_ia32_Push_stack);
1310 set_irn_n(node, i, new_Bad());
1314 for(i = arity - 1; i >= 0; --i) {
1315 ir_entity *inent = be_get_MemPerm_in_entity(node, i);
1316 ir_entity *outent = be_get_MemPerm_out_entity(node, i);
1317 ir_type *enttype = get_entity_type(outent);
1318 int entbits = get_type_size_bits(enttype);
1319 int entbits2 = get_type_size_bits(get_entity_type(inent));
1322 /* work around cases where entities have different sizes */
1323 if(entbits2 < entbits)
1325 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1327 pop = create_pop(cg, node, node, sp, outent);
1328 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1330 add_ia32_am_offs_int(pop, 4);
1332 // add another pop after the first one
1333 pop = create_pop(cg, node, node, sp, outent);
1334 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack);
1341 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1342 sched_add_before(node, keep);
1344 // exchange memprojs
1345 foreach_out_edge_safe(node, edge, next) {
1346 ir_node *proj = get_edge_src_irn(edge);
1347 int p = get_Proj_proj(proj);
1351 set_Proj_pred(proj, pops[p]);
1352 set_Proj_proj(proj, pn_ia32_Pop_M);
1356 arity = get_irn_arity(node);
1357 for(i = 0; i < arity; ++i) {
1358 set_irn_n(node, i, new_Bad());
1364 * Block-Walker: Calls the transform functions Spill and Reload.
1366 static void ia32_after_ra_walker(ir_node *block, void *env) {
1367 ir_node *node, *prev;
1368 ia32_code_gen_t *cg = env;
1370 /* beware: the schedule is changed here */
1371 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1372 prev = sched_prev(node);
1374 if (be_is_Reload(node)) {
1375 transform_to_Load(cg, node);
1376 } else if (be_is_Spill(node)) {
1377 transform_to_Store(cg, node);
1378 } else if(be_is_MemPerm(node)) {
1379 transform_MemPerm(cg, node);
1385 * Collects nodes that need frame entities assigned.
1387 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1389 be_fec_env_t *env = data;
1391 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1392 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1393 int align = get_mode_size_bytes(mode);
1394 be_node_needs_frame_entity(env, node, mode, align);
1395 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1396 && is_ia32_use_frame(node)) {
1397 if (is_ia32_need_stackent(node) || is_ia32_Load(node)) {
1398 const ir_mode *mode = get_ia32_ls_mode(node);
1399 const ia32_attr_t *attr = get_ia32_attr_const(node);
1400 int align = get_mode_size_bytes(mode);
1402 if(attr->data.need_64bit_stackent) {
1405 if(attr->data.need_32bit_stackent) {
1408 be_node_needs_frame_entity(env, node, mode, align);
1409 } else if (is_ia32_vfild(node) || is_ia32_xLoad(node)
1410 || is_ia32_vfld(node)) {
1411 const ir_mode *mode = get_ia32_ls_mode(node);
1413 be_node_needs_frame_entity(env, node, mode, align);
1414 } else if(is_ia32_FldCW(node)) {
1415 const ir_mode *mode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
1417 be_node_needs_frame_entity(env, node, mode, align);
1420 assert(is_ia32_St(node) ||
1421 is_ia32_xStoreSimple(node) ||
1422 is_ia32_vfst(node) ||
1423 is_ia32_vfist(node) ||
1424 is_ia32_FnstCW(node));
1431 * We transform Spill and Reload here. This needs to be done before
1432 * stack biasing otherwise we would miss the corrected offset for these nodes.
1434 static void ia32_after_ra(void *self) {
1435 ia32_code_gen_t *cg = self;
1436 ir_graph *irg = cg->irg;
1437 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1439 /* create and coalesce frame entities */
1440 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1441 be_assign_entities(fec_env);
1442 be_free_frame_entity_coalescer(fec_env);
1444 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1448 * Last touchups for the graph before emit: x87 simulation to replace the
1449 * virtual with real x87 instructions, creating a block schedule and peephole
1452 static void ia32_finish(void *self) {
1453 ia32_code_gen_t *cg = self;
1454 ir_graph *irg = cg->irg;
1456 ia32_finish_irg(irg, cg);
1458 /* we might have to rewrite x87 virtual registers */
1459 if (cg->do_x87_sim) {
1460 x87_simulate_graph(cg->arch_env, cg->birg);
1463 /* create block schedule, this also removes empty blocks which might
1464 * produce critical edges */
1465 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1467 /* do peephole optimisations */
1468 ia32_peephole_optimization(irg, cg);
1472 * Emits the code, closes the output file and frees
1473 * the code generator interface.
1475 static void ia32_codegen(void *self) {
1476 ia32_code_gen_t *cg = self;
1477 ir_graph *irg = cg->irg;
1479 ia32_gen_routine(cg, irg);
1483 /* remove it from the isa */
1486 assert(ia32_current_cg == cg);
1487 ia32_current_cg = NULL;
1489 /* de-allocate code generator */
1490 del_set(cg->reg_set);
1494 static void *ia32_cg_init(be_irg_t *birg);
1496 static const arch_code_generator_if_t ia32_code_gen_if = {
1498 ia32_before_abi, /* before abi introduce hook */
1501 ia32_before_sched, /* before scheduling hook */
1502 ia32_before_ra, /* before register allocation hook */
1503 ia32_after_ra, /* after register allocation hook */
1504 ia32_finish, /* called before codegen */
1505 ia32_codegen /* emit && done */
1509 * Initializes a IA32 code generator.
1511 static void *ia32_cg_init(be_irg_t *birg) {
1512 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1513 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1515 cg->impl = &ia32_code_gen_if;
1516 cg->irg = birg->irg;
1517 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1518 cg->arch_env = birg->main_env->arch_env;
1521 cg->blk_sched = NULL;
1522 cg->fp_kind = isa->fp_kind;
1523 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1525 /* copy optimizations from isa for easier access */
1527 cg->arch = isa->arch;
1528 cg->opt_arch = isa->opt_arch;
1534 if (isa->name_obst) {
1535 obstack_free(isa->name_obst, NULL);
1536 obstack_init(isa->name_obst);
1540 cur_reg_set = cg->reg_set;
1542 ia32_irn_ops.cg = cg;
1544 assert(ia32_current_cg == NULL);
1545 ia32_current_cg = cg;
1547 return (arch_code_generator_t *)cg;
1552 /*****************************************************************
1553 * ____ _ _ _____ _____
1554 * | _ \ | | | | |_ _|/ ____| /\
1555 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1556 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1557 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1558 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1560 *****************************************************************/
1563 * Set output modes for GCC
1565 static const tarval_mode_info mo_integer = {
1572 * set the tarval output mode of all integer modes to decimal
1574 static void set_tarval_output_modes(void)
1578 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1579 ir_mode *mode = get_irp_mode(i);
1581 if (mode_is_int(mode))
1582 set_tarval_mode_output_option(mode, &mo_integer);
1586 const arch_isa_if_t ia32_isa_if;
1589 * The template that generates a new ISA object.
1590 * Note that this template can be changed by command line
1593 static ia32_isa_t ia32_isa_template = {
1595 &ia32_isa_if, /* isa interface implementation */
1596 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1597 &ia32_gp_regs[REG_EBP], /* base pointer register */
1598 -1, /* stack direction */
1599 NULL, /* main environment */
1600 7, /* costs for a spill instruction */
1601 5, /* costs for a reload instruction */
1603 NULL_EMITTER, /* emitter environment */
1604 NULL, /* 16bit register names */
1605 NULL, /* 8bit register names */
1606 NULL, /* 8bit register names high */
1610 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1611 IA32_OPT_DOAM | /* optimize address mode default: on */
1612 IA32_OPT_LEA | /* optimize for LEAs default: on */
1613 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1614 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1615 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1616 arch_pentium_4, /* instruction architecture */
1617 arch_pentium_4, /* optimize for architecture */
1618 fp_x87, /* floating point mode */
1619 NULL, /* current code generator */
1621 NULL, /* name obstack */
1622 0 /* name obst size */
1626 static void set_arch_costs(enum cpu_support arch);
1629 * Initializes the backend ISA.
1631 static void *ia32_init(FILE *file_handle) {
1632 static int inited = 0;
1639 set_tarval_output_modes();
1641 isa = xmalloc(sizeof(*isa));
1642 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1644 if(mode_fpcw == NULL) {
1645 mode_fpcw = new_ir_mode("Fpcw", irms_int_number, 16, 0, irma_none, 0);
1648 ia32_register_init();
1649 ia32_create_opcodes();
1651 set_arch_costs(isa->opt_arch);
1653 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1654 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1655 /* no SSE2 for these cpu's */
1656 isa->fp_kind = fp_x87;
1658 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1659 /* Pentium 4 don't like inc and dec instructions */
1660 isa->opt &= ~IA32_OPT_INCDEC;
1663 be_emit_init_env(&isa->emit, file_handle);
1664 isa->regs_16bit = pmap_create();
1665 isa->regs_8bit = pmap_create();
1666 isa->regs_8bit_high = pmap_create();
1667 isa->types = pmap_create();
1668 isa->tv_ent = pmap_create();
1669 isa->cpu = ia32_init_machine_description();
1671 ia32_build_16bit_reg_map(isa->regs_16bit);
1672 ia32_build_8bit_reg_map(isa->regs_8bit);
1673 ia32_build_8bit_reg_map_high(isa->regs_8bit_high);
1676 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1677 obstack_init(isa->name_obst);
1680 /* enter the ISA object into the intrinsic environment */
1681 intrinsic_env.isa = isa;
1682 ia32_handle_intrinsics();
1684 /* needed for the debug support */
1685 be_gas_emit_switch_section(&isa->emit, GAS_SECTION_TEXT);
1686 be_emit_cstring(&isa->emit, ".Ltext0:\n");
1687 be_emit_write_line(&isa->emit);
1689 /* we mark referenced global entities, so we can only emit those which
1690 * are actually referenced. (Note: you mustn't use the type visited flag
1691 * elsewhere in the backend)
1693 inc_master_type_visited();
1701 * Closes the output file and frees the ISA structure.
1703 static void ia32_done(void *self) {
1704 ia32_isa_t *isa = self;
1706 /* emit now all global declarations */
1707 be_gas_emit_decls(&isa->emit, isa->arch_isa.main_env, 1);
1709 pmap_destroy(isa->regs_16bit);
1710 pmap_destroy(isa->regs_8bit);
1711 pmap_destroy(isa->regs_8bit_high);
1712 pmap_destroy(isa->tv_ent);
1713 pmap_destroy(isa->types);
1716 obstack_free(isa->name_obst, NULL);
1719 be_emit_destroy_env(&isa->emit);
1726 * Return the number of register classes for this architecture.
1727 * We report always these:
1728 * - the general purpose registers
1729 * - the SSE floating point register set
1730 * - the virtual floating point registers
1731 * - the SSE vector register set
1733 static int ia32_get_n_reg_class(const void *self) {
1739 * Return the register class for index i.
1741 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i)
1744 assert(i >= 0 && i < N_CLASSES);
1745 return &ia32_reg_classes[i];
1749 * Get the register class which shall be used to store a value of a given mode.
1750 * @param self The this pointer.
1751 * @param mode The mode in question.
1752 * @return A register class which can hold values of the given mode.
1754 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1755 const ia32_isa_t *isa = self;
1756 if (mode_is_float(mode)) {
1757 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1760 return &ia32_reg_classes[CLASS_ia32_gp];
1764 * Get the ABI restrictions for procedure calls.
1765 * @param self The this pointer.
1766 * @param method_type The type of the method (procedure) in question.
1767 * @param abi The abi object to be modified
1769 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1770 const ia32_isa_t *isa = self;
1775 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1777 /* set abi flags for calls */
1778 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1779 call_flags.bits.store_args_sequential = 0;
1780 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1781 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1782 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1784 /* set parameter passing style */
1785 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1787 if (get_method_variadicity(method_type) == variadicity_variadic) {
1788 /* pass all parameters of a variadic function on the stack */
1791 cc = get_method_calling_convention(method_type);
1792 if (get_method_additional_properties(method_type) & mtp_property_private) {
1793 /* set the calling conventions to register parameter */
1794 cc = (cc & ~cc_bits) | cc_reg_param;
1797 n = get_method_n_params(method_type);
1798 for (i = regnum = 0; i < n; i++) {
1799 const ir_mode *mode;
1800 const arch_register_t *reg = NULL;
1802 tp = get_method_param_type(method_type, i);
1803 mode = get_type_mode(tp);
1805 reg = ia32_get_RegParam_reg(isa->cg, cc, regnum, mode);
1808 be_abi_call_param_reg(abi, i, reg);
1811 be_abi_call_param_stack(abi, i, 4, 0, 0);
1815 /* set return registers */
1816 n = get_method_n_ress(method_type);
1818 assert(n <= 2 && "more than two results not supported");
1820 /* In case of 64bit returns, we will have two 32bit values */
1822 tp = get_method_res_type(method_type, 0);
1823 mode = get_type_mode(tp);
1825 assert(!mode_is_float(mode) && "two FP results not supported");
1827 tp = get_method_res_type(method_type, 1);
1828 mode = get_type_mode(tp);
1830 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1832 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1833 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1836 const arch_register_t *reg;
1838 tp = get_method_res_type(method_type, 0);
1839 assert(is_atomic_type(tp));
1840 mode = get_type_mode(tp);
1842 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1844 be_abi_call_res_reg(abi, 0, reg);
1849 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self,
1854 return &ia32_irn_ops;
1857 const arch_irn_handler_t ia32_irn_handler = {
1861 const arch_irn_handler_t *ia32_get_irn_handler(const void *self)
1864 return &ia32_irn_handler;
1867 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn)
1871 if(!is_ia32_irn(irn)) {
1875 if(is_ia32_NoReg_GP(irn) || is_ia32_NoReg_VFP(irn) || is_ia32_NoReg_XMM(irn)
1876 || is_ia32_Unknown_GP(irn) || is_ia32_Unknown_XMM(irn)
1877 || is_ia32_Unknown_VFP(irn) || is_ia32_ChangeCW(irn)
1878 || is_ia32_Immediate(irn))
1885 * Initializes the code generator interface.
1887 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self)
1890 return &ia32_code_gen_if;
1894 * Returns the estimated execution time of an ia32 irn.
1896 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1897 const arch_env_t *arch_env = env;
1898 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1901 list_sched_selector_t ia32_sched_selector;
1904 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1906 static const list_sched_selector_t *ia32_get_list_sched_selector(
1907 const void *self, list_sched_selector_t *selector)
1910 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1911 ia32_sched_selector.exectime = ia32_sched_exectime;
1912 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1913 return &ia32_sched_selector;
1916 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self)
1923 * Returns the necessary byte alignment for storing a register of given class.
1925 static int ia32_get_reg_class_alignment(const void *self,
1926 const arch_register_class_t *cls)
1928 ir_mode *mode = arch_register_class_mode(cls);
1929 int bytes = get_mode_size_bytes(mode);
1932 if (mode_is_float(mode) && bytes > 8)
1937 static const be_execution_unit_t ***ia32_get_allowed_execution_units(
1938 const void *self, const ir_node *irn)
1940 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1941 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1942 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1945 static const be_execution_unit_t *_allowed_units_GP[] = {
1946 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1947 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1948 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1949 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1950 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1951 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1952 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1955 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1956 &be_machine_execution_units_DUMMY[0],
1959 static const be_execution_unit_t **_units_callret[] = {
1960 _allowed_units_BRANCH,
1963 static const be_execution_unit_t **_units_other[] = {
1967 static const be_execution_unit_t **_units_dummy[] = {
1968 _allowed_units_DUMMY,
1971 const be_execution_unit_t ***ret;
1974 if (is_ia32_irn(irn)) {
1975 ret = get_ia32_exec_units(irn);
1977 else if (is_be_node(irn)) {
1978 if (be_is_Call(irn) || be_is_Return(irn)) {
1979 ret = _units_callret;
1981 else if (be_is_Barrier(irn)) {
1996 * Return the abstract ia32 machine.
1998 static const be_machine_t *ia32_get_machine(const void *self) {
1999 const ia32_isa_t *isa = self;
2004 * Return irp irgs in the desired order.
2006 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list)
2014 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
2015 * @return 1 if allowed, 0 otherwise
2017 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
2027 ir_node *pred = get_Proj_pred(sel);
2029 ir_node *left = get_Cmp_left(pred);
2030 ir_mode *cmp_mode = get_irn_mode(left);
2031 if(mode_is_float(cmp_mode))
2037 /* check the Phi nodes */
2038 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
2039 ir_mode *mode = get_irn_mode(phi);
2041 if (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
2048 typedef struct insn_const {
2049 int add_cost; /**< cost of an add instruction */
2050 int lea_cost; /**< cost of a lea instruction */
2051 int const_shf_cost; /**< cost of a constant shift instruction */
2052 int cost_mul_start; /**< starting cost of a multiply instruction */
2053 int cost_mul_bit; /**< cost of multiply for every set bit */
2056 /* costs for the i386 */
2057 static const insn_const i386_cost = {
2058 1, /* cost of an add instruction */
2059 1, /* cost of a lea instruction */
2060 2, /* cost of a constant shift instruction */
2061 6, /* starting cost of a multiply instruction */
2062 1 /* cost of multiply for every set bit */
2065 /* costs for the i486 */
2066 static const insn_const i486_cost = {
2067 1, /* cost of an add instruction */
2068 1, /* cost of a lea instruction */
2069 2, /* cost of a constant shift instruction */
2070 12, /* starting cost of a multiply instruction */
2071 1 /* cost of multiply for every set bit */
2074 /* costs for the Pentium */
2075 static const insn_const pentium_cost = {
2076 1, /* cost of an add instruction */
2077 1, /* cost of a lea instruction */
2078 1, /* cost of a constant shift instruction */
2079 11, /* starting cost of a multiply instruction */
2080 0 /* cost of multiply for every set bit */
2083 /* costs for the Pentium Pro */
2084 static const insn_const pentiumpro_cost = {
2085 1, /* cost of an add instruction */
2086 1, /* cost of a lea instruction */
2087 1, /* cost of a constant shift instruction */
2088 4, /* starting cost of a multiply instruction */
2089 0 /* cost of multiply for every set bit */
2092 /* costs for the K6 */
2093 static const insn_const k6_cost = {
2094 1, /* cost of an add instruction */
2095 2, /* cost of a lea instruction */
2096 1, /* cost of a constant shift instruction */
2097 3, /* starting cost of a multiply instruction */
2098 0 /* cost of multiply for every set bit */
2101 /* costs for the Athlon */
2102 static const insn_const athlon_cost = {
2103 1, /* cost of an add instruction */
2104 2, /* cost of a lea instruction */
2105 1, /* cost of a constant shift instruction */
2106 5, /* starting cost of a multiply instruction */
2107 0 /* cost of multiply for every set bit */
2110 /* costs for the Pentium 4 */
2111 static const insn_const pentium4_cost = {
2112 1, /* cost of an add instruction */
2113 3, /* cost of a lea instruction */
2114 4, /* cost of a constant shift instruction */
2115 15, /* starting cost of a multiply instruction */
2116 0 /* cost of multiply for every set bit */
2119 /* costs for the Core */
2120 static const insn_const core_cost = {
2121 1, /* cost of an add instruction */
2122 1, /* cost of a lea instruction */
2123 1, /* cost of a constant shift instruction */
2124 10, /* starting cost of a multiply instruction */
2125 0 /* cost of multiply for every set bit */
2128 /* costs for the generic */
2129 static const insn_const generic_cost = {
2130 1, /* cost of an add instruction */
2131 2, /* cost of a lea instruction */
2132 1, /* cost of a constant shift instruction */
2133 4, /* starting cost of a multiply instruction */
2134 0 /* cost of multiply for every set bit */
2137 static const insn_const *arch_costs = &generic_cost;
2139 static void set_arch_costs(enum cpu_support arch) {
2142 arch_costs = &i386_cost;
2145 arch_costs = &i486_cost;
2148 case arch_pentium_mmx:
2149 arch_costs = &pentium_cost;
2151 case arch_pentium_pro:
2152 case arch_pentium_2:
2153 case arch_pentium_3:
2154 arch_costs = &pentiumpro_cost;
2156 case arch_pentium_4:
2157 arch_costs = &pentium4_cost;
2159 case arch_pentium_m:
2160 arch_costs = &pentiumpro_cost;
2163 arch_costs = &core_cost;
2166 arch_costs = &k6_cost;
2169 case arch_athlon_64:
2171 arch_costs = &athlon_cost;
2175 arch_costs = &generic_cost;
2180 * Evaluate a given simple instruction.
2182 static int ia32_evaluate_insn(insn_kind kind, tarval *tv) {
2187 cost = arch_costs->cost_mul_start;
2188 if (arch_costs->cost_mul_bit > 0) {
2189 char *bitstr = get_tarval_bitpattern(tv);
2192 for (i = 0; bitstr[i] != '\0'; ++i) {
2193 if (bitstr[i] == '1') {
2194 cost += arch_costs->cost_mul_bit;
2201 return arch_costs->lea_cost;
2204 return arch_costs->add_cost;
2206 return arch_costs->const_shf_cost;
2208 return arch_costs->add_cost;
2215 * Returns the libFirm configuration parameter for this backend.
2217 static const backend_params *ia32_get_libfirm_params(void) {
2218 static const ir_settings_if_conv_t ifconv = {
2219 4, /* maxdepth, doesn't matter for Psi-conversion */
2220 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
2222 static const ir_settings_arch_dep_t ad = {
2223 1, /* also use subs */
2224 4, /* maximum shifts */
2225 31, /* maximum shift amount */
2226 ia32_evaluate_insn, /* evaluate the instruction sequence */
2228 1, /* allow Mulhs */
2229 1, /* allow Mulus */
2230 32 /* Mulh allowed up to 32 bit */
2232 static backend_params p = {
2233 1, /* need dword lowering */
2234 1, /* support inline assembly */
2235 NULL, /* no additional opcodes */
2236 NULL, /* will be set later */
2237 ia32_create_intrinsic_fkt,
2238 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
2239 NULL, /* will be set below */
2243 p.if_conv_info = &ifconv;
2247 /* instruction set architectures. */
2248 static const lc_opt_enum_int_items_t arch_items[] = {
2249 { "386", arch_i386, },
2250 { "486", arch_i486, },
2251 { "pentium", arch_pentium, },
2252 { "586", arch_pentium, },
2253 { "pentiumpro", arch_pentium_pro, },
2254 { "686", arch_pentium_pro, },
2255 { "pentiummmx", arch_pentium_mmx, },
2256 { "pentium2", arch_pentium_2, },
2257 { "p2", arch_pentium_2, },
2258 { "pentium3", arch_pentium_3, },
2259 { "p3", arch_pentium_3, },
2260 { "pentium4", arch_pentium_4, },
2261 { "p4", arch_pentium_4, },
2262 { "pentiumm", arch_pentium_m, },
2263 { "pm", arch_pentium_m, },
2264 { "core", arch_core, },
2266 { "athlon", arch_athlon, },
2267 { "athlon64", arch_athlon_64, },
2268 { "opteron", arch_opteron, },
2269 { "generic", arch_generic, },
2273 static lc_opt_enum_int_var_t arch_var = {
2274 &ia32_isa_template.arch, arch_items
2277 static lc_opt_enum_int_var_t opt_arch_var = {
2278 &ia32_isa_template.opt_arch, arch_items
2281 static const lc_opt_enum_int_items_t fp_unit_items[] = {
2283 { "sse2", fp_sse2 },
2287 static lc_opt_enum_int_var_t fp_unit_var = {
2288 &ia32_isa_template.fp_kind, fp_unit_items
2291 static const lc_opt_enum_int_items_t gas_items[] = {
2292 { "normal", GAS_FLAVOUR_NORMAL },
2293 { "mingw", GAS_FLAVOUR_MINGW },
2297 static lc_opt_enum_int_var_t gas_var = {
2298 (int*) &be_gas_flavour, gas_items
2301 static const lc_opt_table_entry_t ia32_options[] = {
2302 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
2303 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
2304 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
2305 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
2306 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
2307 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
2308 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
2309 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
2310 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2314 const arch_isa_if_t ia32_isa_if = {
2317 ia32_get_n_reg_class,
2319 ia32_get_reg_class_for_mode,
2321 ia32_get_irn_handler,
2322 ia32_get_code_generator_if,
2323 ia32_get_list_sched_selector,
2324 ia32_get_ilp_sched_selector,
2325 ia32_get_reg_class_alignment,
2326 ia32_get_libfirm_params,
2327 ia32_get_allowed_execution_units,
2332 void ia32_init_emitter(void);
2333 void ia32_init_finish(void);
2334 void ia32_init_optimize(void);
2335 void ia32_init_transform(void);
2336 void ia32_init_x87(void);
2338 void be_init_arch_ia32(void)
2340 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2341 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2343 lc_opt_add_table(ia32_grp, ia32_options);
2344 be_register_isa_if("ia32", &ia32_isa_if);
2346 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.cg");
2348 ia32_init_emitter();
2350 ia32_init_optimize();
2351 ia32_init_transform();
2355 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);