11 #include "pseudo_irg.h"
15 #include "iredges_t.h"
22 #include "../bearch.h" /* the general register allocator interface */
23 #include "../benode_t.h"
24 #include "../belower.h"
25 #include "../besched_t.h"
26 #include "bearch_ia32_t.h"
28 #include "ia32_new_nodes.h" /* ia32 nodes interface */
29 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
30 #include "ia32_gen_decls.h" /* interface declaration emitter */
31 #include "ia32_transform.h"
32 #include "ia32_emitter.h"
33 #include "ia32_map_regs.h"
34 #include "ia32_optimize.h"
36 #define DEBUG_MODULE "firm.be.ia32.isa"
39 static set *cur_reg_set = NULL;
42 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
44 extern ir_node *be_new_NoReg(ir_graph *irg);
46 /**************************************************
49 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
50 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
51 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
52 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
55 **************************************************/
57 static ir_node *my_skip_proj(const ir_node *n) {
63 static int is_Call_Proj(const ir_node *n) {
65 is_Proj(get_Proj_pred(n)) &&
66 get_irn_mode(get_Proj_pred(n)) == mode_T &&
67 is_ia32_Call(get_Proj_pred(get_Proj_pred(n))))
75 static int is_Start_Proj(const ir_node *n) {
77 is_Proj(get_Proj_pred(n)) &&
78 get_irn_mode(get_Proj_pred(n)) == mode_T &&
79 is_Start(get_Proj_pred(get_Proj_pred(n))))
87 static int is_P_frame_base_Proj(const ir_node *n) {
89 is_Start(get_Proj_pred(n)) &&
90 get_Proj_proj(n) == pn_Start_P_frame_base)
98 static int is_used_by_Keep(const ir_node *n) {
99 return be_is_Keep(get_edge_src_irn(get_irn_out_edge_first(n)));
103 * Return register requirements for an ia32 node.
104 * If the node returns a tuple (mode_T) then the proj's
105 * will be asked for this information.
107 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
108 const ia32_register_req_t *irn_req;
109 long node_pos = pos == -1 ? 0 : pos;
110 ir_mode *mode = get_irn_mode(irn);
111 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
112 const ia32_irn_ops_t *ops = self;
114 if (mode == mode_T || mode == mode_M) {
115 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
119 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
122 if (is_Call_Proj(irn) && is_used_by_Keep(irn)) {
127 irn_req = ia32_projnum_reg_req_map[get_Proj_proj(irn)];
128 memcpy(req, &(irn_req->req), sizeof(*req));
133 else if (is_Start_Proj(irn)) {
134 irn_req = ops->cg->reg_param_req[get_Proj_proj(irn)];
135 assert(irn_req && "missing requirement for regparam");
136 memcpy(req, &(irn_req->req), sizeof(*req));
140 else if (is_Proj(irn)) {
142 node_pos = ia32_translate_proj_pos(irn);
148 irn = my_skip_proj(irn);
150 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
153 if (is_ia32_irn(irn)) {
155 irn_req = get_ia32_in_req(irn, pos);
158 irn_req = get_ia32_out_req(irn, node_pos);
161 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
163 memcpy(req, &(irn_req->req), sizeof(*req));
165 if (arch_register_req_is(&(irn_req->req), should_be_same) ||
166 arch_register_req_is(&(irn_req->req), should_be_different)) {
167 assert(irn_req->pos >= 0 && "should be same/different constraint for in -> out NYI");
168 req->other = get_irn_n(irn, irn_req->pos);
172 /* treat Phi like Const with default requirements */
174 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
175 if (mode_is_float(mode))
176 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
177 else if (mode_is_int(mode) || mode_is_reference(mode))
178 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
179 else if (mode == mode_T || mode == mode_M) {
180 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
184 assert(0 && "unsupported Phi-Mode");
186 else if (is_Start(irn)) {
187 DB((mod, LEVEL_1, "returning reqs none for ProjX -> Start (%+F )\n", irn));
189 case pn_Start_X_initial_exec:
190 case pn_Start_P_value_arg_base:
191 case pn_Start_P_globals:
192 case pn_Start_P_frame_base:
193 memcpy(req, &(ia32_default_req_none.req), sizeof(*req));
195 case pn_Start_T_args:
196 assert(0 && "ProjT(pn_Start_T_args) should not be asked");
199 else if (get_irn_op(irn) == op_Return && pos > 0) {
200 DB((mod, LEVEL_1, "returning reqs EAX for %+F\n", irn));
201 memcpy(req, &(ia32_default_req_ia32_gp_eax.req), sizeof(*req));
204 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
212 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
215 if ((is_Call_Proj(irn) && is_used_by_Keep(irn)) ||
216 is_P_frame_base_Proj(irn) ||
219 /* don't skip the proj, we want to take the else below */
221 else if (is_Proj(irn)) {
222 pos = ia32_translate_proj_pos(irn);
223 irn = my_skip_proj(irn);
226 if (is_ia32_irn(irn)) {
227 const arch_register_t **slots;
229 slots = get_ia32_slots(irn);
233 ia32_set_firm_reg(irn, reg, cur_reg_set);
237 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
239 const arch_register_t *reg = NULL;
241 if ((is_Call_Proj(irn) && is_used_by_Keep(irn)) ||
242 is_P_frame_base_Proj(irn) ||
245 /* don't skip the proj, we want to take the else below */
247 else if (is_Proj(irn)) {
248 pos = ia32_translate_proj_pos(irn);
249 irn = my_skip_proj(irn);
252 if (is_ia32_irn(irn)) {
253 const arch_register_t **slots;
254 slots = get_ia32_slots(irn);
258 reg = ia32_get_firm_reg(irn, cur_reg_set);
264 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
265 irn = my_skip_proj(irn);
267 return arch_irn_class_branch;
268 else if (is_ia32_Call(irn))
269 return arch_irn_class_call;
270 else if (is_ia32_irn(irn))
271 return arch_irn_class_normal;
276 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
277 irn = my_skip_proj(irn);
278 if (is_ia32_irn(irn))
279 return get_ia32_flags(irn);
281 if (is_Start_Proj(irn))
282 return arch_irn_flags_ignore;
288 /* fill register allocator interface */
290 static const arch_irn_ops_if_t ia32_irn_ops_if = {
291 ia32_get_irn_reg_req,
298 ia32_irn_ops_t ia32_irn_ops = {
305 /**************************************************
308 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
309 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
310 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
311 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
314 **************************************************/
316 static void check_for_alloca(ir_node *irn, void *env) {
317 int *has_alloca = env;
319 if (get_irn_op(irn) == op_Alloc) {
320 if (get_Alloc_where(irn) == stack_alloc) {
327 * Transforms the standard firm graph into
330 static void ia32_prepare_graph(void *self) {
331 ia32_code_gen_t *cg = self;
333 if (! is_pseudo_ir_graph(cg->irg)) {
334 /* If there is a alloca in the irg, we use %ebp for stack addressing */
335 /* instead of %esp, as alloca destroys %esp. */
339 /* check for alloca node */
340 irg_walk_blkwise_graph(cg->irg, check_for_alloca, NULL, &(cg->has_alloca));
342 if (cg->has_alloca) {
343 ia32_gp_regs[REG_EBP].type = arch_register_type_ignore;
346 irg_walk_blkwise_graph(cg->irg, ia32_place_consts, ia32_transform_node, cg);
353 * Stack reservation and StackParam lowering.
355 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
357 firm_dbg_module_t *mod = cg->mod;
358 ir_node *frame = get_irg_frame(irg);
359 ir_node *end_block = get_irg_end_block(irg);
360 ir_node **returns, **in, **new_in;
361 ir_node *stack_reserve, *sched_point;
362 ir_node *stack_free, *new_ret, *return_block;
363 int stack_size = 0, i, n_arg;
364 arch_register_t *stack_reg;
365 tarval *stack_size_tv;
368 /* Determine stack register */
369 if (cg->has_alloca) {
370 stack_reg = &ia32_gp_regs[REG_EBP];
373 stack_reg = &ia32_gp_regs[REG_ESP];
376 /* If frame is used, then we need to reserve some stackspace. */
377 if (get_irn_n_edges(frame) > 0) {
378 /* The initial stack reservation. */
379 stack_size = get_type_size_bytes(get_irg_frame_type(irg));
380 frame_dbg = get_irn_dbg_info(frame);
381 stack_reserve = new_rd_ia32_Sub_i(frame_dbg, irg, get_nodes_block(frame), new_NoMem(), mode_Is);
382 stack_size_tv = new_tarval_from_long(stack_size, mode_Is);
383 set_ia32_Immop_tarval(stack_reserve, stack_size_tv);
385 assert(stack_size && "bOrken stack layout");
387 /* reroute all edges from frame pointer to corrected frame pointer */
388 edges_reroute(frame, stack_reserve, irg);
389 set_irn_n(stack_reserve, 0, frame);
391 /* schedule frame pointer */
392 if (! sched_is_scheduled(frame)) {
393 sched_add_after(get_irg_start(irg), frame);
397 arch_set_irn_register(cg->arch_env, frame, stack_reg);
398 arch_set_irn_register(cg->arch_env, stack_reserve, stack_reg);
400 /* insert into schedule */
401 sched_add_after(frame, stack_reserve);
403 /* Free stack for each Return node */
404 returns = get_Block_cfgpred_arr(end_block);
405 for (i = 0; i < get_Block_n_cfgpreds(end_block); i++) {
406 assert(get_irn_opcode(returns[i]) == iro_Return && "cfgpred of endblock is not a return");
408 return_block = get_nodes_block(returns[i]);
411 stack_free = new_rd_ia32_Add_i(frame_dbg, irg, return_block, stack_reserve, mode_Is);
412 set_ia32_Immop_tarval(stack_free, stack_size_tv);
413 arch_set_irn_register(cg->arch_env, stack_free, stack_reg);
415 DBG((mod, LEVEL_1, "examining %+F, %+F created, block %+F", returns[i], stack_free, return_block));
417 /* get the old Return arguments */
418 n_arg = get_Return_n_ress(returns[i]);
419 in = get_Return_res_arr(returns[i]);
420 new_in = alloca((n_arg + 2) * sizeof(new_in[0]));
422 /* copy the old to the new in's */
423 memcpy(new_in, in, n_arg * sizeof(in[0]));
424 new_in[n_arg++] = stack_free;
425 new_in[n_arg++] = get_Return_mem(returns[i]);
427 /* create the new return node */
428 new_ret = new_rd_ia32_Return(get_irn_dbg_info(returns[i]), irg, return_block, n_arg, new_in);
430 /* In case the return node is the only node in the block, */
431 /* it is not scheduled, so we need this work-around. */
432 if (! sched_is_scheduled(returns[i])) {
433 sched_point = return_block;
436 sched_point = sched_prev(returns[i]);
437 sched_remove(returns[i]);
440 /* exchange the old return with the new one */
441 exchange(returns[i], new_ret);
443 DB((mod, LEVEL_1, " ... replaced with %+F\n", new_ret));
445 /* remove the old one from schedule and add the new nodes properly */
446 sched_add_after(sched_point, new_ret);
447 sched_add_after(sched_point, stack_free);
456 * Dummy functions for hooks we don't need but which must be filled.
458 static void ia32_before_sched(void *self) {
459 ia32_code_gen_t *cg = self;
461 lower_nodes_before_sched(cg->irg, cg->arch_env);
464 static void ia32_before_ra(void *self) {
469 * Creates a Store for a Spill
471 static ir_node *ia32_lower_spill(void *self, ir_node *spill) {
472 ia32_code_gen_t *cg = self;
473 dbg_info *dbg = get_irn_dbg_info(spill);
474 ir_node *block = get_nodes_block(spill);
475 ir_node *ptr = get_irg_frame(cg->irg);
476 ir_node *val = be_get_Spill_context(spill);
477 ir_node *mem = new_rd_NoMem(cg->irg);
478 ir_node *noreg = be_new_NoReg(cg->irg);
479 ir_mode *mode = get_irn_mode(spill);
481 entity *ent = be_get_spill_entity(spill);
482 unsigned offs = get_entity_offset_bytes(ent);
485 DB((cg->mod, LEVEL_1, "lower_spill: got offset %d for %+F\n", offs, ent));
487 res = new_rd_ia32_Store(dbg, cg->irg, block, ptr, noreg, val, mem, mode);
488 snprintf(buf, sizeof(buf), "%d", offs);
489 add_ia32_am_offs(res, buf);
495 * Create a Load for a Spill
497 static ir_node *ia32_lower_reload(void *self, ir_node *reload) {
498 ia32_code_gen_t *cg = self;
499 dbg_info *dbg = get_irn_dbg_info(reload);
500 ir_node *block = get_nodes_block(reload);
501 ir_node *ptr = get_irg_frame(cg->irg);
502 ir_mode *mode = get_irn_mode(reload);
503 ir_node *pred = get_irn_n(reload, 0);
504 ir_node *noreg = be_new_NoReg(cg->irg);
509 if (be_is_Spill(pred)) {
510 entity *ent = be_get_spill_entity(pred);
511 unsigned offs = get_entity_offset_bytes(ent);
512 DB((cg->mod, LEVEL_1, "lower_reload: got offset %d for %+F\n", offs, ent));
514 snprintf(buf, sizeof(buf), "%d", offs);
516 else if (is_ia32_Store(pred)) {
517 ofs = get_ia32_am_offs(pred);
518 strncpy(buf, ofs, sizeof(buf));
522 assert(0 && "unsupported Reload predecessor");
525 res = new_rd_ia32_Load(dbg, cg->irg, block, ptr, noreg, pred, mode);
526 add_ia32_am_offs(res, buf);
532 * Return the stack register for this irg.
534 static const arch_register_t *ia32_get_stack_register(void *self) {
535 ia32_code_gen_t *cg = self;
537 if (cg->has_alloca) {
538 return &ia32_gp_regs[REG_EBP];
541 return &ia32_gp_regs[REG_ESP];
545 * Emits the code, closes the output file and frees
546 * the code generator interface.
548 static void ia32_codegen(void *self) {
549 ia32_code_gen_t *cg = self;
550 ir_graph *irg = cg->irg;
553 if (cg->emit_decls) {
554 ia32_gen_decls(cg->out);
558 ia32_finish_irg(irg, cg);
559 //dump_ir_block_graph_sched(irg, "-finished");
560 ia32_gen_routine(out, irg, cg);
564 pmap_destroy(cg->tv_ent);
565 pmap_destroy(cg->types);
567 /* de-allocate code generator */
568 del_set(cg->reg_set);
572 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env);
574 static const arch_code_generator_if_t ia32_code_gen_if = {
577 ia32_before_sched, /* before scheduling hook */
578 ia32_before_ra, /* before register allocation hook */
581 ia32_get_stack_register,
582 ia32_codegen /* emit && done */
586 * Initializes the code generator.
588 static void *ia32_cg_init(FILE *F, ir_graph *irg, const arch_env_t *arch_env) {
589 ia32_isa_t *isa = (ia32_isa_t *)arch_env->isa;
590 ia32_code_gen_t *cg = xmalloc(sizeof(*cg));
592 cg->impl = &ia32_code_gen_if;
594 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
595 cg->mod = firm_dbg_register("firm.be.ia32.cg");
597 cg->arch_env = arch_env;
598 cg->types = pmap_create();
599 cg->tv_ent = pmap_create();
603 if (isa->num_codegens > 1)
608 cur_reg_set = cg->reg_set;
610 ia32_irn_ops.cg = cg;
612 return (arch_code_generator_t *)cg;
617 /*****************************************************************
618 * ____ _ _ _____ _____
619 * | _ \ | | | | |_ _|/ ____| /\
620 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
621 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
622 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
623 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
625 *****************************************************************/
628 * Initializes the backend ISA and opens the output file.
630 static void *ia32_init(void) {
631 static int inited = 0;
632 ia32_isa_t *isa = xmalloc(sizeof(*isa));
634 isa->impl = &ia32_isa_if;
641 isa->num_codegens = 0;
642 isa->reg_projnum_map = new_set(ia32_cmp_reg_projnum_assoc, 1024);
644 ia32_register_init(isa);
645 ia32_create_opcodes();
653 * Closes the output file and frees the ISA structure.
655 static void ia32_done(void *self) {
661 static int ia32_get_n_reg_class(const void *self) {
665 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
666 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
667 return &ia32_reg_classes[i];
670 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
671 return &ia32_irn_ops;
674 const arch_irn_handler_t ia32_irn_handler = {
678 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
679 return &ia32_irn_handler;
682 long ia32_handle_call_proj(const void *self, ir_node *proj, int is_keep) {
683 ia32_isa_t *isa = (ia32_isa_t *)self;
684 long pn = get_Proj_proj(proj);
687 /* It's not a Keep proj, which means, that it is a result proj. */
688 /* Possible result proj numbers are 0 and 1 */
689 /* Set the correct register (depends on the mode) and the */
690 /* corresponding proj number */
691 if (mode_is_float(get_irn_mode(proj))) {
692 assert(pn == 0 && "only one floating point result supported");
694 /* Get the proj number for the floating point result */
695 pn = ia32_get_reg_projnum(&ia32_fp_regs[REG_XMM0], isa->reg_projnum_map);
698 /* In case of 64bit return value, the result is */
699 /* in EDX:EAX and we have two result projs. */
702 pn = ia32_get_reg_projnum(&ia32_gp_regs[REG_EAX], isa->reg_projnum_map);
705 pn = ia32_get_reg_projnum(&ia32_gp_regs[REG_EDX], isa->reg_projnum_map);
708 assert(0 && "only two int results supported");
712 /* Set the correct proj number */
713 set_Proj_proj(proj, pn);
716 /* Set mode to floating point if required */
717 if (!strcmp(ia32_reg_classes[CLASS_ia32_fp].name,
718 ia32_projnum_reg_req_map[pn]->req.cls->name)) {
719 set_irn_mode(proj, mode_F);
726 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
727 return is_ia32_irn(irn);
731 * Initializes the code generator interface.
733 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
734 return &ia32_code_gen_if;
737 list_sched_selector_t ia32_sched_selector;
740 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
742 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
743 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
744 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
745 return &ia32_sched_selector;
749 static void ia32_register_options(lc_opt_entry_t *ent)
752 #endif /* WITH_LIBCORE */
754 const arch_isa_if_t ia32_isa_if = {
756 ia32_register_options,
760 ia32_get_n_reg_class,
762 ia32_get_irn_handler,
763 ia32_get_code_generator_if,
764 ia32_get_list_sched_selector,
765 ia32_handle_call_proj