2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
24 #include "pseudo_irg.h"
28 #include "iredges_t.h"
36 #include "../beabi.h" /* the general register allocator interface */
37 #include "../benode_t.h"
38 #include "../belower.h"
39 #include "../besched_t.h"
41 #include "bearch_ia32_t.h"
43 #include "ia32_new_nodes.h" /* ia32 nodes interface */
44 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
45 #include "ia32_gen_decls.h" /* interface declaration emitter */
46 #include "ia32_transform.h"
47 #include "ia32_emitter.h"
48 #include "ia32_map_regs.h"
49 #include "ia32_optimize.h"
51 #include "ia32_dbg_stat.h"
52 #include "ia32_finish.h"
54 #define DEBUG_MODULE "firm.be.ia32.isa"
57 static set *cur_reg_set = NULL;
60 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
62 /* Creates the unique per irg GP NoReg node. */
63 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
64 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_GP_NOREG]);
67 /* Creates the unique per irg FP NoReg node. */
68 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
69 return be_abi_get_callee_save_irn(cg->birg->abi,
70 USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG]);
73 /* returns the first Proj with given mode from mode_T node */
74 static ir_node *get_proj_for_mode(ir_node *node, ir_mode *mode) {
75 const ir_edge_t *edge;
77 assert(get_irn_mode(node) == mode_T && "Need mode_T node.");
79 foreach_out_edge(node, edge) {
80 ir_node *proj = get_edge_src_irn(edge);
81 if (get_irn_mode(proj) == mode)
88 /**************************************************
91 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
92 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
93 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
94 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
97 **************************************************/
99 static ir_node *my_skip_proj(const ir_node *n) {
101 n = get_Proj_pred(n);
107 * Return register requirements for an ia32 node.
108 * If the node returns a tuple (mode_T) then the proj's
109 * will be asked for this information.
111 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
112 const ia32_irn_ops_t *ops = self;
113 const ia32_register_req_t *irn_req;
114 long node_pos = pos == -1 ? 0 : pos;
115 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
116 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
118 if (is_Block(irn) || mode == mode_M || mode == mode_X) {
119 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
123 if (mode == mode_T && pos < 0) {
124 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
128 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
132 node_pos = ia32_translate_proj_pos(irn);
138 irn = my_skip_proj(irn);
140 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
143 if (is_ia32_irn(irn)) {
145 irn_req = get_ia32_in_req(irn, pos);
148 irn_req = get_ia32_out_req(irn, node_pos);
151 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
153 memcpy(req, &(irn_req->req), sizeof(*req));
155 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
156 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
157 req->other_same = get_irn_n(irn, irn_req->same_pos);
160 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
161 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
162 req->other_different = get_irn_n(irn, irn_req->different_pos);
166 /* treat Unknowns like Const with default requirements */
167 if (is_Unknown(irn)) {
168 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
169 if (mode_is_float(mode)) {
170 if (USE_SSE2(ops->cg))
171 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
173 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
175 else if (mode_is_int(mode) || mode_is_reference(mode))
176 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
177 else if (mode == mode_T || mode == mode_M) {
178 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
182 assert(0 && "unsupported Unknown-Mode");
185 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
193 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
195 const ia32_irn_ops_t *ops = self;
197 if (get_irn_mode(irn) == mode_X) {
201 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
204 pos = ia32_translate_proj_pos(irn);
205 irn = my_skip_proj(irn);
208 if (is_ia32_irn(irn)) {
209 const arch_register_t **slots;
211 slots = get_ia32_slots(irn);
215 ia32_set_firm_reg(irn, reg, cur_reg_set);
219 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
221 const arch_register_t *reg = NULL;
225 if (get_irn_mode(irn) == mode_X) {
229 pos = ia32_translate_proj_pos(irn);
230 irn = my_skip_proj(irn);
233 if (is_ia32_irn(irn)) {
234 const arch_register_t **slots;
235 slots = get_ia32_slots(irn);
239 reg = ia32_get_firm_reg(irn, cur_reg_set);
245 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
246 irn = my_skip_proj(irn);
248 return arch_irn_class_branch;
249 else if (is_ia32_Cnst(irn))
250 return arch_irn_class_const;
251 else if (is_ia32_Ld(irn))
252 return arch_irn_class_load;
253 else if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
254 return arch_irn_class_store;
255 else if (is_ia32_irn(irn))
256 return arch_irn_class_normal;
261 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
262 irn = my_skip_proj(irn);
263 if (is_ia32_irn(irn))
264 return get_ia32_flags(irn);
267 return arch_irn_flags_ignore;
272 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
273 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
276 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
278 const ia32_irn_ops_t *ops = self;
280 if (get_ia32_frame_ent(irn)) {
281 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
283 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
284 snprintf(buf, sizeof(buf), "%d", bias);
286 if (get_ia32_op_type(irn) == ia32_Normal) {
287 set_ia32_cnst(irn, buf);
290 add_ia32_am_offs(irn, buf);
292 set_ia32_am_flavour(irn, am_flav);
298 be_abi_call_flags_bits_t flags;
299 const arch_isa_t *isa;
300 const arch_env_t *aenv;
304 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
306 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
307 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
308 env->flags = fl.bits;
311 env->isa = aenv->isa;
316 * Put all registers which are saved by the prologue/epilogue in a set.
318 * @param self The callback object.
319 * @param s The result set.
321 static void ia32_abi_dont_save_regs(void *self, pset *s)
323 ia32_abi_env_t *env = self;
324 if(env->flags.try_omit_fp)
325 pset_insert_ptr(s, env->isa->bp);
329 * Generate the routine prologue.
331 * @param self The callback object.
332 * @param mem A pointer to the mem node. Update this if you define new memory.
333 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
335 * @return The register which shall be used as a stack frame base.
337 * All nodes which define registers in @p reg_map must keep @p reg_map current.
339 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
341 ia32_abi_env_t *env = self;
343 if (!env->flags.try_omit_fp) {
344 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
345 ir_node *bl = get_irg_start_block(env->irg);
346 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
347 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
351 push = new_rd_ia32_Push(NULL, env->irg, bl, curr_sp, curr_bp, *mem);
352 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
353 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
355 /* the push must have SP out register */
356 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
357 set_ia32_flags(push, arch_irn_flags_ignore);
359 /* move esp to ebp */
360 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
361 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
362 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
363 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
365 /* beware: the copy must be done before any other sp use */
366 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
367 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
368 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
369 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
371 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
372 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
381 * Generate the routine epilogue.
382 * @param self The callback object.
383 * @param bl The block for the epilog
384 * @param mem A pointer to the mem node. Update this if you define new memory.
385 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
386 * @return The register which shall be used as a stack frame base.
388 * All nodes which define registers in @p reg_map must keep @p reg_map current.
390 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
392 ia32_abi_env_t *env = self;
393 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
394 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
396 if (env->flags.try_omit_fp) {
397 /* simply remove the stack frame here */
398 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, *mem, BE_STACK_FRAME_SIZE, be_stack_dir_shrink);
401 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
402 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
403 int reg_size = get_mode_size_bytes(env->isa->bp->reg_class->mode);
405 /* gcc always emits a leave at the end of a routine */
406 if (1 || ARCH_AMD(isa->opt_arch)) {
410 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, *mem);
411 set_ia32_flags(leave, arch_irn_flags_ignore);
412 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
413 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
414 *mem = new_r_Proj(current_ir_graph, bl, leave, mode_M, pn_ia32_Leave_M);
419 /* copy ebp to esp */
420 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
423 pop = new_rd_ia32_Pop(NULL, env->irg, bl, curr_sp, *mem);
424 set_ia32_flags(pop, arch_irn_flags_ignore);
425 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
426 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
427 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
429 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
430 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
433 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
434 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
438 * Produces the type which sits between the stack args and the locals on the stack.
439 * it will contain the return address and space to store the old base pointer.
440 * @return The Firm type modeling the ABI between type.
442 static ir_type *ia32_abi_get_between_type(void *self)
444 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
445 static ir_type *omit_fp_between_type = NULL;
446 static ir_type *between_type = NULL;
448 ia32_abi_env_t *env = self;
450 if ( !between_type) {
452 entity *ret_addr_ent;
453 entity *omit_fp_ret_addr_ent;
455 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_P);
456 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_P);
458 between_type = new_type_struct(IDENT("ia32_between_type"));
459 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
460 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
462 set_entity_offset_bytes(old_bp_ent, 0);
463 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
464 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
465 set_type_state(between_type, layout_fixed);
467 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
468 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
470 set_entity_offset_bytes(omit_fp_ret_addr_ent, 0);
471 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
472 set_type_state(omit_fp_between_type, layout_fixed);
475 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
480 * Get the estimated cycle count for @p irn.
482 * @param self The this pointer.
483 * @param irn The node.
485 * @return The estimated cycle count for this operation
487 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
490 switch (get_ia32_irn_opcode(irn)) {
492 case iro_ia32_DivMod:
497 case iro_ia32_l_Load:
507 case iro_ia32_xStore:
508 case iro_ia32_l_Store:
510 case iro_ia32_Store8Bit:
518 case iro_ia32_l_MulS:
531 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
533 * @param irn The original operation
534 * @param i Index of the argument we want the inverse operation to yield
535 * @param inverse struct to be filled with the resulting inverse op
536 * @param obstack The obstack to use for allocation of the returned nodes array
537 * @return The inverse operation or NULL if operation invertible
539 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
542 ir_node *block, *noreg, *nomem;
545 /* we cannot invert non-ia32 irns */
546 if (! is_ia32_irn(irn))
549 /* operand must always be a real operand (not base, index or mem) */
550 if (i != 2 && i != 3)
553 /* we don't invert address mode operations */
554 if (get_ia32_op_type(irn) != ia32_Normal)
557 irg = get_irn_irg(irn);
558 block = get_nodes_block(irn);
559 mode = get_ia32_res_mode(irn);
560 noreg = get_irn_n(irn, 0);
561 nomem = new_r_NoMem(irg);
563 /* initialize structure */
564 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
568 switch (get_ia32_irn_opcode(irn)) {
570 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
571 /* we have an add with a const here */
572 /* invers == add with negated const */
573 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
574 pnc = pn_ia32_Add_res;
576 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
577 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
578 set_ia32_commutative(inverse->nodes[0]);
580 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
581 /* we have an add with a symconst here */
582 /* invers == sub with const */
583 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
584 pnc = pn_ia32_Sub_res;
586 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
589 /* normal add: inverse == sub */
590 ir_node *proj = get_irn_out_edge_first(irn)->src;
591 assert(proj && is_Proj(proj));
593 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, i ^ 1), nomem);
594 pnc = pn_ia32_Sub_res;
599 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
600 /* we have a sub with a const/symconst here */
601 /* invers == add with this const */
602 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
603 pnc = pn_ia32_Add_res;
604 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
605 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
609 ir_node *proj = get_irn_out_edge_first(irn)->src;
610 assert(proj && is_Proj(proj));
613 inverse->nodes[0] = new_rd_ia32_Add(NULL, irg, block, noreg, noreg, proj, get_irn_n(irn, 3), nomem);
616 inverse->nodes[0] = new_rd_ia32_Sub(NULL, irg, block, noreg, noreg, get_irn_n(irn, 2), proj, nomem);
618 pnc = pn_ia32_Sub_res;
623 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
624 /* xor with const: inverse = xor */
625 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
626 pnc = pn_ia32_Eor_res;
627 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
628 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
632 inverse->nodes[0] = new_rd_ia32_Eor(NULL, irg, block, noreg, noreg, (ir_node *)irn, get_irn_n(irn, i), nomem);
633 pnc = pn_ia32_Eor_res;
638 inverse->nodes[0] = new_rd_ia32_Not(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), nomem);
639 pnc = pn_ia32_Not_res;
643 inverse->nodes[0] = new_rd_ia32_Minus(NULL, irg, block, noreg, noreg, get_irn_n(irn, i), nomem);
644 pnc = pn_ia32_Minus_res;
648 /* inverse operation not supported */
652 set_ia32_res_mode(inverse->nodes[0], mode);
653 inverse->nodes[1] = new_r_Proj(irg, block, inverse->nodes[0], mode, pnc);
658 static const be_abi_callbacks_t ia32_abi_callbacks = {
661 ia32_abi_get_between_type,
662 ia32_abi_dont_save_regs,
667 /* fill register allocator interface */
669 static const arch_irn_ops_if_t ia32_irn_ops_if = {
670 ia32_get_irn_reg_req,
675 ia32_get_frame_entity,
678 ia32_get_op_estimated_cost
681 ia32_irn_ops_t ia32_irn_ops = {
688 /**************************************************
691 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
692 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
693 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
694 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
697 **************************************************/
700 * Transforms the standard firm graph into
703 static void ia32_prepare_graph(void *self) {
704 ia32_code_gen_t *cg = self;
705 dom_front_info_t *dom;
706 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
708 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
710 /* 1st: transform constants and psi condition trees */
711 ia32_pre_transform_phase(cg);
713 /* 2nd: transform all remaining nodes */
714 ia32_register_transformers();
715 dom = be_compute_dominance_frontiers(cg->irg);
716 irg_walk_blkwise_graph(cg->irg, NULL, ia32_transform_node, cg);
717 be_free_dominance_frontiers(dom);
720 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
722 /* 3rd: optimize address mode */
723 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
724 ia32_optimize_addressmode(cg);
727 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
729 DEBUG_ONLY(cg->mod = old_mod;)
733 * Dummy functions for hooks we don't need but which must be filled.
735 static void ia32_before_sched(void *self) {
738 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
746 mode = get_irn_mode(irn);
748 /* check if we already saw this node or the node has more than one user */
749 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1)
752 /* mark irn visited */
753 bitset_add_irn(already_visited, irn);
755 /* non-Tuple nodes with one user: ok, return */
756 if (get_irn_n_edges(irn) >= 1 && mode != mode_T)
759 /* tuple node has one user which is not the mem proj-> ok */
760 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
761 mem_proj = get_proj_for_mode(irn, mode_M);
766 for (i = get_irn_arity(irn) - 1; i >= 0; i--) {
767 ir_node *pred = get_irn_n(irn, i);
769 /* do not follow memory edges or we will accidentally remove stores */
770 if (is_Proj(pred) && get_irn_mode(pred) == mode_M)
773 set_irn_n(irn, i, new_Bad());
776 The current node is about to be removed: if the predecessor
777 has only this node as user, it need to be removed as well.
779 if (get_irn_n_edges(pred) <= 1)
780 remove_unused_nodes(pred, already_visited);
783 if (sched_is_scheduled(irn))
787 static void remove_unused_loads_walker(ir_node *irn, void *env) {
788 bitset_t *already_visited = env;
789 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
790 remove_unused_nodes(irn, env);
794 * Called before the register allocator.
795 * Calculate a block schedule here. We need it for the x87
796 * simulator and the emitter.
798 static void ia32_before_ra(void *self) {
799 ia32_code_gen_t *cg = self;
800 bitset_t *already_visited = bitset_irg_malloc(cg->irg);
802 cg->blk_sched = sched_create_block_schedule(cg->irg);
806 There are sometimes unused loads, only pinned by memory.
807 We need to remove those Loads and all other nodes which won't be used
808 after removing the Load from schedule.
810 irg_walk_graph(cg->irg, remove_unused_loads_walker, NULL, already_visited);
811 bitset_free(already_visited);
816 * Transforms a be node into a Load.
818 static void transform_to_Load(ia32_transform_env_t *env) {
819 ir_node *irn = env->irn;
820 entity *ent = be_get_frame_entity(irn);
821 ir_mode *mode = env->mode;
822 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
823 ir_node *nomem = new_rd_NoMem(env->irg);
824 ir_node *sched_point = NULL;
825 ir_node *ptr = get_irn_n(irn, 0);
826 ir_node *mem = be_is_Reload(irn) ? get_irn_n(irn, 1) : nomem;
827 ir_node *new_op, *proj;
828 const arch_register_t *reg;
830 if (sched_is_scheduled(irn)) {
831 sched_point = sched_prev(irn);
834 if (mode_is_float(mode)) {
835 if (USE_SSE2(env->cg))
836 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
838 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
841 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
844 set_ia32_am_support(new_op, ia32_am_Source);
845 set_ia32_op_type(new_op, ia32_AddrModeS);
846 set_ia32_am_flavour(new_op, ia32_B);
847 set_ia32_ls_mode(new_op, mode);
848 set_ia32_frame_ent(new_op, ent);
849 set_ia32_use_frame(new_op);
851 DBG_OPT_RELOAD2LD(irn, new_op);
853 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
856 sched_add_after(sched_point, new_op);
857 sched_add_after(new_op, proj);
862 /* copy the register from the old node to the new Load */
863 reg = arch_get_irn_register(env->cg->arch_env, irn);
864 arch_set_irn_register(env->cg->arch_env, new_op, reg);
866 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
872 * Transforms a be node into a Store.
874 static void transform_to_Store(ia32_transform_env_t *env) {
875 ir_node *irn = env->irn;
876 entity *ent = be_get_frame_entity(irn);
877 ir_mode *mode = env->mode;
878 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
879 ir_node *nomem = new_rd_NoMem(env->irg);
880 ir_node *ptr = get_irn_n(irn, 0);
881 ir_node *val = get_irn_n(irn, 1);
882 ir_node *new_op, *proj;
883 ir_node *sched_point = NULL;
885 if (sched_is_scheduled(irn)) {
886 sched_point = sched_prev(irn);
889 if (mode_is_float(mode)) {
890 if (USE_SSE2(env->cg))
891 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
893 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
895 else if (get_mode_size_bits(mode) == 8) {
896 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
899 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem);
902 set_ia32_am_support(new_op, ia32_am_Dest);
903 set_ia32_op_type(new_op, ia32_AddrModeD);
904 set_ia32_am_flavour(new_op, ia32_B);
905 set_ia32_ls_mode(new_op, mode);
906 set_ia32_frame_ent(new_op, ent);
907 set_ia32_use_frame(new_op);
909 DBG_OPT_SPILL2ST(irn, new_op);
911 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode_M, pn_ia32_Store_M);
914 sched_add_after(sched_point, new_op);
918 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, irn));
924 * Fix the mode of Spill/Reload
926 static ir_mode *fix_spill_mode(ia32_code_gen_t *cg, ir_mode *mode)
928 if (mode_is_float(mode)) {
940 * Block-Walker: Calls the transform functions Spill and Reload.
942 static void ia32_after_ra_walker(ir_node *block, void *env) {
943 ir_node *node, *prev;
944 ia32_code_gen_t *cg = env;
945 ia32_transform_env_t tenv;
948 tenv.irg = current_ir_graph;
950 DEBUG_ONLY(tenv.mod = cg->mod;)
952 /* beware: the schedule is changed here */
953 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
954 prev = sched_prev(node);
955 if (be_is_Reload(node)) {
956 /* we always reload the whole register */
957 tenv.dbg = get_irn_dbg_info(node);
959 tenv.mode = fix_spill_mode(cg, get_irn_mode(node));
960 transform_to_Load(&tenv);
962 else if (be_is_Spill(node)) {
963 /* we always spill the whole register */
964 tenv.dbg = get_irn_dbg_info(node);
966 tenv.mode = fix_spill_mode(cg, get_irn_mode(be_get_Spill_context(node)));
967 transform_to_Store(&tenv);
973 * We transform Spill and Reload here. This needs to be done before
974 * stack biasing otherwise we would miss the corrected offset for these nodes.
976 * If x87 instruction should be emitted, run the x87 simulator and patch
977 * the virtual instructions. This must obviously be done after register allocation.
979 static void ia32_after_ra(void *self) {
980 ia32_code_gen_t *cg = self;
981 irg_block_walk_graph(cg->irg, NULL, ia32_after_ra_walker, self);
983 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
984 if (cg->used_fp == fp_x87 || cg->force_sim) {
985 x87_simulate_graph(cg->arch_env, cg->irg, cg->blk_sched);
991 * Emits the code, closes the output file and frees
992 * the code generator interface.
994 static void ia32_codegen(void *self) {
995 ia32_code_gen_t *cg = self;
996 ir_graph *irg = cg->irg;
998 ia32_finish_irg(irg, cg);
1000 be_dump(irg, "-finished", dump_ir_block_graph_sched);
1001 ia32_gen_routine(cg->isa->out, irg, cg);
1005 /* remove it from the isa */
1008 /* de-allocate code generator */
1009 del_set(cg->reg_set);
1014 static void *ia32_cg_init(const be_irg_t *birg);
1016 static const arch_code_generator_if_t ia32_code_gen_if = {
1018 NULL, /* before abi introduce hook */
1020 ia32_before_sched, /* before scheduling hook */
1021 ia32_before_ra, /* before register allocation hook */
1022 ia32_after_ra, /* after register allocation hook */
1023 ia32_codegen /* emit && done */
1027 * Initializes a IA32 code generator.
1029 static void *ia32_cg_init(const be_irg_t *birg) {
1030 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1031 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1033 cg->impl = &ia32_code_gen_if;
1034 cg->irg = birg->irg;
1035 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1036 cg->arch_env = birg->main_env->arch_env;
1039 cg->blk_sched = NULL;
1040 cg->fp_to_gp = NULL;
1041 cg->gp_to_fp = NULL;
1042 cg->fp_kind = isa->fp_kind;
1043 cg->used_fp = fp_none;
1044 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1046 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1048 /* copy optimizations from isa for easier access */
1050 cg->arch = isa->arch;
1051 cg->opt_arch = isa->opt_arch;
1057 if (isa->name_obst_size) {
1058 //printf("freed %d bytes from name obst\n", isa->name_obst_size);
1059 isa->name_obst_size = 0;
1060 obstack_free(isa->name_obst, NULL);
1061 obstack_init(isa->name_obst);
1065 cur_reg_set = cg->reg_set;
1067 ia32_irn_ops.cg = cg;
1069 return (arch_code_generator_t *)cg;
1074 /*****************************************************************
1075 * ____ _ _ _____ _____
1076 * | _ \ | | | | |_ _|/ ____| /\
1077 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1078 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1079 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1080 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1082 *****************************************************************/
1085 * Set output modes for GCC
1087 static const tarval_mode_info mo_integer = {
1094 * set the tarval output mode to C-semantics
1096 static void set_tarval_output_modes(void)
1098 set_tarval_mode_output_option(get_modeLs(), &mo_integer);
1099 set_tarval_mode_output_option(get_modeLu(), &mo_integer);
1100 set_tarval_mode_output_option(get_modeIs(), &mo_integer);
1101 set_tarval_mode_output_option(get_modeIu(), &mo_integer);
1102 set_tarval_mode_output_option(get_modeHs(), &mo_integer);
1103 set_tarval_mode_output_option(get_modeHu(), &mo_integer);
1104 set_tarval_mode_output_option(get_modeBs(), &mo_integer);
1105 set_tarval_mode_output_option(get_modeBu(), &mo_integer);
1106 set_tarval_mode_output_option(get_modeC(), &mo_integer);
1107 set_tarval_mode_output_option(get_modeU(), &mo_integer);
1108 set_tarval_mode_output_option(get_modeIu(), &mo_integer);
1113 * The template that generates a new ISA object.
1114 * Note that this template can be changed by command line
1117 static ia32_isa_t ia32_isa_template = {
1119 &ia32_isa_if, /* isa interface implementation */
1120 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1121 &ia32_gp_regs[REG_EBP], /* base pointer register */
1122 -1, /* stack direction */
1124 NULL, /* 16bit register names */
1125 NULL, /* 8bit register names */
1129 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1130 IA32_OPT_DOAM | /* optimize address mode default: on */
1131 IA32_OPT_LEA | /* optimize for LEAs default: on */
1132 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1133 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1134 IA32_OPT_EXTBB), /* use extended basic block scheduling, default: on */
1135 arch_pentium_4, /* instruction architecture */
1136 arch_pentium_4, /* optimize for architecture */
1137 fp_sse2, /* use sse2 unit */
1138 NULL, /* current code generator */
1140 NULL, /* name obstack */
1141 0 /* name obst size */
1146 * Initializes the backend ISA.
1148 static void *ia32_init(FILE *file_handle) {
1149 static int inited = 0;
1155 set_tarval_output_modes();
1157 isa = xmalloc(sizeof(*isa));
1158 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1160 ia32_register_init(isa);
1161 ia32_create_opcodes();
1163 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1164 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1165 /* no SSE2 for these cpu's */
1166 isa->fp_kind = fp_x87;
1168 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1169 /* Pentium 4 don't like inc and dec instructions */
1170 isa->opt &= ~IA32_OPT_INCDEC;
1173 isa->regs_16bit = pmap_create();
1174 isa->regs_8bit = pmap_create();
1175 isa->types = pmap_create();
1176 isa->tv_ent = pmap_create();
1177 isa->out = file_handle;
1179 ia32_build_16bit_reg_map(isa->regs_16bit);
1180 ia32_build_8bit_reg_map(isa->regs_8bit);
1182 /* patch register names of x87 registers */
1184 ia32_st_regs[0].name = "st";
1185 ia32_st_regs[1].name = "st(1)";
1186 ia32_st_regs[2].name = "st(2)";
1187 ia32_st_regs[3].name = "st(3)";
1188 ia32_st_regs[4].name = "st(4)";
1189 ia32_st_regs[5].name = "st(5)";
1190 ia32_st_regs[6].name = "st(6)";
1191 ia32_st_regs[7].name = "st(7)";
1195 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1196 obstack_init(isa->name_obst);
1197 isa->name_obst_size = 0;
1200 ia32_handle_intrinsics();
1201 ia32_switch_section(NULL, NO_SECTION);
1202 fprintf(isa->out, "\t.intel_syntax\n");
1212 * Closes the output file and frees the ISA structure.
1214 static void ia32_done(void *self) {
1215 ia32_isa_t *isa = self;
1217 /* emit now all global declarations */
1218 ia32_gen_decls(isa->out);
1220 pmap_destroy(isa->regs_16bit);
1221 pmap_destroy(isa->regs_8bit);
1222 pmap_destroy(isa->tv_ent);
1223 pmap_destroy(isa->types);
1226 //printf("name obst size = %d bytes\n", isa->name_obst_size);
1227 obstack_free(isa->name_obst, NULL);
1235 * Return the number of register classes for this architecture.
1236 * We report always these:
1237 * - the general purpose registers
1238 * - the SSE floating point register set
1239 * - the virtual floating point registers
1241 static int ia32_get_n_reg_class(const void *self) {
1246 * Return the register class for index i.
1248 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1249 const ia32_isa_t *isa = self;
1250 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1252 return &ia32_reg_classes[CLASS_ia32_gp];
1254 return &ia32_reg_classes[CLASS_ia32_xmm];
1256 return &ia32_reg_classes[CLASS_ia32_vfp];
1260 * Get the register class which shall be used to store a value of a given mode.
1261 * @param self The this pointer.
1262 * @param mode The mode in question.
1263 * @return A register class which can hold values of the given mode.
1265 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1266 const ia32_isa_t *isa = self;
1267 if (mode_is_float(mode)) {
1268 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1271 return &ia32_reg_classes[CLASS_ia32_gp];
1275 * Get the ABI restrictions for procedure calls.
1276 * @param self The this pointer.
1277 * @param method_type The type of the method (procedure) in question.
1278 * @param abi The abi object to be modified
1280 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1281 const ia32_isa_t *isa = self;
1284 unsigned cc = get_method_calling_convention(method_type);
1285 int n = get_method_n_params(method_type);
1288 int i, ignore_1, ignore_2;
1290 const arch_register_t *reg;
1291 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1293 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1295 /* set abi flags for calls */
1296 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1297 call_flags.bits.store_args_sequential = use_push;
1298 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1299 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1300 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1302 /* set stack parameter passing style */
1303 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1305 /* collect the mode for each type */
1306 modes = alloca(n * sizeof(modes[0]));
1308 for (i = 0; i < n; i++) {
1309 tp = get_method_param_type(method_type, i);
1310 modes[i] = get_type_mode(tp);
1313 /* set register parameters */
1314 if (cc & cc_reg_param) {
1315 /* determine the number of parameters passed via registers */
1316 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1318 /* loop over all parameters and set the register requirements */
1319 for (i = 0; i <= biggest_n; i++) {
1320 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1321 assert(reg && "kaputt");
1322 be_abi_call_param_reg(abi, i, reg);
1329 /* set stack parameters */
1330 for (i = stack_idx; i < n; i++) {
1331 be_abi_call_param_stack(abi, i, 1, 0, 0);
1335 /* set return registers */
1336 n = get_method_n_ress(method_type);
1338 assert(n <= 2 && "more than two results not supported");
1340 /* In case of 64bit returns, we will have two 32bit values */
1342 tp = get_method_res_type(method_type, 0);
1343 mode = get_type_mode(tp);
1345 assert(!mode_is_float(mode) && "two FP results not supported");
1347 tp = get_method_res_type(method_type, 1);
1348 mode = get_type_mode(tp);
1350 assert(!mode_is_float(mode) && "two FP results not supported");
1352 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1353 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1356 const arch_register_t *reg;
1358 tp = get_method_res_type(method_type, 0);
1359 assert(is_atomic_type(tp));
1360 mode = get_type_mode(tp);
1362 reg = mode_is_float(mode) ?
1363 (USE_SSE2(isa) ? &ia32_xmm_regs[REG_XMM0] : &ia32_vfp_regs[REG_VF0]) :
1364 &ia32_gp_regs[REG_EAX];
1366 be_abi_call_res_reg(abi, 0, reg);
1371 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1372 return &ia32_irn_ops;
1375 const arch_irn_handler_t ia32_irn_handler = {
1379 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1380 return &ia32_irn_handler;
1383 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1384 return is_ia32_irn(irn) ? 1 : -1;
1388 * Initializes the code generator interface.
1390 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1391 return &ia32_code_gen_if;
1394 list_sched_selector_t ia32_sched_selector;
1397 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1399 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
1400 // memcpy(&ia32_sched_selector, reg_pressure_selector, sizeof(list_sched_selector_t));
1401 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
1402 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1403 return &ia32_sched_selector;
1407 * Returns the necessary byte alignment for storing a register of given class.
1409 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1410 ir_mode *mode = arch_register_class_mode(cls);
1411 int bytes = get_mode_size_bytes(mode);
1413 if (mode_is_float(mode) && bytes > 8)
1418 static ia32_intrinsic_env_t intrinsic_env = { NULL, NULL };
1421 * Returns the libFirm configuration parameter for this backend.
1423 static const backend_params *ia32_get_libfirm_params(void) {
1424 static const arch_dep_params_t ad = {
1425 1, /* also use subs */
1426 4, /* maximum shifts */
1427 31, /* maximum shift amount */
1429 1, /* allow Mulhs */
1430 1, /* allow Mulus */
1431 32 /* Mulh allowed up to 32 bit */
1433 static backend_params p = {
1434 NULL, /* no additional opcodes */
1435 NULL, /* will be set later */
1436 1, /* need dword lowering */
1437 ia32_create_intrinsic_fkt,
1438 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1446 /* instruction set architectures. */
1447 static const lc_opt_enum_int_items_t arch_items[] = {
1448 { "386", arch_i386, },
1449 { "486", arch_i486, },
1450 { "pentium", arch_pentium, },
1451 { "586", arch_pentium, },
1452 { "pentiumpro", arch_pentium_pro, },
1453 { "686", arch_pentium_pro, },
1454 { "pentiummmx", arch_pentium_mmx, },
1455 { "pentium2", arch_pentium_2, },
1456 { "p2", arch_pentium_2, },
1457 { "pentium3", arch_pentium_3, },
1458 { "p3", arch_pentium_3, },
1459 { "pentium4", arch_pentium_4, },
1460 { "p4", arch_pentium_4, },
1461 { "pentiumm", arch_pentium_m, },
1462 { "pm", arch_pentium_m, },
1463 { "core", arch_core, },
1465 { "athlon", arch_athlon, },
1466 { "athlon64", arch_athlon_64, },
1467 { "opteron", arch_opteron, },
1471 static lc_opt_enum_int_var_t arch_var = {
1472 &ia32_isa_template.arch, arch_items
1475 static lc_opt_enum_int_var_t opt_arch_var = {
1476 &ia32_isa_template.opt_arch, arch_items
1479 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1481 { "sse2", fp_sse2 },
1485 static lc_opt_enum_int_var_t fp_unit_var = {
1486 &ia32_isa_template.fp_kind, fp_unit_items
1489 static const lc_opt_enum_int_items_t gas_items[] = {
1490 { "linux", ASM_LINUX_GAS },
1491 { "mingw", ASM_MINGW_GAS },
1495 static lc_opt_enum_int_var_t gas_var = {
1496 (int *)&asm_flavour, gas_items
1499 static const lc_opt_table_entry_t ia32_options[] = {
1500 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
1501 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
1502 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
1503 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
1504 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
1505 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
1506 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
1507 LC_OPT_ENT_NEGBIT("noextbb", "do not use extended basic block scheduling", &ia32_isa_template.opt, IA32_OPT_EXTBB),
1508 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
1513 * Register command line options for the ia32 backend.
1517 * ia32-arch=arch create instruction for arch
1518 * ia32-opt=arch optimize for run on arch
1519 * ia32-fpunit=unit select floating point unit (x87 or SSE2)
1520 * ia32-incdec optimize for inc/dec
1521 * ia32-noaddrmode do not use address mode
1522 * ia32-nolea do not optimize for LEAs
1523 * ia32-noplacecnst do not place constants,
1524 * ia32-noimmop no operations with immediates
1525 * ia32-noextbb do not use extended basic block scheduling
1526 * ia32-gasmode set the GAS compatibility mode
1528 static void ia32_register_options(lc_opt_entry_t *ent)
1530 lc_opt_entry_t *be_grp_ia32 = lc_opt_get_grp(ent, "ia32");
1531 lc_opt_add_table(be_grp_ia32, ia32_options);
1533 #endif /* WITH_LIBCORE */
1535 const arch_isa_if_t ia32_isa_if = {
1538 ia32_get_n_reg_class,
1540 ia32_get_reg_class_for_mode,
1542 ia32_get_irn_handler,
1543 ia32_get_code_generator_if,
1544 ia32_get_list_sched_selector,
1545 ia32_get_reg_class_alignment,
1546 ia32_get_libfirm_params,
1548 ia32_register_options