11 #include "pseudo_irg.h"
15 #include "iredges_t.h"
22 #include "../beabi.h" /* the general register allocator interface */
23 #include "../benode_t.h"
24 #include "../belower.h"
25 #include "../besched_t.h"
27 #include "bearch_ia32_t.h"
29 #include "ia32_new_nodes.h" /* ia32 nodes interface */
30 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
31 #include "ia32_gen_decls.h" /* interface declaration emitter */
32 #include "ia32_transform.h"
33 #include "ia32_emitter.h"
34 #include "ia32_map_regs.h"
35 #include "ia32_optimize.h"
37 #define DEBUG_MODULE "firm.be.ia32.isa"
40 static set *cur_reg_set = NULL;
43 #define is_Start(irn) (get_irn_opcode(irn) == iro_Start)
45 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
46 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_gp_regs[REG_XXX]);
49 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
50 return be_abi_get_callee_save_irn(cg->birg->abi, &ia32_fp_regs[REG_XXXX]);
53 /**************************************************
56 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
57 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
58 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
59 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
62 **************************************************/
64 static ir_node *my_skip_proj(const ir_node *n) {
71 * Return register requirements for an ia32 node.
72 * If the node returns a tuple (mode_T) then the proj's
73 * will be asked for this information.
75 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
76 const ia32_register_req_t *irn_req;
77 long node_pos = pos == -1 ? 0 : pos;
78 ir_mode *mode = get_irn_mode(irn);
79 firm_dbg_module_t *mod = firm_dbg_register(DEBUG_MODULE);
80 const ia32_irn_ops_t *ops = self;
82 if (mode == mode_T || mode == mode_M) {
83 DBG((mod, LEVEL_1, "ignoring mode_T, mode_M node %+F\n", irn));
87 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
92 node_pos = ia32_translate_proj_pos(irn);
98 irn = my_skip_proj(irn);
100 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
103 if (is_ia32_irn(irn)) {
105 irn_req = get_ia32_in_req(irn, pos);
108 irn_req = get_ia32_out_req(irn, node_pos);
111 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
113 memcpy(req, &(irn_req->req), sizeof(*req));
115 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
116 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
117 req->other_same = get_irn_n(irn, irn_req->same_pos);
120 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
121 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
122 req->other_different = get_irn_n(irn, irn_req->different_pos);
126 /* treat Phi like Const with default requirements */
128 DB((mod, LEVEL_1, "returning standard reqs for %+F\n", irn));
129 if (mode_is_float(mode))
130 memcpy(req, &(ia32_default_req_ia32_fp.req), sizeof(*req));
131 else if (mode_is_int(mode) || mode_is_reference(mode))
132 memcpy(req, &(ia32_default_req_ia32_gp.req), sizeof(*req));
133 else if (mode == mode_T || mode == mode_M) {
134 DBG((mod, LEVEL_1, "ignoring Phi node %+F\n", irn));
138 assert(0 && "unsupported Phi-Mode");
141 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
149 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
153 pos = ia32_translate_proj_pos(irn);
154 irn = my_skip_proj(irn);
157 if (is_ia32_irn(irn)) {
158 const arch_register_t **slots;
160 slots = get_ia32_slots(irn);
164 ia32_set_firm_reg(irn, reg, cur_reg_set);
168 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
170 const arch_register_t *reg = NULL;
173 pos = ia32_translate_proj_pos(irn);
174 irn = my_skip_proj(irn);
177 if (is_ia32_irn(irn)) {
178 const arch_register_t **slots;
179 slots = get_ia32_slots(irn);
183 reg = ia32_get_firm_reg(irn, cur_reg_set);
189 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
190 irn = my_skip_proj(irn);
192 return arch_irn_class_branch;
193 else if (is_ia32_irn(irn))
194 return arch_irn_class_normal;
199 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
200 irn = my_skip_proj(irn);
201 if (is_ia32_irn(irn))
202 return get_ia32_flags(irn);
208 static entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
209 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
212 static void ia32_set_stack_bias(const void *self, ir_node *irn, int bias) {
214 const ia32_irn_ops_t *ops = self;
216 if (is_ia32_use_frame(irn)) {
217 ia32_am_flavour_t am_flav = get_ia32_am_flavour(irn);
219 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
220 snprintf(buf, sizeof(buf), "%d", bias);
221 add_ia32_am_offs(irn, buf);
223 set_ia32_am_flavour(irn, am_flav);
227 /* fill register allocator interface */
229 static const arch_irn_ops_if_t ia32_irn_ops_if = {
230 ia32_get_irn_reg_req,
235 ia32_get_frame_entity,
239 ia32_irn_ops_t ia32_irn_ops = {
246 /**************************************************
249 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
250 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
251 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
252 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
255 **************************************************/
258 * Transforms the standard firm graph into
261 static void ia32_prepare_graph(void *self) {
262 ia32_code_gen_t *cg = self;
264 irg_walk_blkwise_graph(cg->irg, ia32_place_consts, ia32_transform_node, cg);
265 dump_ir_block_graph_sched(cg->irg, "-transformed");
266 edges_deactivate(cg->irg);
267 edges_activate(cg->irg);
268 irg_walk_blkwise_graph(cg->irg, NULL, ia32_optimize_am, cg);
269 dump_ir_block_graph_sched(cg->irg, "-am");
274 * Insert copies for all ia32 nodes where the should_be_same requirement
277 static void ia32_finish_irg_walker(ir_node *irn, void *env) {
278 ia32_code_gen_t *cg = env;
279 const ia32_register_req_t **reqs;
280 const arch_register_t *out_reg, *in_reg;
282 ir_node *copy, *in_node, *block;
284 if (! is_ia32_irn(irn))
287 reqs = get_ia32_out_req_all(irn);
288 n_res = get_ia32_n_res(irn);
289 block = get_nodes_block(irn);
291 /* check all OUT requirements, if there is a should_be_same */
292 for (i = 0; i < n_res; i++) {
293 if (arch_register_req_is(&(reqs[i]->req), should_be_same)) {
294 /* get in and out register */
295 out_reg = get_ia32_out_reg(irn, i);
296 in_node = get_irn_n(irn, reqs[i]->same_pos);
297 in_reg = arch_get_irn_register(cg->arch_env, in_node);
299 /* check if in and out register are equal */
300 if (arch_register_get_index(out_reg) != arch_register_get_index(in_reg)) {
301 DBG((cg->mod, LEVEL_1, "inserting copy for %+F in_pos %d\n", irn, reqs[i]->same_pos));
303 /* create copy from in register */
304 copy = be_new_Copy(arch_register_get_class(in_reg), cg->irg, block, in_node);
306 /* destination is the out register */
307 arch_set_irn_register(cg->arch_env, copy, out_reg);
309 /* insert copy before the node into the schedule */
310 sched_add_before(irn, copy);
317 * Add Copy nodes for not fulfilled should_be_equal constraints
319 static void ia32_finish_irg(ir_graph *irg, ia32_code_gen_t *cg) {
320 irg_walk_blkwise_graph(irg, NULL, ia32_finish_irg_walker, cg);
326 * Dummy functions for hooks we don't need but which must be filled.
328 static void ia32_before_sched(void *self) {
331 static void ia32_before_ra(void *self) {
337 * Transforms a be node into a Load.
339 static void transform_to_Load(ia32_transform_env_t *env) {
340 ir_node *irn = env->irn;
341 entity *ent = be_get_frame_entity(irn);
342 ir_mode *mode = env->mode;
343 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
344 ir_node *nomem = new_rd_NoMem(env->irg);
345 ir_node *new_op, *proj;
346 ir_node *sched_point = NULL;
348 if (sched_is_scheduled(irn)) {
349 sched_point = sched_prev(irn);
352 if (mode_is_float(mode)) {
353 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_irn_n(irn, 0), noreg, nomem, mode_T);
356 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_irn_n(irn, 0), noreg, nomem, mode_T);
359 set_ia32_am_support(new_op, ia32_am_Source);
360 set_ia32_op_type(new_op, ia32_AddrModeS);
361 set_ia32_am_flavour(new_op, ia32_B);
362 set_ia32_ls_mode(new_op, mode);
363 set_ia32_frame_ent(new_op, ent);
364 set_ia32_use_frame(new_op);
366 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_Load_res);
369 sched_add_after(sched_point, new_op);
370 sched_add_after(new_op, proj);
380 * Transforms a be node into a Store.
382 static void transform_to_Store(ia32_transform_env_t *env) {
383 ir_node *irn = env->irn;
384 entity *ent = be_get_frame_entity(irn);
385 ir_mode *mode = env->mode;
386 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
387 ir_node *nomem = new_rd_NoMem(env->irg);
388 ir_node *ptr = get_irn_n(irn, 0);
389 ir_node *val = get_irn_n(irn, 1);
390 ir_node *new_op, *proj;
391 ir_node *sched_point = NULL;
393 if (sched_is_scheduled(irn)) {
394 sched_point = sched_prev(irn);
397 if (mode_is_float(mode)) {
398 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
401 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, nomem, mode_T);
404 set_ia32_am_support(new_op, ia32_am_Dest);
405 set_ia32_op_type(new_op, ia32_AddrModeD);
406 set_ia32_am_flavour(new_op, ia32_B);
407 set_ia32_ls_mode(new_op, get_irn_mode(val));
408 set_ia32_frame_ent(new_op, ent);
409 set_ia32_use_frame(new_op);
411 proj = new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
414 sched_add_after(sched_point, new_op);
415 sched_add_after(new_op, proj);
425 * Calls the transform functions for StackParam, Spill and Reload.
427 static void ia32_after_ra_walker(ir_node *node, void *env) {
428 ia32_code_gen_t *cg = env;
429 ir_node *new_node = NULL;
430 ia32_transform_env_t tenv;
435 tenv.block = get_nodes_block(node);
436 tenv.dbg = get_irn_dbg_info(node);
437 tenv.irg = current_ir_graph;
440 tenv.mode = get_irn_mode(node);
443 if (be_is_StackParam(node) || be_is_Reload(node)) {
444 transform_to_Load(&tenv);
446 else if (be_is_Spill(node)) {
447 transform_to_Store(&tenv);
452 * We transform StackParam, Spill and Reload here. This needs to be done before
453 * stack biasing otherwise we would miss the corrected offset for these nodes.
455 static void ia32_after_ra(void *self) {
456 ia32_code_gen_t *cg = self;
457 irg_walk_blkwise_graph(cg->irg, NULL, ia32_after_ra_walker, self);
462 * Emits the code, closes the output file and frees
463 * the code generator interface.
465 static void ia32_codegen(void *self) {
466 ia32_code_gen_t *cg = self;
467 ir_graph *irg = cg->irg;
470 if (cg->emit_decls) {
471 ia32_gen_decls(cg->out);
475 ia32_finish_irg(irg, cg);
476 dump_ir_block_graph_sched(irg, "-finished");
477 ia32_gen_routine(out, irg, cg);
481 pmap_destroy(cg->tv_ent);
482 pmap_destroy(cg->types);
484 /* de-allocate code generator */
485 del_set(cg->reg_set);
489 static void *ia32_cg_init(FILE *F, const be_irg_t *birg);
491 static const arch_code_generator_if_t ia32_code_gen_if = {
494 ia32_before_sched, /* before scheduling hook */
495 ia32_before_ra, /* before register allocation hook */
496 ia32_after_ra, /* after register allocation hook */
497 ia32_codegen /* emit && done */
501 * Initializes the code generator.
503 static void *ia32_cg_init(FILE *F, const be_irg_t *birg) {
504 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
505 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
507 cg->impl = &ia32_code_gen_if;
509 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
510 cg->mod = firm_dbg_register("firm.be.ia32.cg");
512 cg->arch_env = birg->main_env->arch_env;
513 cg->types = pmap_create();
514 cg->tv_ent = pmap_create();
519 if (isa->num_codegens > 1)
524 cur_reg_set = cg->reg_set;
526 ia32_irn_ops.cg = cg;
528 return (arch_code_generator_t *)cg;
533 /*****************************************************************
534 * ____ _ _ _____ _____
535 * | _ \ | | | | |_ _|/ ____| /\
536 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
537 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
538 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
539 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
541 *****************************************************************/
543 static ia32_isa_t ia32_isa_template = {
545 &ia32_gp_regs[REG_ESP],
546 &ia32_gp_regs[REG_EBP],
552 * Initializes the backend ISA.
554 static void *ia32_init(void) {
555 static int inited = 0;
561 isa = xcalloc(1, sizeof(*isa));
562 memcpy(isa, &ia32_isa_template, sizeof(*isa));
564 ia32_register_init(isa);
565 ia32_create_opcodes();
575 * Closes the output file and frees the ISA structure.
577 static void ia32_done(void *self) {
583 static int ia32_get_n_reg_class(const void *self) {
587 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
588 assert(i >= 0 && i < N_CLASSES && "Invalid ia32 register class requested.");
589 return &ia32_reg_classes[i];
593 * Get the register class which shall be used to store a value of a given mode.
594 * @param self The this pointer.
595 * @param mode The mode in question.
596 * @return A register class which can hold values of the given mode.
598 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
599 if (mode_is_float(mode))
600 return &ia32_reg_classes[CLASS_ia32_fp];
602 return &ia32_reg_classes[CLASS_ia32_gp];
606 * Produces the type which sits between the stack args and the locals on the stack.
607 * it will contain the return address and space to store the old base pointer.
608 * @return The Firm type modelling the ABI between type.
610 static ir_type *get_between_type(void)
612 static ir_type *between_type = NULL;
613 static entity *old_bp_ent = NULL;
616 entity *ret_addr_ent;
617 ir_type *ret_addr_type = new_type_primitive(new_id_from_str("return_addr"), mode_P);
618 ir_type *old_bp_type = new_type_primitive(new_id_from_str("bp"), mode_P);
620 between_type = new_type_class(new_id_from_str("ia32_between_type"));
621 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
622 ret_addr_ent = new_entity(between_type, new_id_from_str("ret_addr"), ret_addr_type);
624 set_entity_offset_bytes(old_bp_ent, 0);
625 set_entity_offset_bytes(ret_addr_ent, get_type_size_bytes(old_bp_type));
626 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
633 * Get the ABI restrictions for procedure calls.
634 * @param self The this pointer.
635 * @param method_type The type of the method (procedure) in question.
636 * @param abi The abi object to be modified
638 void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
639 ir_type *between_type;
642 unsigned cc = get_method_calling_convention(method_type);
643 int n = get_method_n_params(method_type);
648 const arch_register_t *reg;
649 be_abi_call_flags_t call_flags = { 0, 0, 1, 0, 1 };
651 /* get the between type and the frame pointer save entity */
652 between_type = get_between_type();
654 /* set stack parameter passing style */
655 be_abi_call_set_flags(abi, call_flags, between_type);
657 /* collect the mode for each type */
658 modes = alloca(n * sizeof(modes[0]));
660 for (i = 0; i < n; i++) {
661 tp = get_method_param_type(method_type, i);
662 modes[i] = get_type_mode(tp);
665 /* set register parameters */
666 if (cc & cc_reg_param) {
667 /* determine the number of parameters passed via registers */
668 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore, &ignore);
670 /* loop over all parameters and set the register requirements */
671 for (i = 0; i <= biggest_n; i++) {
672 reg = ia32_get_RegParam_reg(n, modes, i, cc);
673 assert(reg && "kaputt");
674 be_abi_call_param_reg(abi, i, reg);
681 /* set stack parameters */
682 for (i = stack_idx; i < n; i++) {
683 be_abi_call_param_stack(abi, i);
687 /* set return registers */
688 n = get_method_n_ress(method_type);
690 assert(n <= 2 && "more than two results not supported");
692 /* In case of 64bit returns, we will have two 32bit values */
694 tp = get_method_res_type(method_type, 0);
695 mode = get_type_mode(tp);
697 assert(!mode_is_float(mode) && "two FP results not supported");
699 tp = get_method_res_type(method_type, 1);
700 mode = get_type_mode(tp);
702 assert(!mode_is_float(mode) && "two FP results not supported");
704 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
705 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
708 tp = get_method_res_type(method_type, 0);
709 assert(is_atomic_type(tp));
710 mode = get_type_mode(tp);
712 be_abi_call_res_reg(abi, 0, mode_is_float(mode) ? &ia32_fp_regs[REG_XMM0] : &ia32_gp_regs[REG_EAX]);
717 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
718 return &ia32_irn_ops;
721 const arch_irn_handler_t ia32_irn_handler = {
725 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
726 return &ia32_irn_handler;
729 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
730 return is_ia32_irn(irn);
734 * Initializes the code generator interface.
736 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
737 return &ia32_code_gen_if;
740 list_sched_selector_t ia32_sched_selector;
743 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
745 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self) {
746 memcpy(&ia32_sched_selector, trivial_selector, sizeof(list_sched_selector_t));
747 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
748 return &ia32_sched_selector;
752 static void ia32_register_options(lc_opt_entry_t *ent)
755 #endif /* WITH_LIBCORE */
757 const arch_isa_if_t ia32_isa_if = {
759 ia32_register_options,
763 ia32_get_n_reg_class,
765 ia32_get_reg_class_for_mode,
767 ia32_get_irn_handler,
768 ia32_get_code_generator_if,
769 ia32_get_list_sched_selector