2 * This is the main ia32 firm backend driver.
3 * @author Christian Wuerdig
20 #include <libcore/lc_opts.h>
21 #include <libcore/lc_opts_enum.h>
22 #endif /* WITH_LIBCORE */
26 #include "pseudo_irg.h"
30 #include "iredges_t.h"
39 #include "../beabi.h" /* the general register allocator interface */
40 #include "../benode_t.h"
41 #include "../belower.h"
42 #include "../besched_t.h"
45 #include "../beirgmod.h"
46 #include "../be_dbgout.h"
47 #include "../beblocksched.h"
48 #include "../bemachine.h"
49 #include "../beilpsched.h"
50 #include "../bespillslots.h"
51 #include "../bemodule.h"
53 #include "bearch_ia32_t.h"
55 #include "ia32_new_nodes.h" /* ia32 nodes interface */
56 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
57 #include "gen_ia32_machine.h"
58 #include "ia32_gen_decls.h" /* interface declaration emitter */
59 #include "ia32_transform.h"
60 #include "ia32_emitter.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_optimize.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_finish.h"
66 #include "ia32_util.h"
68 #define DEBUG_MODULE "firm.be.ia32.isa"
71 static set *cur_reg_set = NULL;
73 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_graph *irg, ir_node *block);
75 static INLINE ir_node *create_const(ia32_code_gen_t *cg, ir_node **place,
76 create_const_node_func func, arch_register_t* reg)
84 block = get_irg_start_block(cg->irg);
85 res = func(NULL, cg->irg, block);
86 arch_set_irn_register(cg->arch_env, res, reg);
89 /* schedule the node if we already have a scheduled program */
90 if(sched_is_scheduled(startnode)) {
91 sched_add_before(startnode, res);
94 /* keep the node so it isn't accidently removed when unused ... */
96 be_new_Keep(arch_register_get_class(reg), cg->irg, block, 1, in);
101 /* Creates the unique per irg GP NoReg node. */
102 ir_node *ia32_new_NoReg_gp(ia32_code_gen_t *cg) {
103 return create_const(cg, &cg->noreg_gp, new_rd_ia32_NoReg_GP,
104 &ia32_gp_regs[REG_GP_NOREG]);
107 ir_node *ia32_new_NoReg_vfp(ia32_code_gen_t *cg) {
108 return create_const(cg, &cg->noreg_vfp, new_rd_ia32_NoReg_VFP,
109 &ia32_vfp_regs[REG_VFP_NOREG]);
112 ir_node *ia32_new_NoReg_xmm(ia32_code_gen_t *cg) {
113 return create_const(cg, &cg->noreg_xmm, new_rd_ia32_NoReg_XMM,
114 &ia32_xmm_regs[REG_XMM_NOREG]);
117 /* Creates the unique per irg FP NoReg node. */
118 ir_node *ia32_new_NoReg_fp(ia32_code_gen_t *cg) {
119 return USE_SSE2(cg) ? ia32_new_NoReg_xmm(cg) : ia32_new_NoReg_vfp(cg);
122 ir_node *ia32_new_Unknown_gp(ia32_code_gen_t *cg) {
123 return create_const(cg, &cg->unknown_gp, new_rd_ia32_Unknown_GP,
124 &ia32_gp_regs[REG_GP_UKNWN]);
127 ir_node *ia32_new_Unknown_vfp(ia32_code_gen_t *cg) {
128 return create_const(cg, &cg->unknown_vfp, new_rd_ia32_Unknown_VFP,
129 &ia32_vfp_regs[REG_VFP_UKNWN]);
132 ir_node *ia32_new_Unknown_xmm(ia32_code_gen_t *cg) {
133 return create_const(cg, &cg->unknown_xmm, new_rd_ia32_Unknown_XMM,
134 &ia32_xmm_regs[REG_XMM_UKNWN]);
139 * Returns gp_noreg or fp_noreg, depending in input requirements.
141 ir_node *ia32_get_admissible_noreg(ia32_code_gen_t *cg, ir_node *irn, int pos) {
142 arch_register_req_t req;
143 const arch_register_req_t *p_req;
145 p_req = arch_get_register_req(cg->arch_env, &req, irn, pos);
146 assert(p_req && "Missing register requirements");
147 if (p_req->cls == &ia32_reg_classes[CLASS_ia32_gp])
148 return ia32_new_NoReg_gp(cg);
150 return ia32_new_NoReg_fp(cg);
153 /**************************************************
156 * _ __ ___ __ _ __ _| | | ___ ___ _| |_
157 * | '__/ _ \/ _` | / _` | | |/ _ \ / __| | | _|
158 * | | | __/ (_| | | (_| | | | (_) | (__ | | |
159 * |_| \___|\__, | \__,_|_|_|\___/ \___| |_|_|
162 **************************************************/
165 * Return register requirements for an ia32 node.
166 * If the node returns a tuple (mode_T) then the proj's
167 * will be asked for this information.
169 static const arch_register_req_t *ia32_get_irn_reg_req(const void *self, arch_register_req_t *req, const ir_node *irn, int pos) {
170 const ia32_irn_ops_t *ops = self;
171 const ia32_register_req_t *irn_req;
172 long node_pos = pos == -1 ? 0 : pos;
173 ir_mode *mode = is_Block(irn) ? NULL : get_irn_mode(irn);
174 FIRM_DBG_REGISTER(firm_dbg_module_t *mod, DEBUG_MODULE);
176 if (is_Block(irn) || mode == mode_X) {
177 DBG((mod, LEVEL_1, "ignoring Block, mode_M, mode_X node %+F\n", irn));
181 if (mode == mode_T && pos < 0) {
182 DBG((mod, LEVEL_1, "ignoring request OUT requirements for node %+F\n", irn));
186 DBG((mod, LEVEL_1, "get requirements at pos %d for %+F ... ", pos, irn));
193 DBG((mod, LEVEL_1, "ignoring request IN requirements for node %+F\n", irn));
197 node_pos = (pos == -1) ? get_Proj_proj(irn) : pos;
198 irn = skip_Proj_const(irn);
200 DB((mod, LEVEL_1, "skipping Proj, going to %+F at pos %d ... ", irn, node_pos));
203 if (is_ia32_irn(irn)) {
204 irn_req = (pos >= 0) ? get_ia32_in_req(irn, pos) : get_ia32_out_req(irn, node_pos);
205 if (irn_req == NULL) {
206 /* no requirements */
210 DB((mod, LEVEL_1, "returning reqs for %+F at pos %d\n", irn, pos));
212 memcpy(req, &(irn_req->req), sizeof(*req));
214 if (arch_register_req_is(&(irn_req->req), should_be_same)) {
215 assert(irn_req->same_pos >= 0 && "should be same constraint for in -> out NYI");
216 req->other_same = get_irn_n(irn, irn_req->same_pos);
219 if (arch_register_req_is(&(irn_req->req), should_be_different)) {
220 assert(irn_req->different_pos >= 0 && "should be different constraint for in -> out NYI");
221 req->other_different = get_irn_n(irn, irn_req->different_pos);
225 /* treat Unknowns like Const with default requirements */
226 if (is_Unknown(irn)) {
227 DB((mod, LEVEL_1, "returning UKNWN reqs for %+F\n", irn));
228 if (mode_is_float(mode)) {
229 if (USE_SSE2(ops->cg))
230 memcpy(req, &(ia32_default_req_ia32_xmm_xmm_UKNWN), sizeof(*req));
232 memcpy(req, &(ia32_default_req_ia32_vfp_vfp_UKNWN), sizeof(*req));
234 else if (mode_is_int(mode) || mode_is_reference(mode))
235 memcpy(req, &(ia32_default_req_ia32_gp_gp_UKNWN), sizeof(*req));
236 else if (mode == mode_T || mode == mode_M) {
237 DBG((mod, LEVEL_1, "ignoring Unknown node %+F\n", irn));
241 assert(0 && "unsupported Unknown-Mode");
244 DB((mod, LEVEL_1, "returning NULL for %+F (not ia32)\n", irn));
252 static void ia32_set_irn_reg(const void *self, ir_node *irn, const arch_register_t *reg) {
254 const ia32_irn_ops_t *ops = self;
256 if (get_irn_mode(irn) == mode_X) {
260 DBG((ops->cg->mod, LEVEL_1, "ia32 assigned register %s to node %+F\n", reg->name, irn));
263 pos = get_Proj_proj(irn);
264 irn = skip_Proj(irn);
267 if (is_ia32_irn(irn)) {
268 const arch_register_t **slots;
270 slots = get_ia32_slots(irn);
274 ia32_set_firm_reg(irn, reg, cur_reg_set);
278 static const arch_register_t *ia32_get_irn_reg(const void *self, const ir_node *irn) {
280 const arch_register_t *reg = NULL;
284 if (get_irn_mode(irn) == mode_X) {
288 pos = get_Proj_proj(irn);
289 irn = skip_Proj_const(irn);
292 if (is_ia32_irn(irn)) {
293 const arch_register_t **slots;
294 slots = get_ia32_slots(irn);
298 reg = ia32_get_firm_reg(irn, cur_reg_set);
304 static arch_irn_class_t ia32_classify(const void *self, const ir_node *irn) {
305 arch_irn_class_t classification = arch_irn_class_normal;
307 irn = skip_Proj_const(irn);
310 classification |= arch_irn_class_branch;
312 if (! is_ia32_irn(irn))
313 return classification & ~arch_irn_class_normal;
315 if (is_ia32_Cnst(irn))
316 classification |= arch_irn_class_const;
319 classification |= arch_irn_class_load;
321 if (is_ia32_St(irn) || is_ia32_Store8Bit(irn))
322 classification |= arch_irn_class_store;
324 if (is_ia32_got_reload(irn))
325 classification |= arch_irn_class_reload;
327 return classification;
330 static arch_irn_flags_t ia32_get_flags(const void *self, const ir_node *irn) {
331 arch_irn_flags_t flags = arch_irn_flags_none;
334 return arch_irn_flags_ignore;
336 if(is_Proj(irn) && mode_is_datab(get_irn_mode(irn))) {
337 ir_node *pred = get_Proj_pred(irn);
339 if(is_ia32_irn(pred)) {
340 flags = get_ia32_out_flags(pred, get_Proj_proj(irn));
346 if (is_ia32_irn(irn)) {
347 flags |= get_ia32_flags(irn);
354 * The IA32 ABI callback object.
357 be_abi_call_flags_bits_t flags; /**< The call flags. */
358 const arch_isa_t *isa; /**< The ISA handle. */
359 const arch_env_t *aenv; /**< The architecture environment. */
360 ir_graph *irg; /**< The associated graph. */
363 static ir_entity *ia32_get_frame_entity(const void *self, const ir_node *irn) {
364 return is_ia32_irn(irn) ? get_ia32_frame_ent(irn) : NULL;
367 static void ia32_set_frame_entity(const void *self, ir_node *irn, ir_entity *ent) {
368 set_ia32_frame_ent(irn, ent);
371 static void ia32_set_frame_offset(const void *self, ir_node *irn, int bias) {
372 const ia32_irn_ops_t *ops = self;
374 if (get_ia32_frame_ent(irn)) {
375 ia32_am_flavour_t am_flav;
377 if (is_ia32_Pop(irn)) {
378 int omit_fp = be_abi_omit_fp(ops->cg->birg->abi);
380 /* Pop nodes modify the stack pointer before calculating the destination
381 * address, so fix this here
387 DBG((ops->cg->mod, LEVEL_1, "stack biased %+F with %d\n", irn, bias));
389 am_flav = get_ia32_am_flavour(irn);
391 set_ia32_am_flavour(irn, am_flav);
393 add_ia32_am_offs_int(irn, bias);
397 static int ia32_get_sp_bias(const void *self, const ir_node *irn) {
399 long proj = get_Proj_proj(irn);
400 ir_node *pred = get_Proj_pred(irn);
402 if (is_ia32_Push(pred) && proj == pn_ia32_Push_stack)
404 if (is_ia32_Pop(pred) && proj == pn_ia32_Pop_stack)
412 * Put all registers which are saved by the prologue/epilogue in a set.
414 * @param self The callback object.
415 * @param s The result set.
417 static void ia32_abi_dont_save_regs(void *self, pset *s)
419 ia32_abi_env_t *env = self;
420 if(env->flags.try_omit_fp)
421 pset_insert_ptr(s, env->isa->bp);
425 * Generate the routine prologue.
427 * @param self The callback object.
428 * @param mem A pointer to the mem node. Update this if you define new memory.
429 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
431 * @return The register which shall be used as a stack frame base.
433 * All nodes which define registers in @p reg_map must keep @p reg_map current.
435 static const arch_register_t *ia32_abi_prologue(void *self, ir_node **mem, pmap *reg_map)
437 ia32_abi_env_t *env = self;
438 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
439 ia32_code_gen_t *cg = isa->cg;
441 if (! env->flags.try_omit_fp) {
442 ir_node *bl = get_irg_start_block(env->irg);
443 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
444 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
445 ir_node *noreg = ia32_new_NoReg_gp(cg);
449 push = new_rd_ia32_Push(NULL, env->irg, bl, noreg, noreg, curr_bp, curr_sp, *mem);
450 curr_sp = new_r_Proj(env->irg, bl, push, get_irn_mode(curr_sp), pn_ia32_Push_stack);
451 *mem = new_r_Proj(env->irg, bl, push, mode_M, pn_ia32_Push_M);
453 /* the push must have SP out register */
454 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
455 set_ia32_flags(push, arch_irn_flags_ignore);
457 /* move esp to ebp */
458 curr_bp = be_new_Copy(env->isa->bp->reg_class, env->irg, bl, curr_sp);
459 be_set_constr_single_reg(curr_bp, BE_OUT_POS(0), env->isa->bp);
460 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
461 be_node_set_flags(curr_bp, BE_OUT_POS(0), arch_irn_flags_ignore);
463 /* beware: the copy must be done before any other sp use */
464 curr_sp = be_new_CopyKeep_single(env->isa->sp->reg_class, env->irg, bl, curr_sp, curr_bp, get_irn_mode(curr_sp));
465 be_set_constr_single_reg(curr_sp, BE_OUT_POS(0), env->isa->sp);
466 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
467 be_node_set_flags(curr_sp, BE_OUT_POS(0), arch_irn_flags_ignore);
469 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
470 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
479 * Generate the routine epilogue.
480 * @param self The callback object.
481 * @param bl The block for the epilog
482 * @param mem A pointer to the mem node. Update this if you define new memory.
483 * @param reg_map A map mapping all callee_save/ignore/parameter registers to their defining nodes.
484 * @return The register which shall be used as a stack frame base.
486 * All nodes which define registers in @p reg_map must keep @p reg_map current.
488 static void ia32_abi_epilogue(void *self, ir_node *bl, ir_node **mem, pmap *reg_map)
490 ia32_abi_env_t *env = self;
491 ir_node *curr_sp = be_abi_reg_map_get(reg_map, env->isa->sp);
492 ir_node *curr_bp = be_abi_reg_map_get(reg_map, env->isa->bp);
494 if (env->flags.try_omit_fp) {
495 /* simply remove the stack frame here */
496 curr_sp = be_new_IncSP(env->isa->sp, env->irg, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK);
497 add_irn_dep(curr_sp, *mem);
499 const ia32_isa_t *isa = (ia32_isa_t *)env->isa;
500 ia32_code_gen_t *cg = isa->cg;
501 ir_mode *mode_bp = env->isa->bp->reg_class->mode;
503 /* gcc always emits a leave at the end of a routine */
504 if (1 || ARCH_AMD(isa->opt_arch)) {
508 leave = new_rd_ia32_Leave(NULL, env->irg, bl, curr_sp, curr_bp);
509 set_ia32_flags(leave, arch_irn_flags_ignore);
510 curr_bp = new_r_Proj(current_ir_graph, bl, leave, mode_bp, pn_ia32_Leave_frame);
511 curr_sp = new_r_Proj(current_ir_graph, bl, leave, get_irn_mode(curr_sp), pn_ia32_Leave_stack);
513 ir_node *noreg = ia32_new_NoReg_gp(cg);
516 /* copy ebp to esp */
517 curr_sp = be_new_SetSP(env->isa->sp, env->irg, bl, curr_sp, curr_bp, *mem);
520 pop = new_rd_ia32_Pop(NULL, env->irg, bl, noreg, noreg, curr_sp, *mem);
521 set_ia32_flags(pop, arch_irn_flags_ignore);
522 curr_bp = new_r_Proj(current_ir_graph, bl, pop, mode_bp, pn_ia32_Pop_res);
523 curr_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(curr_sp), pn_ia32_Pop_stack);
525 *mem = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
527 arch_set_irn_register(env->aenv, curr_sp, env->isa->sp);
528 arch_set_irn_register(env->aenv, curr_bp, env->isa->bp);
531 be_abi_reg_map_set(reg_map, env->isa->sp, curr_sp);
532 be_abi_reg_map_set(reg_map, env->isa->bp, curr_bp);
536 * Initialize the callback object.
537 * @param call The call object.
538 * @param aenv The architecture environment.
539 * @param irg The graph with the method.
540 * @return Some pointer. This pointer is passed to all other callback functions as self object.
542 static void *ia32_abi_init(const be_abi_call_t *call, const arch_env_t *aenv, ir_graph *irg)
544 ia32_abi_env_t *env = xmalloc(sizeof(env[0]));
545 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
546 env->flags = fl.bits;
549 env->isa = aenv->isa;
554 * Destroy the callback object.
555 * @param self The callback object.
557 static void ia32_abi_done(void *self) {
562 * Produces the type which sits between the stack args and the locals on the stack.
563 * it will contain the return address and space to store the old base pointer.
564 * @return The Firm type modeling the ABI between type.
566 static ir_type *ia32_abi_get_between_type(void *self)
568 #define IDENT(s) new_id_from_chars(s, sizeof(s)-1)
569 static ir_type *omit_fp_between_type = NULL;
570 static ir_type *between_type = NULL;
572 ia32_abi_env_t *env = self;
574 if (! between_type) {
575 ir_entity *old_bp_ent;
576 ir_entity *ret_addr_ent;
577 ir_entity *omit_fp_ret_addr_ent;
579 ir_type *old_bp_type = new_type_primitive(IDENT("bp"), mode_Iu);
580 ir_type *ret_addr_type = new_type_primitive(IDENT("return_addr"), mode_Iu);
582 between_type = new_type_struct(IDENT("ia32_between_type"));
583 old_bp_ent = new_entity(between_type, IDENT("old_bp"), old_bp_type);
584 ret_addr_ent = new_entity(between_type, IDENT("ret_addr"), ret_addr_type);
586 set_entity_offset(old_bp_ent, 0);
587 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
588 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
589 set_type_state(between_type, layout_fixed);
591 omit_fp_between_type = new_type_struct(IDENT("ia32_between_type_omit_fp"));
592 omit_fp_ret_addr_ent = new_entity(omit_fp_between_type, IDENT("ret_addr"), ret_addr_type);
594 set_entity_offset(omit_fp_ret_addr_ent, 0);
595 set_type_size_bytes(omit_fp_between_type, get_type_size_bytes(ret_addr_type));
596 set_type_state(omit_fp_between_type, layout_fixed);
599 return env->flags.try_omit_fp ? omit_fp_between_type : between_type;
604 * Get the estimated cycle count for @p irn.
606 * @param self The this pointer.
607 * @param irn The node.
609 * @return The estimated cycle count for this operation
611 static int ia32_get_op_estimated_cost(const void *self, const ir_node *irn)
614 ia32_op_type_t op_tp;
615 const ia32_irn_ops_t *ops = self;
619 if (!is_ia32_irn(irn))
622 assert(is_ia32_irn(irn));
624 cost = get_ia32_latency(irn);
625 op_tp = get_ia32_op_type(irn);
627 if (is_ia32_CopyB(irn)) {
629 if (ARCH_INTEL(ops->cg->arch))
632 else if (is_ia32_CopyB_i(irn)) {
633 int size = get_tarval_long(get_ia32_Immop_tarval(irn));
634 cost = 20 + (int)ceil((4/3) * size);
635 if (ARCH_INTEL(ops->cg->arch))
638 /* in case of address mode operations add additional cycles */
639 else if (op_tp == ia32_AddrModeD || op_tp == ia32_AddrModeS) {
641 In case of stack access add 5 cycles (we assume stack is in cache),
642 other memory operations cost 20 cycles.
644 cost += is_ia32_use_frame(irn) ? 5 : 20;
651 * Returns the inverse operation if @p irn, recalculating the argument at position @p i.
653 * @param irn The original operation
654 * @param i Index of the argument we want the inverse operation to yield
655 * @param inverse struct to be filled with the resulting inverse op
656 * @param obstack The obstack to use for allocation of the returned nodes array
657 * @return The inverse operation or NULL if operation invertible
659 static arch_inverse_t *ia32_get_inverse(const void *self, const ir_node *irn, int i, arch_inverse_t *inverse, struct obstack *obst) {
663 ir_node *block, *noreg, *nomem;
666 /* we cannot invert non-ia32 irns */
667 if (! is_ia32_irn(irn))
670 /* operand must always be a real operand (not base, index or mem) */
671 if (i != 2 && i != 3)
674 /* we don't invert address mode operations */
675 if (get_ia32_op_type(irn) != ia32_Normal)
678 irg = get_irn_irg(irn);
679 block = get_nodes_block(irn);
680 mode = get_irn_mode(irn);
681 irn_mode = get_irn_mode(irn);
682 noreg = get_irn_n(irn, 0);
683 nomem = new_r_NoMem(irg);
684 dbg = get_irn_dbg_info(irn);
686 /* initialize structure */
687 inverse->nodes = obstack_alloc(obst, 2 * sizeof(inverse->nodes[0]));
691 switch (get_ia32_irn_opcode(irn)) {
693 if (get_ia32_immop_type(irn) == ia32_ImmConst) {
694 /* we have an add with a const here */
695 /* invers == add with negated const */
696 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
698 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
699 set_ia32_Immop_tarval(inverse->nodes[0], tarval_neg(get_ia32_Immop_tarval(irn)));
700 set_ia32_commutative(inverse->nodes[0]);
702 else if (get_ia32_immop_type(irn) == ia32_ImmSymConst) {
703 /* we have an add with a symconst here */
704 /* invers == sub with const */
705 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
707 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
710 /* normal add: inverse == sub */
711 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, i ^ 1), nomem);
716 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
717 /* we have a sub with a const/symconst here */
718 /* invers == add with this const */
719 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
720 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
721 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
726 inverse->nodes[0] = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, (ir_node*) irn, get_irn_n(irn, 3), nomem);
729 inverse->nodes[0] = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, get_irn_n(irn, 2), (ir_node*) irn, nomem);
735 if (get_ia32_immop_type(irn) != ia32_ImmNone) {
736 /* xor with const: inverse = xor */
737 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, get_irn_n(irn, i), noreg, nomem);
738 inverse->costs += (get_ia32_immop_type(irn) == ia32_ImmSymConst) ? 5 : 1;
739 copy_ia32_Immop_attr(inverse->nodes[0], (ir_node *)irn);
743 inverse->nodes[0] = new_rd_ia32_Xor(dbg, irg, block, noreg, noreg, (ir_node *) irn, get_irn_n(irn, i), nomem);
748 inverse->nodes[0] = new_rd_ia32_Not(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
753 inverse->nodes[0] = new_rd_ia32_Neg(dbg, irg, block, noreg, noreg, (ir_node*) irn, nomem);
758 /* inverse operation not supported */
765 static ir_mode *get_spill_mode_mode(const ir_mode *mode)
767 if(mode_is_float(mode))
774 * Get the mode that should be used for spilling value node
776 static ir_mode *get_spill_mode(const ir_node *node)
778 ir_mode *mode = get_irn_mode(node);
779 return get_spill_mode_mode(mode);
783 * Checks wether an addressmode reload for a node with mode mode is compatible
784 * with a spillslot of mode spill_mode
786 static int ia32_is_spillmode_compatible(const ir_mode *mode, const ir_mode *spillmode)
788 if(mode_is_float(mode)) {
789 return mode == spillmode;
796 * Check if irn can load it's operand at position i from memory (source addressmode).
797 * @param self Pointer to irn ops itself
798 * @param irn The irn to be checked
799 * @param i The operands position
800 * @return Non-Zero if operand can be loaded
802 static int ia32_possible_memory_operand(const void *self, const ir_node *irn, unsigned int i) {
803 ir_node *op = get_irn_n(irn, i);
804 const ir_mode *mode = get_irn_mode(op);
805 const ir_mode *spillmode = get_spill_mode(op);
807 if (! is_ia32_irn(irn) || /* must be an ia32 irn */
808 get_irn_arity(irn) != 5 || /* must be a binary operation */
809 get_ia32_op_type(irn) != ia32_Normal || /* must not already be a addressmode irn */
810 ! (get_ia32_am_support(irn) & ia32_am_Source) || /* must be capable of source addressmode */
811 ! ia32_is_spillmode_compatible(mode, spillmode) ||
812 (i != 2 && i != 3) || /* a "real" operand position must be requested */
813 (i == 2 && ! is_ia32_commutative(irn)) || /* if first operand requested irn must be commutative */
814 is_ia32_use_frame(irn)) /* must not already use frame */
820 static void ia32_perform_memory_operand(const void *self, ir_node *irn, ir_node *spill, unsigned int i) {
821 const ia32_irn_ops_t *ops = self;
822 ia32_code_gen_t *cg = ops->cg;
824 assert(ia32_possible_memory_operand(self, irn, i) && "Cannot perform memory operand change");
827 ir_node *tmp = get_irn_n(irn, 3);
828 set_irn_n(irn, 3, get_irn_n(irn, 2));
829 set_irn_n(irn, 2, tmp);
832 set_ia32_am_support(irn, ia32_am_Source);
833 set_ia32_op_type(irn, ia32_AddrModeS);
834 set_ia32_am_flavour(irn, ia32_B);
835 set_ia32_ls_mode(irn, get_irn_mode(get_irn_n(irn, i)));
836 set_ia32_use_frame(irn);
837 set_ia32_got_reload(irn);
839 set_irn_n(irn, 0, get_irg_frame(get_irn_irg(irn)));
840 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
841 set_irn_n(irn, 4, spill);
843 //FIXME DBG_OPT_AM_S(reload, irn);
846 static const be_abi_callbacks_t ia32_abi_callbacks = {
849 ia32_abi_get_between_type,
850 ia32_abi_dont_save_regs,
855 /* fill register allocator interface */
857 static const arch_irn_ops_if_t ia32_irn_ops_if = {
858 ia32_get_irn_reg_req,
863 ia32_get_frame_entity,
864 ia32_set_frame_entity,
865 ia32_set_frame_offset,
868 ia32_get_op_estimated_cost,
869 ia32_possible_memory_operand,
870 ia32_perform_memory_operand,
873 ia32_irn_ops_t ia32_irn_ops = {
880 /**************************************************
883 * ___ ___ __| | ___ __ _ ___ _ __ _| |_
884 * / __/ _ \ / _` |/ _ \/ _` |/ _ \ '_ \ | | _|
885 * | (_| (_) | (_| | __/ (_| | __/ | | | | | |
886 * \___\___/ \__,_|\___|\__, |\___|_| |_| |_|_|
889 **************************************************/
892 * Transforms the standard firm graph into
895 static void ia32_prepare_graph(void *self) {
896 ia32_code_gen_t *cg = self;
897 DEBUG_ONLY(firm_dbg_module_t *old_mod = cg->mod;)
899 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.transform");
901 /* 1st: transform psi condition trees */
902 ia32_pre_transform_phase(cg);
904 /* 2nd: transform all remaining nodes */
905 ia32_transform_graph(cg);
906 // Matze: disabled for now. Because after transformation start block has no
907 // self-loop anymore so it might be merged with its successor block. This
908 // will bring several nodes to the startblock which sometimes get scheduled
909 // before the initial IncSP/Barrier
910 //local_optimize_graph(cg->irg);
913 be_dump(cg->irg, "-transformed", dump_ir_block_graph_sched);
915 /* 3rd: optimize address mode */
916 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.am");
917 ia32_optimize_addressmode(cg);
920 be_dump(cg->irg, "-am", dump_ir_block_graph_sched);
922 DEBUG_ONLY(cg->mod = old_mod;)
926 * Dummy functions for hooks we don't need but which must be filled.
928 static void ia32_before_sched(void *self) {
931 static void remove_unused_nodes(ir_node *irn, bitset_t *already_visited) {
934 ir_node *mem_proj = NULL;
939 mode = get_irn_mode(irn);
941 /* check if we already saw this node or the node has more than one user */
942 if (bitset_contains_irn(already_visited, irn) || get_irn_n_edges(irn) > 1) {
946 /* mark irn visited */
947 bitset_add_irn(already_visited, irn);
949 /* non-Tuple nodes with one user: ok, return */
950 if (get_irn_n_edges(irn) >= 1 && mode != mode_T) {
954 /* tuple node has one user which is not the mem proj-> ok */
955 if (mode == mode_T && get_irn_n_edges(irn) == 1) {
956 mem_proj = ia32_get_proj_for_mode(irn, mode_M);
957 if (mem_proj == NULL) {
962 arity = get_irn_arity(irn);
963 for (i = 0; i < arity; ++i) {
964 ir_node *pred = get_irn_n(irn, i);
966 /* do not follow memory edges or we will accidentally remove stores */
967 if (get_irn_mode(pred) == mode_M) {
968 if(mem_proj != NULL) {
969 edges_reroute(mem_proj, pred, get_irn_irg(mem_proj));
975 set_irn_n(irn, i, new_Bad());
978 The current node is about to be removed: if the predecessor
979 has only this node as user, it need to be removed as well.
981 if (get_irn_n_edges(pred) <= 1)
982 remove_unused_nodes(pred, already_visited);
985 // we need to set the presd to Bad again to also get the memory edges
986 arity = get_irn_arity(irn);
987 for (i = 0; i < arity; ++i) {
988 set_irn_n(irn, i, new_Bad());
991 if (sched_is_scheduled(irn)) {
996 static void remove_unused_loads_walker(ir_node *irn, void *env) {
997 bitset_t *already_visited = env;
998 if (is_ia32_Ld(irn) && ! bitset_contains_irn(already_visited, irn))
999 remove_unused_nodes(irn, env);
1003 * Called before the register allocator.
1004 * Calculate a block schedule here. We need it for the x87
1005 * simulator and the emitter.
1007 static void ia32_before_ra(void *self) {
1008 ia32_code_gen_t *cg = self;
1009 bitset_t *already_visited = bitset_irg_alloca(cg->irg);
1012 Handle special case:
1013 There are sometimes unused loads, only pinned by memory.
1014 We need to remove those Loads and all other nodes which won't be used
1015 after removing the Load from schedule.
1017 irg_walk_graph(cg->irg, NULL, remove_unused_loads_walker, already_visited);
1022 * Transforms a be_Reload into a ia32 Load.
1024 static void transform_to_Load(ia32_code_gen_t *cg, ir_node *node) {
1025 ir_graph *irg = get_irn_irg(node);
1026 dbg_info *dbg = get_irn_dbg_info(node);
1027 ir_node *block = get_nodes_block(node);
1028 ir_entity *ent = be_get_frame_entity(node);
1029 ir_mode *mode = get_irn_mode(node);
1030 ir_mode *spillmode = get_spill_mode(node);
1031 ir_node *noreg = ia32_new_NoReg_gp(cg);
1032 ir_node *sched_point = NULL;
1033 ir_node *ptr = get_irg_frame(irg);
1034 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
1035 ir_node *new_op, *proj;
1036 const arch_register_t *reg;
1038 if (sched_is_scheduled(node)) {
1039 sched_point = sched_prev(node);
1042 if (mode_is_float(spillmode)) {
1044 new_op = new_rd_ia32_xLoad(dbg, irg, block, ptr, noreg, mem);
1046 new_op = new_rd_ia32_vfld(dbg, irg, block, ptr, noreg, mem);
1049 new_op = new_rd_ia32_Load(dbg, irg, block, ptr, noreg, mem);
1051 set_ia32_am_support(new_op, ia32_am_Source);
1052 set_ia32_op_type(new_op, ia32_AddrModeS);
1053 set_ia32_am_flavour(new_op, ia32_B);
1054 set_ia32_ls_mode(new_op, spillmode);
1055 set_ia32_frame_ent(new_op, ent);
1056 set_ia32_use_frame(new_op);
1058 DBG_OPT_RELOAD2LD(node, new_op);
1060 proj = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Load_res);
1063 sched_add_after(sched_point, new_op);
1064 sched_add_after(new_op, proj);
1069 /* copy the register from the old node to the new Load */
1070 reg = arch_get_irn_register(cg->arch_env, node);
1071 arch_set_irn_register(cg->arch_env, new_op, reg);
1073 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1075 exchange(node, proj);
1079 * Transforms a be_Spill node into a ia32 Store.
1081 static void transform_to_Store(ia32_code_gen_t *cg, ir_node *node) {
1082 ir_graph *irg = get_irn_irg(node);
1083 dbg_info *dbg = get_irn_dbg_info(node);
1084 ir_node *block = get_nodes_block(node);
1085 ir_entity *ent = be_get_frame_entity(node);
1086 const ir_node *spillval = get_irn_n(node, be_pos_Spill_val);
1087 ir_mode *mode = get_spill_mode(spillval);
1088 ir_node *noreg = ia32_new_NoReg_gp(cg);
1089 ir_node *nomem = new_rd_NoMem(irg);
1090 ir_node *ptr = get_irg_frame(irg);
1091 ir_node *val = get_irn_n(node, be_pos_Spill_val);
1093 ir_node *sched_point = NULL;
1095 if (sched_is_scheduled(node)) {
1096 sched_point = sched_prev(node);
1099 if (mode_is_float(mode)) {
1101 store = new_rd_ia32_xStore(dbg, irg, block, ptr, noreg, val, nomem);
1103 store = new_rd_ia32_vfst(dbg, irg, block, ptr, noreg, val, nomem);
1105 else if (get_mode_size_bits(mode) == 8) {
1106 store = new_rd_ia32_Store8Bit(dbg, irg, block, ptr, noreg, val, nomem);
1109 store = new_rd_ia32_Store(dbg, irg, block, ptr, noreg, val, nomem);
1112 set_ia32_am_support(store, ia32_am_Dest);
1113 set_ia32_op_type(store, ia32_AddrModeD);
1114 set_ia32_am_flavour(store, ia32_B);
1115 set_ia32_ls_mode(store, mode);
1116 set_ia32_frame_ent(store, ent);
1117 set_ia32_use_frame(store);
1119 DBG_OPT_SPILL2ST(node, store);
1120 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(cg, node));
1123 sched_add_after(sched_point, store);
1127 exchange(node, store);
1130 static ir_node *create_push(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_node *mem, ir_entity *ent) {
1131 ir_graph *irg = get_irn_irg(node);
1132 dbg_info *dbg = get_irn_dbg_info(node);
1133 ir_node *block = get_nodes_block(node);
1134 ir_node *noreg = ia32_new_NoReg_gp(cg);
1135 ir_node *frame = get_irg_frame(irg);
1137 ir_node *push = new_rd_ia32_Push(dbg, irg, block, frame, noreg, noreg, sp, mem);
1139 set_ia32_frame_ent(push, ent);
1140 set_ia32_use_frame(push);
1141 set_ia32_op_type(push, ia32_AddrModeS);
1142 set_ia32_am_flavour(push, ia32_B);
1143 set_ia32_ls_mode(push, mode_Is);
1145 sched_add_before(schedpoint, push);
1149 static ir_node *create_pop(ia32_code_gen_t *cg, ir_node *node, ir_node *schedpoint, ir_node *sp, ir_entity *ent) {
1150 ir_graph *irg = get_irn_irg(node);
1151 dbg_info *dbg = get_irn_dbg_info(node);
1152 ir_node *block = get_nodes_block(node);
1153 ir_node *noreg = ia32_new_NoReg_gp(cg);
1154 ir_node *frame = get_irg_frame(irg);
1156 ir_node *pop = new_rd_ia32_Pop(dbg, irg, block, frame, noreg, sp, new_NoMem());
1158 set_ia32_frame_ent(pop, ent);
1159 set_ia32_use_frame(pop);
1160 set_ia32_op_type(pop, ia32_AddrModeD);
1161 set_ia32_am_flavour(pop, ia32_am_OB);
1162 set_ia32_ls_mode(pop, mode_Is);
1164 sched_add_before(schedpoint, pop);
1169 static ir_node* create_spproj(ia32_code_gen_t *cg, ir_node *node, ir_node *pred, int pos, ir_node *schedpoint) {
1170 ir_graph *irg = get_irn_irg(node);
1171 dbg_info *dbg = get_irn_dbg_info(node);
1172 ir_node *block = get_nodes_block(node);
1173 ir_mode *spmode = mode_Iu;
1174 const arch_register_t *spreg = &ia32_gp_regs[REG_ESP];
1177 sp = new_rd_Proj(dbg, irg, block, pred, spmode, pos);
1178 arch_set_irn_register(cg->arch_env, sp, spreg);
1179 sched_add_before(schedpoint, sp);
1185 * Transform memperm, currently we do this the ugly way and produce
1186 * push/pop into/from memory cascades. This is possible without using
1189 static void transform_MemPerm(ia32_code_gen_t *cg, ir_node *node) {
1190 ir_graph *irg = get_irn_irg(node);
1191 ir_node *block = get_nodes_block(node);
1195 ir_node *sp = be_abi_get_ignore_irn(cg->birg->abi, &ia32_gp_regs[REG_ESP]);
1196 const ir_edge_t *edge;
1197 const ir_edge_t *next;
1200 arity = be_get_MemPerm_entity_arity(node);
1201 pops = alloca(arity * sizeof(pops[0]));
1204 for(i = 0; i < arity; ++i) {
1205 ir_entity *ent = be_get_MemPerm_in_entity(node, i);
1206 ir_type *enttype = get_entity_type(ent);
1207 int entbits = get_type_size_bits(enttype);
1208 ir_node *mem = get_irn_n(node, i + 1);
1211 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1213 push = create_push(cg, node, node, sp, mem, ent);
1214 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1216 // add another push after the first one
1217 push = create_push(cg, node, node, sp, mem, ent);
1218 add_ia32_am_offs_int(push, 4);
1219 sp = create_spproj(cg, node, push, pn_ia32_Push_stack, node);
1222 set_irn_n(node, i, new_Bad());
1226 for(i = arity - 1; i >= 0; --i) {
1227 ir_entity *ent = be_get_MemPerm_out_entity(node, i);
1228 ir_type *enttype = get_entity_type(ent);
1229 int entbits = get_type_size_bits(enttype);
1233 assert( (entbits == 32 || entbits == 64) && "spillslot on x86 should be 32 or 64 bit");
1235 pop = create_pop(cg, node, node, sp, ent);
1236 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1238 add_ia32_am_offs_int(pop, 4);
1240 // add another pop after the first one
1241 pop = create_pop(cg, node, node, sp, ent);
1242 sp = create_spproj(cg, node, pop, pn_ia32_Pop_stack, node);
1249 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
1250 sched_add_before(node, keep);
1252 // exchange memprojs
1253 foreach_out_edge_safe(node, edge, next) {
1254 ir_node *proj = get_edge_src_irn(edge);
1255 int p = get_Proj_proj(proj);
1259 set_Proj_pred(proj, pops[p]);
1260 set_Proj_proj(proj, 3);
1264 arity = get_irn_arity(node);
1265 for(i = 0; i < arity; ++i) {
1266 set_irn_n(node, i, new_Bad());
1272 * Block-Walker: Calls the transform functions Spill and Reload.
1274 static void ia32_after_ra_walker(ir_node *block, void *env) {
1275 ir_node *node, *prev;
1276 ia32_code_gen_t *cg = env;
1278 /* beware: the schedule is changed here */
1279 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
1280 prev = sched_prev(node);
1282 if (be_is_Reload(node)) {
1283 transform_to_Load(cg, node);
1284 } else if (be_is_Spill(node)) {
1285 transform_to_Store(cg, node);
1286 } else if(be_is_MemPerm(node)) {
1287 transform_MemPerm(cg, node);
1293 * Collects nodes that need frame entities assigned.
1295 static void ia32_collect_frame_entity_nodes(ir_node *node, void *data)
1297 be_fec_env_t *env = data;
1299 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
1300 const ir_mode *mode = get_spill_mode_mode(get_irn_mode(node));
1301 int align = get_mode_size_bytes(mode);
1302 be_node_needs_frame_entity(env, node, mode, align);
1303 } else if(is_ia32_irn(node) && get_ia32_frame_ent(node) == NULL
1304 && is_ia32_use_frame(node)) {
1305 if (is_ia32_got_reload(node) || is_ia32_Load(node)) {
1306 const ir_mode *mode = get_ia32_ls_mode(node);
1307 int align = get_mode_size_bytes(mode);
1308 be_node_needs_frame_entity(env, node, mode, align);
1309 } else if (is_ia32_vfild(node)) {
1310 const ir_mode *mode = get_ia32_ls_mode(node);
1312 be_node_needs_frame_entity(env, node, mode, align);
1313 } else if (is_ia32_SetST0(node)) {
1314 const ir_mode *mode = get_ia32_ls_mode(node);
1316 be_node_needs_frame_entity(env, node, mode, align);
1319 if(!is_ia32_Store(node)
1320 && !is_ia32_xStore(node)
1321 && !is_ia32_xStoreSimple(node)
1322 && !is_ia32_vfist(node)) {
1331 * We transform Spill and Reload here. This needs to be done before
1332 * stack biasing otherwise we would miss the corrected offset for these nodes.
1334 static void ia32_after_ra(void *self) {
1335 ia32_code_gen_t *cg = self;
1336 ir_graph *irg = cg->irg;
1337 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(cg->birg);
1339 /* create and coalesce frame entities */
1340 irg_walk_graph(irg, NULL, ia32_collect_frame_entity_nodes, fec_env);
1341 be_assign_entities(fec_env);
1342 be_free_frame_entity_coalescer(fec_env);
1344 irg_block_walk_graph(irg, NULL, ia32_after_ra_walker, cg);
1346 ia32_finish_irg(irg, cg);
1350 * Last touchups for the graph before emit: x87 simulation to replace the
1351 * virtual with real x87 instructions, creating a block schedule and peephole
1354 static void ia32_finish(void *self) {
1355 ia32_code_gen_t *cg = self;
1356 ir_graph *irg = cg->irg;
1358 /* if we do x87 code generation, rewrite all the virtual instructions and registers */
1359 if (cg->used_fp == fp_x87 || cg->force_sim) {
1360 x87_simulate_graph(cg->arch_env, cg->birg);
1363 /* create block schedule, this also removes empty blocks which might
1364 * produce critical edges */
1365 cg->blk_sched = be_create_block_schedule(irg, cg->birg->exec_freq);
1367 /* do peephole optimisations */
1368 ia32_peephole_optimization(irg, cg);
1372 * Emits the code, closes the output file and frees
1373 * the code generator interface.
1375 static void ia32_codegen(void *self) {
1376 ia32_code_gen_t *cg = self;
1377 ir_graph *irg = cg->irg;
1379 ia32_gen_routine(cg, cg->isa->out, irg);
1383 /* remove it from the isa */
1386 /* de-allocate code generator */
1387 del_set(cg->reg_set);
1391 static void *ia32_cg_init(be_irg_t *birg);
1393 static const arch_code_generator_if_t ia32_code_gen_if = {
1395 NULL, /* before abi introduce hook */
1398 ia32_before_sched, /* before scheduling hook */
1399 ia32_before_ra, /* before register allocation hook */
1400 ia32_after_ra, /* after register allocation hook */
1401 ia32_finish, /* called before codegen */
1402 ia32_codegen /* emit && done */
1406 * Initializes a IA32 code generator.
1408 static void *ia32_cg_init(be_irg_t *birg) {
1409 ia32_isa_t *isa = (ia32_isa_t *)birg->main_env->arch_env->isa;
1410 ia32_code_gen_t *cg = xcalloc(1, sizeof(*cg));
1412 cg->impl = &ia32_code_gen_if;
1413 cg->irg = birg->irg;
1414 cg->reg_set = new_set(ia32_cmp_irn_reg_assoc, 1024);
1415 cg->arch_env = birg->main_env->arch_env;
1418 cg->blk_sched = NULL;
1419 cg->fp_kind = isa->fp_kind;
1420 cg->used_fp = fp_none;
1421 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
1423 FIRM_DBG_REGISTER(cg->mod, "firm.be.ia32.cg");
1425 /* copy optimizations from isa for easier access */
1427 cg->arch = isa->arch;
1428 cg->opt_arch = isa->opt_arch;
1434 if (isa->name_obst) {
1435 obstack_free(isa->name_obst, NULL);
1436 obstack_init(isa->name_obst);
1440 cur_reg_set = cg->reg_set;
1442 ia32_irn_ops.cg = cg;
1444 return (arch_code_generator_t *)cg;
1449 /*****************************************************************
1450 * ____ _ _ _____ _____
1451 * | _ \ | | | | |_ _|/ ____| /\
1452 * | |_) | __ _ ___| | _____ _ __ __| | | | | (___ / \
1453 * | _ < / _` |/ __| |/ / _ \ '_ \ / _` | | | \___ \ / /\ \
1454 * | |_) | (_| | (__| < __/ | | | (_| | _| |_ ____) / ____ \
1455 * |____/ \__,_|\___|_|\_\___|_| |_|\__,_| |_____|_____/_/ \_\
1457 *****************************************************************/
1460 * Set output modes for GCC
1462 static const tarval_mode_info mo_integer = {
1469 * set the tarval output mode of all integer modes to decimal
1471 static void set_tarval_output_modes(void)
1475 for (i = get_irp_n_modes() - 1; i >= 0; --i) {
1476 ir_mode *mode = get_irp_mode(i);
1478 if (mode_is_int(mode))
1479 set_tarval_mode_output_option(mode, &mo_integer);
1483 const arch_isa_if_t ia32_isa_if;
1486 * The template that generates a new ISA object.
1487 * Note that this template can be changed by command line
1490 static ia32_isa_t ia32_isa_template = {
1492 &ia32_isa_if, /* isa interface implementation */
1493 &ia32_gp_regs[REG_ESP], /* stack pointer register */
1494 &ia32_gp_regs[REG_EBP], /* base pointer register */
1495 -1, /* stack direction */
1496 NULL, /* main environment */
1498 NULL, /* 16bit register names */
1499 NULL, /* 8bit register names */
1503 IA32_OPT_INCDEC | /* optimize add 1, sub 1 into inc/dec default: on */
1504 IA32_OPT_DOAM | /* optimize address mode default: on */
1505 IA32_OPT_LEA | /* optimize for LEAs default: on */
1506 IA32_OPT_PLACECNST | /* place constants immediately before instructions, default: on */
1507 IA32_OPT_IMMOPS | /* operations can use immediates, default: on */
1508 IA32_OPT_PUSHARGS), /* create pushs for function argument passing, default: on */
1509 arch_pentium_4, /* instruction architecture */
1510 arch_pentium_4, /* optimize for architecture */
1511 fp_sse2, /* use sse2 unit */
1512 NULL, /* current code generator */
1513 NULL, /* output file */
1515 NULL, /* name obstack */
1516 0 /* name obst size */
1521 * Initializes the backend ISA.
1523 static void *ia32_init(FILE *file_handle) {
1524 static int inited = 0;
1530 set_tarval_output_modes();
1532 isa = xmalloc(sizeof(*isa));
1533 memcpy(isa, &ia32_isa_template, sizeof(*isa));
1535 ia32_register_init(isa);
1536 ia32_create_opcodes();
1537 ia32_register_copy_attr_func();
1539 if ((ARCH_INTEL(isa->arch) && isa->arch < arch_pentium_4) ||
1540 (ARCH_AMD(isa->arch) && isa->arch < arch_athlon))
1541 /* no SSE2 for these cpu's */
1542 isa->fp_kind = fp_x87;
1544 if (ARCH_INTEL(isa->opt_arch) && isa->opt_arch >= arch_pentium_4) {
1545 /* Pentium 4 don't like inc and dec instructions */
1546 isa->opt &= ~IA32_OPT_INCDEC;
1549 isa->regs_16bit = pmap_create();
1550 isa->regs_8bit = pmap_create();
1551 isa->types = pmap_create();
1552 isa->tv_ent = pmap_create();
1553 isa->out = file_handle;
1554 isa->cpu = ia32_init_machine_description();
1556 ia32_build_16bit_reg_map(isa->regs_16bit);
1557 ia32_build_8bit_reg_map(isa->regs_8bit);
1559 /* patch register names of x87 registers */
1560 ia32_st_regs[0].name = "st";
1561 ia32_st_regs[1].name = "st(1)";
1562 ia32_st_regs[2].name = "st(2)";
1563 ia32_st_regs[3].name = "st(3)";
1564 ia32_st_regs[4].name = "st(4)";
1565 ia32_st_regs[5].name = "st(5)";
1566 ia32_st_regs[6].name = "st(6)";
1567 ia32_st_regs[7].name = "st(7)";
1570 isa->name_obst = xmalloc(sizeof(*isa->name_obst));
1571 obstack_init(isa->name_obst);
1574 ia32_handle_intrinsics();
1575 ia32_switch_section(isa->out, NO_SECTION);
1577 /* needed for the debug support */
1578 ia32_switch_section(isa->out, SECTION_TEXT);
1579 fprintf(isa->out, ".Ltext0:\n");
1589 * Closes the output file and frees the ISA structure.
1591 static void ia32_done(void *self) {
1592 ia32_isa_t *isa = self;
1594 /* emit now all global declarations */
1595 ia32_gen_decls(isa->out, isa->arch_isa.main_env);
1597 pmap_destroy(isa->regs_16bit);
1598 pmap_destroy(isa->regs_8bit);
1599 pmap_destroy(isa->tv_ent);
1600 pmap_destroy(isa->types);
1603 obstack_free(isa->name_obst, NULL);
1611 * Return the number of register classes for this architecture.
1612 * We report always these:
1613 * - the general purpose registers
1614 * - the SSE floating point register set
1615 * - the virtual floating point registers
1617 static int ia32_get_n_reg_class(const void *self) {
1622 * Return the register class for index i.
1624 static const arch_register_class_t *ia32_get_reg_class(const void *self, int i) {
1625 assert(i >= 0 && i < 3 && "Invalid ia32 register class requested.");
1627 return &ia32_reg_classes[CLASS_ia32_gp];
1629 return &ia32_reg_classes[CLASS_ia32_xmm];
1631 return &ia32_reg_classes[CLASS_ia32_vfp];
1635 * Get the register class which shall be used to store a value of a given mode.
1636 * @param self The this pointer.
1637 * @param mode The mode in question.
1638 * @return A register class which can hold values of the given mode.
1640 const arch_register_class_t *ia32_get_reg_class_for_mode(const void *self, const ir_mode *mode) {
1641 const ia32_isa_t *isa = self;
1642 if (mode_is_float(mode)) {
1643 return USE_SSE2(isa) ? &ia32_reg_classes[CLASS_ia32_xmm] : &ia32_reg_classes[CLASS_ia32_vfp];
1646 return &ia32_reg_classes[CLASS_ia32_gp];
1650 * Get the ABI restrictions for procedure calls.
1651 * @param self The this pointer.
1652 * @param method_type The type of the method (procedure) in question.
1653 * @param abi The abi object to be modified
1655 static void ia32_get_call_abi(const void *self, ir_type *method_type, be_abi_call_t *abi) {
1656 const ia32_isa_t *isa = self;
1659 unsigned cc = get_method_calling_convention(method_type);
1660 int n = get_method_n_params(method_type);
1663 int i, ignore_1, ignore_2;
1665 const arch_register_t *reg;
1666 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
1668 unsigned use_push = !IS_P6_ARCH(isa->opt_arch);
1670 /* set abi flags for calls */
1671 call_flags.bits.left_to_right = 0; /* always last arg first on stack */
1672 call_flags.bits.store_args_sequential = use_push;
1673 /* call_flags.bits.try_omit_fp not changed: can handle both settings */
1674 call_flags.bits.fp_free = 0; /* the frame pointer is fixed in IA32 */
1675 call_flags.bits.call_has_imm = 1; /* IA32 calls can have immediate address */
1677 /* set stack parameter passing style */
1678 be_abi_call_set_flags(abi, call_flags, &ia32_abi_callbacks);
1680 /* collect the mode for each type */
1681 modes = alloca(n * sizeof(modes[0]));
1683 for (i = 0; i < n; i++) {
1684 tp = get_method_param_type(method_type, i);
1685 modes[i] = get_type_mode(tp);
1688 /* set register parameters */
1689 if (cc & cc_reg_param) {
1690 /* determine the number of parameters passed via registers */
1691 biggest_n = ia32_get_n_regparam_class(n, modes, &ignore_1, &ignore_2);
1693 /* loop over all parameters and set the register requirements */
1694 for (i = 0; i <= biggest_n; i++) {
1695 reg = ia32_get_RegParam_reg(n, modes, i, cc);
1696 assert(reg && "kaputt");
1697 be_abi_call_param_reg(abi, i, reg);
1704 /* set stack parameters */
1705 for (i = stack_idx; i < n; i++) {
1706 /* parameters on the stack are 32 bit aligned */
1707 be_abi_call_param_stack(abi, i, 4, 0, 0);
1711 /* set return registers */
1712 n = get_method_n_ress(method_type);
1714 assert(n <= 2 && "more than two results not supported");
1716 /* In case of 64bit returns, we will have two 32bit values */
1718 tp = get_method_res_type(method_type, 0);
1719 mode = get_type_mode(tp);
1721 assert(!mode_is_float(mode) && "two FP results not supported");
1723 tp = get_method_res_type(method_type, 1);
1724 mode = get_type_mode(tp);
1726 assert(!mode_is_float(mode) && "mixed INT, FP results not supported");
1728 be_abi_call_res_reg(abi, 0, &ia32_gp_regs[REG_EAX]);
1729 be_abi_call_res_reg(abi, 1, &ia32_gp_regs[REG_EDX]);
1732 const arch_register_t *reg;
1734 tp = get_method_res_type(method_type, 0);
1735 assert(is_atomic_type(tp));
1736 mode = get_type_mode(tp);
1738 reg = mode_is_float(mode) ? &ia32_vfp_regs[REG_VF0] : &ia32_gp_regs[REG_EAX];
1740 be_abi_call_res_reg(abi, 0, reg);
1745 static const void *ia32_get_irn_ops(const arch_irn_handler_t *self, const ir_node *irn) {
1746 return &ia32_irn_ops;
1749 const arch_irn_handler_t ia32_irn_handler = {
1753 const arch_irn_handler_t *ia32_get_irn_handler(const void *self) {
1754 return &ia32_irn_handler;
1757 int ia32_to_appear_in_schedule(void *block_env, const ir_node *irn) {
1758 return is_ia32_irn(irn) ? 1 : -1;
1762 * Initializes the code generator interface.
1764 static const arch_code_generator_if_t *ia32_get_code_generator_if(void *self) {
1765 return &ia32_code_gen_if;
1769 * Returns the estimated execution time of an ia32 irn.
1771 static sched_timestep_t ia32_sched_exectime(void *env, const ir_node *irn) {
1772 const arch_env_t *arch_env = env;
1773 return is_ia32_irn(irn) ? ia32_get_op_estimated_cost(arch_get_irn_ops(arch_env, irn), irn) : 1;
1776 list_sched_selector_t ia32_sched_selector;
1779 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
1781 static const list_sched_selector_t *ia32_get_list_sched_selector(const void *self, list_sched_selector_t *selector) {
1782 memcpy(&ia32_sched_selector, selector, sizeof(ia32_sched_selector));
1783 ia32_sched_selector.exectime = ia32_sched_exectime;
1784 ia32_sched_selector.to_appear_in_schedule = ia32_to_appear_in_schedule;
1785 return &ia32_sched_selector;
1788 static const ilp_sched_selector_t *ia32_get_ilp_sched_selector(const void *self) {
1793 * Returns the necessary byte alignment for storing a register of given class.
1795 static int ia32_get_reg_class_alignment(const void *self, const arch_register_class_t *cls) {
1796 ir_mode *mode = arch_register_class_mode(cls);
1797 int bytes = get_mode_size_bytes(mode);
1799 if (mode_is_float(mode) && bytes > 8)
1804 static const be_execution_unit_t ***ia32_get_allowed_execution_units(const void *self, const ir_node *irn) {
1805 static const be_execution_unit_t *_allowed_units_BRANCH[] = {
1806 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH1],
1807 &ia32_execution_units_BRANCH[IA32_EXECUNIT_TP_BRANCH_BRANCH2],
1810 static const be_execution_unit_t *_allowed_units_GP[] = {
1811 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EAX],
1812 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBX],
1813 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ECX],
1814 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDX],
1815 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_ESI],
1816 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EDI],
1817 &ia32_execution_units_GP[IA32_EXECUNIT_TP_GP_GP_EBP],
1820 static const be_execution_unit_t *_allowed_units_DUMMY[] = {
1821 &be_machine_execution_units_DUMMY[0],
1824 static const be_execution_unit_t **_units_callret[] = {
1825 _allowed_units_BRANCH,
1828 static const be_execution_unit_t **_units_other[] = {
1832 static const be_execution_unit_t **_units_dummy[] = {
1833 _allowed_units_DUMMY,
1836 const be_execution_unit_t ***ret;
1838 if (is_ia32_irn(irn)) {
1839 ret = get_ia32_exec_units(irn);
1841 else if (is_be_node(irn)) {
1842 if (be_is_Call(irn) || be_is_Return(irn)) {
1843 ret = _units_callret;
1845 else if (be_is_Barrier(irn)) {
1860 * Return the abstract ia32 machine.
1862 static const be_machine_t *ia32_get_machine(const void *self) {
1863 const ia32_isa_t *isa = self;
1868 * Return irp irgs in the desired order.
1870 static ir_graph **ia32_get_irg_list(const void *self, ir_graph ***irg_list) {
1875 * Allows or disallows the creation of Psi nodes for the given Phi nodes.
1876 * @return 1 if allowed, 0 otherwise
1878 static int ia32_is_psi_allowed(ir_node *sel, ir_node *phi_list, int i, int j)
1880 ir_node *cmp, *cmp_a, *phi;
1883 /* we don't want long long an floating point Psi */
1884 #define IS_BAD_PSI_MODE(mode) (mode_is_float(mode) || get_mode_size_bits(mode) > 32)
1886 if (get_irn_mode(sel) != mode_b)
1889 cmp = get_Proj_pred(sel);
1890 cmp_a = get_Cmp_left(cmp);
1891 mode = get_irn_mode(cmp_a);
1893 if (IS_BAD_PSI_MODE(mode))
1896 /* check the Phi nodes */
1897 for (phi = phi_list; phi; phi = get_irn_link(phi)) {
1898 ir_node *pred_i = get_irn_n(phi, i);
1899 ir_node *pred_j = get_irn_n(phi, j);
1900 ir_mode *mode_i = get_irn_mode(pred_i);
1901 ir_mode *mode_j = get_irn_mode(pred_j);
1903 if (IS_BAD_PSI_MODE(mode_i) || IS_BAD_PSI_MODE(mode_j))
1907 #undef IS_BAD_PSI_MODE
1912 static ia32_intrinsic_env_t intrinsic_env = {
1913 NULL, /**< the irg, these entities belong to */
1914 NULL, /**< entity for first div operand (move into FPU) */
1915 NULL, /**< entity for second div operand (move into FPU) */
1916 NULL, /**< entity for converts ll -> d */
1917 NULL, /**< entity for converts d -> ll */
1921 * Returns the libFirm configuration parameter for this backend.
1923 static const backend_params *ia32_get_libfirm_params(void) {
1924 static const opt_if_conv_info_t ifconv = {
1925 4, /* maxdepth, doesn't matter for Psi-conversion */
1926 ia32_is_psi_allowed /* allows or disallows Psi creation for given selector */
1928 static const arch_dep_params_t ad = {
1929 1, /* also use subs */
1930 4, /* maximum shifts */
1931 31, /* maximum shift amount */
1933 1, /* allow Mulhs */
1934 1, /* allow Mulus */
1935 32 /* Mulh allowed up to 32 bit */
1937 static backend_params p = {
1938 NULL, /* no additional opcodes */
1939 NULL, /* will be set later */
1940 1, /* need dword lowering */
1941 ia32_create_intrinsic_fkt,
1942 &intrinsic_env, /* context for ia32_create_intrinsic_fkt */
1943 NULL, /* will be set later */
1947 p.if_conv_info = &ifconv;
1952 /* instruction set architectures. */
1953 static const lc_opt_enum_int_items_t arch_items[] = {
1954 { "386", arch_i386, },
1955 { "486", arch_i486, },
1956 { "pentium", arch_pentium, },
1957 { "586", arch_pentium, },
1958 { "pentiumpro", arch_pentium_pro, },
1959 { "686", arch_pentium_pro, },
1960 { "pentiummmx", arch_pentium_mmx, },
1961 { "pentium2", arch_pentium_2, },
1962 { "p2", arch_pentium_2, },
1963 { "pentium3", arch_pentium_3, },
1964 { "p3", arch_pentium_3, },
1965 { "pentium4", arch_pentium_4, },
1966 { "p4", arch_pentium_4, },
1967 { "pentiumm", arch_pentium_m, },
1968 { "pm", arch_pentium_m, },
1969 { "core", arch_core, },
1971 { "athlon", arch_athlon, },
1972 { "athlon64", arch_athlon_64, },
1973 { "opteron", arch_opteron, },
1977 static lc_opt_enum_int_var_t arch_var = {
1978 &ia32_isa_template.arch, arch_items
1981 static lc_opt_enum_int_var_t opt_arch_var = {
1982 &ia32_isa_template.opt_arch, arch_items
1985 static const lc_opt_enum_int_items_t fp_unit_items[] = {
1987 { "sse2", fp_sse2 },
1991 static lc_opt_enum_int_var_t fp_unit_var = {
1992 &ia32_isa_template.fp_kind, fp_unit_items
1995 static const lc_opt_enum_int_items_t gas_items[] = {
1996 { "linux", ASM_LINUX_GAS },
1997 { "mingw", ASM_MINGW_GAS },
2001 static lc_opt_enum_int_var_t gas_var = {
2002 (int *)&asm_flavour, gas_items
2005 static const lc_opt_table_entry_t ia32_options[] = {
2006 LC_OPT_ENT_ENUM_INT("arch", "select the instruction architecture", &arch_var),
2007 LC_OPT_ENT_ENUM_INT("opt", "optimize for instruction architecture", &opt_arch_var),
2008 LC_OPT_ENT_ENUM_INT("fpunit", "select the floating point unit", &fp_unit_var),
2009 LC_OPT_ENT_NEGBIT("noaddrmode", "do not use address mode", &ia32_isa_template.opt, IA32_OPT_DOAM),
2010 LC_OPT_ENT_NEGBIT("nolea", "do not optimize for LEAs", &ia32_isa_template.opt, IA32_OPT_LEA),
2011 LC_OPT_ENT_NEGBIT("noplacecnst", "do not place constants", &ia32_isa_template.opt, IA32_OPT_PLACECNST),
2012 LC_OPT_ENT_NEGBIT("noimmop", "no operations with immediates", &ia32_isa_template.opt, IA32_OPT_IMMOPS),
2013 LC_OPT_ENT_NEGBIT("nopushargs", "do not create pushs for function arguments", &ia32_isa_template.opt, IA32_OPT_PUSHARGS),
2014 LC_OPT_ENT_ENUM_INT("gasmode", "set the GAS compatibility mode", &gas_var),
2017 #endif /* WITH_LIBCORE */
2019 const arch_isa_if_t ia32_isa_if = {
2022 ia32_get_n_reg_class,
2024 ia32_get_reg_class_for_mode,
2026 ia32_get_irn_handler,
2027 ia32_get_code_generator_if,
2028 ia32_get_list_sched_selector,
2029 ia32_get_ilp_sched_selector,
2030 ia32_get_reg_class_alignment,
2031 ia32_get_libfirm_params,
2032 ia32_get_allowed_execution_units,
2037 void be_init_arch_ia32(void)
2039 lc_opt_entry_t *be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2040 lc_opt_entry_t *ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2042 lc_opt_add_table(ia32_grp, ia32_options);
2043 be_register_isa_if("ia32", &ia32_isa_if);
2046 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_ia32);